CMOS Single Chip Fast Frequency Hopping Synthesizers For Wireless Multi-Gigahertz Applications

CMOS SINGLE CHIP FAST FREQUENCY
HOPPING SYNTHESIZERS FOR WIRELESS

MULTI-GIGAHERTZ APPLICATIONS
ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES

Consulting Editor: Mohammed Ismail. Ohio State University
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ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V
Chatterjee, S., Kinget, P., Tsividis, Y., Pun, K.P.
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IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS
Chen, Sao-Jie, Hsieh, Yong-Hsiang
ISBN-10: 1-4020-5082-8
LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES
Haartman, Martin v., stling, Mikael
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THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS
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PRECISION TEMPERATURE SENSORS IN CMOS TECHNOLOGY
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CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS
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CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM
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CMOS Single Chip Fast Frequency

Hopping Synthesizers for Wireless
Multi-Gigahertz Applications
Design Methodology, Analysis, and Implementation
By
TAOUFIK BOURDI
Beceem Communications Inc., Santa Clara, California, USA
and
IZZET KALE
Westminster University, London, UK and Eastern Mediterranean University,
Famagusta, North Cyprus
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN-10
ISBN-13
ISBN-10
ISBN-13
1-4020-5927-2 (HB)
978-1-4020-5927-8 (HB)
1-4020-5928-5 (e-book)
978-1-4020-5928-5 (e-book)
Published by Springer,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
www.springer.com
Printed on acid-free paper
All Rights Reserved

2007 Springer
No part of this work may be reproduced, stored in a retrieval system, or transmitted
in any form or by any means, electronic, mechanical, photocopying, microfilming, recording
or otherwise, without written permission from the Publisher, with the exception
of any material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work.
Contents
Preface
Nomenclature
ix
xi
1 INTRODUCTION
1.1 Introduction
1.2 Research Contribution
2 WIRELESS COMMUNICATION SYSTEMS
2.1 Introduction
2.2 The WLAN Standards
2.3 WLAN Transceiver Systems
2.3.1 The Transmitter
2.3.2 The Receiver
2.3.3 The Frequency Synthesizer (Local Oscillator)
3 PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS
3.1 Introduction
3.2 Phase-Locked Loop Frequency Synthesizer
3.2.1 Phase-Locked Loop Main Blocks
3.2.1.1 Phase-Frequency Detector
3.2.1.2 Charge Pump
3.2.1.3 Voltage-Controlled Oscillator
3.2.1.4 Voltage-Controlled Crystal Oscillator
3.2.1.5 Dividers
3.3 Phase-Locked Loop Parameters
3.3.1 Loop Filter Design
1
2
7
7
8
10
12
12
13
15
15
15
16
16
17
18
19
19
19
20
vi
Contents
3.4 Noise in Phase-Locked Loops
3.4.1 Component Noise Models
3.4.1.1 Reference Oscillator and VCO Phase Noise
3.4.1.2 Charge Pump Current Noise
3.4.1.3 Loop Filter Resistor Noise
3.4.1.4 Main Divider Noise
3.4.1.5 Phase-Frequency Detector Phase Noise
3.4.1.6 Overall Phase Noise Contribution
3.5 Fractional-N Synthesizers
3.5.1 '6 Modulators in Frequency Synthesizers
3.5.1.1 Fractional-N Case Study
3.6 RMS Phase Error (Irms) and Error Vector Magnitude
3.7 Conclusion
27
29
30
30
30
31
31
32
34
36
39
41
42
4 SYSTEM SIMULATION OF '6-BASED FRACTIONAL-N

SYNTHESIZERS
45
4.1 Introduction
4.2 Phase-Domain Model
4.2.1 A Constituent Blocks Behavioral Models
4.2.1.1 The Reference Oscillator
4.2.1.2 The '6 Modulator/Feedback Integer Divider
4.2.1.3 The VCO
4.2.1.4 The PFD/CP
4.2.1.5 The Loop Filter
4.2.2 Noise Modeling Summary
4.3 Synthesizer Platform Evaluation
4.3.1 Dithering Effect
4.3.2 Close-to-Integer Operation
4.3.3 Noise Folding
4.3.4 Effect of Prescaler Divider
4.4 Conclusion
45
46
50
50
50
51
52
52
52
53
57
60
60
62
65
5 MULTIMODE '6-BASED FRACTIONAL-N FREQUENCY

SYNTHESIZER
67
5.1 Introduction
5.2 An overview
5.3 A Multimode Multistandard '6-Based PLL Synthesizer Design
5.3.1 Design Methodology
5.4 The '6 Frequency Synthesizer SubBlocks Implementation
5.4.1 The Phase-Frequency Detector
5.4.2 The Charge Pump
5.4.2.1 Dead-Zone Nonlinearity
5.4.2.2 Linear Range and Cycle Slipping
67
67
69
69
71
71
73
76
78
Contents
vii
5.4.2.3 DC Offset Current

78
5.4.2.4 PFD/CP Transient Simulation
82
5.4.3 3.6 GHz Voltage-Controlled Oscillator
85
5.4.4 The Multimodulus Divider
89
5.4.4.1 MMD Operation
90
5.4.5 The Fractional Noise Shaping Coder (the '6 Modulator)
90
5.4.5.1 The Digital Accumulator and the First-Order Linear Model
90
5.4.5.2 The 30-bit Structural MASH Coder Implementation
92
5.4.5.3 The 24-bit Pipelined Adder Design
93
5.4.5.4 Error Cancellation Algorithm
95
5.4.5.5 Design Issues: Limit Cycle Cancellation in Fractional Mode 97
5.4.5.6 Design Issue: Integer Mode and Close-to-Integer Option
99
5.5 Measured Performance of the Implemented Synthesizer
102
5.6 Summary and Conclusion
107
6 IMPROVED PERFORMANCE FRACTIONAL-N FREQUENCY
SYNTHESIZER
111
6.1 Introduction
6.2 Overview
6.3 DeltaSigma-Controlled Adaptive Charge Pump
6.3.1 PLL Gain and Phase Variations
6.3.2 Charge Pump System
6.4 Synthesizer Loop Calibration
6.5 Process Calibration I/C Slew Rate and RC Time Constant
6.6 VCO Tuning Gain Calibration
6.6.1 VCO Calibration Algorithm Description
6.6.1.1 'N Values
6.6.1.2 Summary of Tuning Algorithm Operation
6.7 Improved VCO Band Switching
6.8 Experimental Results
6.9 Comparison with Published Results
6.10 Conclusion
111
111
113
113
116
117
119
121
121
125
125
126
127
128
128
7 CONCLUSION AND FURTHER WORK

7.1 Conclusion
7.2 Further Work
131
131
132
APPENDIX A
PHASE-FREQUENCY DETECTORS AND CHARGE PUMPS
135
135
1 Phase-Frequency Detectors
2 Charge Pump
3 PFD/CP Characteristics
135
138
140
viii
Contents
APPENDIX B
CONTROLLED OSCILLATORS
1 Reference Oscillators
1.1 Voltage-Controlled Crystal Oscillator
1.2 Temperature-Compensated Crystal Oscillator
2 Voltage-Controlled Oscillators
2.1 Voltage-Controlled Oscillators: Phase Noise Analysis
2.2 VCO Design Methodology
2.2.1
VCO Design
2.2.2
Phase Noise Optimization
143
143
143
143
145
146
146
149
150
153
APPENDIX C
PHASE NOISE
157
157
1
2
3
4
Calculation of Global Phase Error From L(f)

Phase Noise and Phase Modulation
RMS Phase Error From Phase Noise
Residual FM
157
159
161
163
APPENDIX D
FREQUENCY DIVIDERS
1 Reference Divider
1.1 Synchronous Dividers
1.2 Asynchronous Reference Frequency Divider
2 Feedback Divider
2.1 Specification and Different Architecture Evaluation
2.1.1
Direct Division versus Prescaler Method
3 High-Speed CMOS Divider Design
3.1 Current-Mode Logic Design: An Overview
4 Implemented CML Gates
165
165
165
165
166
168
168
168
177
178
183
APPENDIX E
PROGRAMS AND CODES
1 MathcadTM Program used for the Simulations
of all the Mathcad Figures
2 MatlabTM Program used for the Simulations
of the Fractional-N PLL Noise Spectrum
187
187
INDEX
207
187
198
Preface
Frequency synthesizers are at the heart of the each transmitter/receiver

system. Almost every communications consumer product employs a frequency
synthesizer often operating as a local oscillator providing the carrier frequency of interest. Mobile phones, radios, and televisions are a few among
the many applications that incorporate frequency synthesizers.
Recently, wireless local area network (WLAN) standards have emerged
in the market. Those standards operate in various frequency ranges. To reduce
component count, it is of importance to design a multimode frequency
synthesizer that serves all WLAN standards including 802.11a, b, and g
standards. With different specifications for those standards, designing
integer- based phase-locked loop frequency synthesizers can not be
achieved. Fractional-N frequency synthesizers offer the solution required for
a common multimode local oscillator. Those fractional-N synthesizers are
based on deltasigma modulators which in combination with a divider yield
the fractional division required for the desired frequency of interest.
In this book, the authors outline detailed design methodology for fast
frequency hopping synthesizers for radio frequency (RF) and wireless
communications applications. Great emphasis on fractional-N deltasigmabased phase-locked loops from specifications, system analysis, and architecture planning to circuit design and silicon implementation.
The book describes an efficient design and characterization methodology
that has been developed to study loop trade-offs in both open- and closeloop modeling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated subblocks of the
chosen frequency synthesizer. The platform predicts accurately the phase
noise, spurious and switching performance of the final design. Therefore,
ix
Preface
excellent phase noise and spurious performance can be achieved while

meeting all the specified requirements. The design methodology reduces the
need for silicon re-spin enabling circuit designers to directly meet cost,
performance, and schedule milestones.
The developed knowledge and techniques have been used in the
successful design and implementation of two high-speed multimode
fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards.
Both synthesizer designs are described in details.
NOMENCLATURE
DC
DCOC
DFF
DGA
Div
DMD
D-S
DSC
DSSS
EVM
F
FDC
FOM
IC
IF
Inv
IP
Absolute Tolerance (CadenceTM specific)

Alternating Current
Analog-to-digital converter
Application-Specific Integrated Circuit
Balanced to unbalanced
Bit Error Rate
Complementary CodeKeying
Carry Look-Ahead
Current-Mode Logic
Charge Pump
Digital-to-analog converter
Decibels per Hertz, SSB Phase Noise PSD Relative to the
Carrier
Direct Current
DC Offset Cancellation
Data-type Flip-Flop
Digitally Controlled Variable-Gain Amplifier
Divider
Dual-Modulus Divider
DeltaSigma
Differential to Single-Ended Converter
Direct-Sequence Spread Spectrum
Error Vector Magnitude
Noise Figure
Frequency to Digital Converter
Figure of Merit
Initial Condition
Intermediate Frequency
Inverter
Intellectual Property
L(f)
LF
LPF
LTI
LTV
LUT
MC
MLF
Single-Sideband Phase Noise

Loop Filter
Low-Pass Filter
Linear Time Invariant
Linear Time Variant
Lookup Table
Modulus Control
Micro-Lead Frame
abstol
AC
ADC
ASIC
Balun
BER
CCK
CLA
CML
CP
DAC
dBc/Hz
xi
xii
Nomenclature
MMD
NTC
PA
PCB
PFD
PLL
PRBS
PSD
PSDMD
PVT
QAM
QPSK
Ref
Multimodulus Divider
Negative Temperature Coefficient Capacitor
Power Amplifier
Printed Circuit Board
Phase-Frequency Detector
Phase-Locked Loop
Pseudorandom Binary Sequence
Power Spectral Density
Phase Switching Dual-Modulus Divider
Process Voltage Temperature
Quadrature-Amplitude Modulation
Quadrature Phase-Shift Keying
Reference
Reltol
RF
RFIC
Rx
SS
SSB
SSBN
SSBPSD
TCXO
TDC
TFF
TRx
Tx
VCO
VCXO
VGA
Vtune
WLAN
Relative Tolerance (Cadence specific)

Radio Frequency
Radio Frequency Integrated Circuit
Receiver
Steady State
Single Sideband
Single-Sideband Noise
Single-Sideband Power Spectral Density
Temperature-Compensated Crystal Oscillator
Time to Digital Converter
Toggle Flip-Flop
Transceiver
Transmitter
Voltage-Controlled Oscillator
Voltage-Controlled Crystal Oscillator
Variable-Gain Amplifier
VCO Tuning Voltage
Wireless Local Area Network
TM
Chapter 1
INTRODUCTION
Outline and Contributions
1.1
INTRODUCTION
Frequency synthesizers are used as local oscillators in all transceiver

systems. It is paramount that those frequency synthesizers are low noise
as their behavior affects the entire performance of the transmission
system. The work presented in this monograph focuses on the research,
study, and improved design and implementation of low-noise frequency
synthesizers for multimode wireless local area network (WLAN)
applications covering all IEEE802.11a, b, and g standards. Performed
measurements on those synthesizers show the low noise obtained by
the design presented in this work. Complete test results highlighting
the superior behavior of the designed synthesizers are shown in both
chapters 5 and 6.
In chapter 2, a brief description of those standards is presented in
terms of their relevance to radio frequency transmission. An adequate
transceiver that operates in all WLAN modes is also described and its
transmitter/receiver chains are detailed. Architecture for the frequency
synthesizer acting as a local oscillator for the transceiver is proposed.
Direct frequency synthesis is not used to avoid frequency pulling in
the transceiver [1].
In chapter 3, detailed analyses of integer and fractional-N phaselocked loops (PLL) frequency synthesizers are treated. Open-loop and
closed-loop transfer functions of the PLL are derived. Noise contributions of individual subblocks of the synthesizers are detailed. Loop
filter design is also included. The derived equations form the basis for
Chapter 1
the optimum design and implementation of the designed and implemented frequency synthesizer chips described in this book.
The behavioral modeling for the proposed fractional-N delta
Sigma ('6-based PLL is carried out in chapter 4 to check for
architectural limitations, identify dominant noise sources, automate
loop filter optimization, and generate phase-frquency detector/charge
pump (PFD/CP) linearity specifications. Also, a phase-domain model
of the proposed architecture is constructed using The CadenceTM
Verilog-A Language. The model combines the voltage-controlled
oscillator (VCO), reference, and divider integrators into one resettable
integrator within the PFD. The '6 modulator model is also included.
The divider adds '6 noise to the frequency variable, then divides the
sum by the average divide ratio. The simulation results obtained in
this chapter contribute to the optimum design and implementation of
fractional-N synthesizers presented in this monograph.
In chapter 5, simulation results presented in chapter 4 are used for
the optimum chip design of a multimode frequency synthesizer for the
WLAN standards. Unconditionally stable '6 modulators of the
third-order (namely MASH-1-1-1) are implemented and employed in
a PLL fractional-N synthesizer providing a good average estimate for
fractional-N dividers. Using a deep submicron 0.18 Pm complementary
metal-oxide semiconductor (CMOS) process with a supply voltage of
1.8 V, a '6-based fractional-N synthesizer is designed, simulated,
laid out, fabricated, and tested.
In chapter 6, additional circuit designs are proposed and
incorporated to enhance the performance of the synthesizer at the cost
of increased circuit complexity. Those additions include adaptive
charge pump (CP) architecture to maintain loop gain and phase
transfer functions while operating in fractional mode. Another circuit
proposal is that of an adaptive band switching control to maintain
frequency agility while offering optimum phase noise performance in
the band of interest.
The conclusion in chapter 7 wraps up the research monograph by
describing the achievement of the work presented and offers
suggestions for future work.
1.2
RESEARCH CONTRIBUTION
The main contributions of the work presented in this book are the
research, study, design, and implementation of two fractional-N
Introduction
frequency synthesizers. Both synthesizers are incorporated in a

multimode transceiver system and operate in all WLAN standards
802.11a, b, and g. The synthesizers designed and built have a unique
architecture that avoids frequency pulling1 in the transceiver and it is
based on the indirect frequency synthesis of the desired frequencies
of interest. The first synthesizer is based on a conventional '6based fractional-N frequency synthesizer that has been thoroughly
investigated and modeled to achieve an outstanding phase noise and
spurious performance. The second synthesizer uses special circuit
design ideas to enhance the phase noise performance of the first
frequency synthesizer making it the most agile and the most adaptive
for many applications, modes of operations, and various wireless
standards.
The research work the authors have endeavored to produce was
culminated in the publication of several articles in international
conferences and journals and patents. Those are listed below.
1. T. Bourdi and I. Kale, On the Efficient Design and Characterization of
Multi-GHz '6 Fractional-N Frequency Synthesizer, IEEE Transaction
of Circuits and Systems CAS-I, Submitted April 2006.
2. T. Bourdi, A. Borjak, and I. Kale, A Modeling Platform for Efficient
Characterization of Phase-Locked Loop '6 Frequency Synthesizers,
IEEE International Symposium on Circuits and Systems, Kos Island
Greece, May 2006, pp. 32213224.
3. Z. Pengfei, L. Der, G. Dawei, I. Sever, T. Bourdi, C. Lam, A. Zolfaghari,
J. Chen, D. Gambetta, Baohong Cheng, S. Gowder, S. Hart, L. Huynh,
T. Nguyen, and B. Razavi, A Single-Chip Dual-Band Direct-Conversion
IEEE 802.11a/b/g WLAN Transceiver in 0.18-um CMOS, IEEE
Journal of Solid-State Circuits, 40 (9), Sept. 2005, pp. 19321939.
4. Z. Pengfei, L. Der, G. Dawei, I. Sever, T. Bourdi C. Lam, A. Zolfaghari,
J. Chen, D. Gambetta, B. Cheng, S. Gower, S. Hart, L. Huynh,
T. Nguyen, and B. Razavi, A CMOS Direct-Conversion Transceiver for
IEEE 802.11a/b/g WLANs, IEEE Custom Integrated Circuits
Conference, 36 Oct. 2004, pp. 409412.
Frequency pulling of the VCO is the frequency change due to nonideal load., i.e. change in
the load causes frequency change in the VCO (hence the term pulling). This is most severe
when the PA/TX frequency is directly related to the VCO frequency.
Chapter 1
5. T. Bourdi, A. Borjak, and I. Kale, A Novel DeltaSigma Based RF

Frequency Synthesizer Architecture For Cellular Applications, IEEE
Transactions of Instrumentation and Measurement, Under Review,
Submitted July 2003.
6. Z. Pengfei, N. Thai, C. Lam, D. Gambetta, C. Soorapanth, C. Baohong,
S. Hart, I. Sever, T. Bourdi, A. Tham, and B. Razavi, A 5-GHz DirectConversion CMOS Transceiver, IEEE Journal of Solid-State Circuits,
38 (12), Dec. 2003, pp. 22322238.
7. Z. Pengfei, N. Thai, C. Lam, D. Gambetta, C. Soorapanth, C. Baohong,
S. Hart, I. Sever, T. Bourdi, A. Tham, and B. Razavi, A Direct Conversion
CMOS Transceiver for IEEE 802.11a WLANs, Digest of International
Solid-State Circuit Conference, 2003, 1, pp. 354498.
8. T. Bourdi, A. Borjak, and I. Kale, Agile Multi-Band DeltaSigma
Frequency Synthesizer Architecture, IEEE International Symposium on
Circuits and Systems, ISCAS2002, May 2002, 5, pp. 413416.
9. T. Bourdi, A. Borjak, and I. Kale, A DeltaSigma Frequency Synthesizer
with Enhanced Phase Noise Performance, IEEE Instrumentation and
Measurement Technology Conference, May 2002, 1, pp. 247251.
10. A. Borjak and T. Bourdi, Intermodulation Products in a Mixer
Subjected to a Multi-Carrier Signal, Microwave Journal, 45 (2) Feb.
2002, pp. 130143.
11. M. Kozak, I. Kale, A. Borjak, T. Bourdi, A Pipelined All-Digital Delta
Sigma Modulator for Fractional-n Frequency Synthesis, IEEE
Instrumentation and Measurement Technology Conference, May 2000,
2, pp. 11531157.
12. T. Bourdi, A. Borjak, and D. Gambetta, Cell-Based Charge-Pump
Architecture for DeltaSigma Fractional-n Synthesizers, Resonext Patent,
Submitted Oct. 2001.
13. T. Bourdi and A. Borjak, A DeltaSigma Controlled Charge Pump
Architecture for Enhanced PLL Synthesizer Performance, Resonext
Patent, Submitted Mar. 2001.
14. T. Bourdi and A. Borjak, M. Henriksson, and I. Kale, A Novel Algorithm
for Effective Control of Fractional-n Synthesizers, Nokia Patent,
submitted Jan. 2000, Filed.
Introduction
REFERENCES
[1] J.A. Weldon, et al., A 1.75 GHz Highly-Integrated Narrow-Band
CMOS Transmitter with Harmonic-Rejection Mixers, IEEE Solid-State
Circuits Conference, 2001, Digest of Technical Papers, 2001 IEEE
International 57 Feb. 2001, pp. 160161, 442.
Chapter 2
WIRELESS COMMUNICATION SYSTEMS
An Overview
2.1
INTRODUCTION
With the turn of the new millennium, there has been an explosion in
the usage of wireless equipment. Wireless cellular devices like mobile
phones are now ubiquitous. Mobile Internet employing wireless
devices is now available in most coffee shops in many countries. Such
devices can achieve short-and medium-range coverage. Devices with
short-range coverage are based on communications standards like
Bluetooth [1], while medium-range coverage devices are based on the
wireless local area networks (WLAN) communications standards [2].
The latter are categorized under two bands 2.4 and 5 GHz. The lower
band is mainly based on the 802.11b standard and employs the
complementary code keying (CCK) modulation [2]. The higher band
(5 GHz) is based on the 802.11a standard and employs the orthogonal
frequency division multiplexing (OFDM) modulation. Recently, the
same OFDM modulation has been ported to the lower frequency of
2.4 GHz of 802.11b. This standard was termed 802.11g.
WLAN devices are now used in most indoor places from homes to
shops to offices. Such devices are incorporated in appliances like televisions, laptops, computers, telephones, PDAs, printers, etc. Figure 2-1
illustrates a typical usage where coverage is also shown.
The synthesizer described in this book is designed and implemented
for direct incorporation in to radio frequency integrated circuit (RFIC)
transceivers for all the WLAN standards (802.11a, b, and g). In this
chapter, a brief overview of those standards is given. An adequate
transceiver system for such standards is also described.
Chapter 2
Printer
Television
Computer
Internet
Laptop
WAN
Access Point
LAN
Computer
Telephone
PDA
Cellular
Tower
Figure 2-1. WLAN Usage
2.2
THE WLAN STANDARDS
As mentioned above the WLAN standards fall in two frequency

bands: the 2.4 GHz band (802.11b and 802.11g) and the 5 GHz band
(802.11a). Here is a brief description of those standards.
The 2.4 GHz 802.11 standards require a pass band of approximately
22 MHz wide for one operating network. Using direct sequence
spread-spectrum modulation (DSSS), the WLAN provides an 11
Mbps data rate to the network users. Thus, the 2.4 GHz bands 83.5
MHz supports three nonoverlapping, simultaneously operating WLAN
networks (66/83.5), and roughly 33 Mbps of data rate (11 Mbps *
three networks) to be shared among common users across the
coverage area as illustrated in Figure 2-2. This has been proven to
adequately distribute sufficient bandwidth to support the majority of
applications across many environments.
Wireless Communication Systems
Figure 2-2. Nonoverlapping and Overlapping US Channel Selection
Figure 2-3. OFDM Physical Layer Frequency Channel Plan Implementation for US Standards
10
Chapter 2
The 802.11a standard requires a 16.6 MHz pass band for one
operating network. The modulation technique allowed in 5 GHz
(orthogonal frequency division multiplexing (OFDM) with 64QAM
subcarriers) is more efficient than the spread spectrum techniques
WLAN uses (more bits/second/hertz), and provides up to 54 Mbps of
data rate to network users. For the US-based 802.11a standard, the 5
GHz unlicensed band covers 300 MHz of spectrum and therefore
supports 12 nonoverlapping, simultaneously operating networks, as
shown in Figure 2-3.
The 802.11g occupies similar frequency bands as the 802.11b,
however the single subcarrier is OFDM modulated as in the case of
802.11a. A summary of the main characteristics for all the WLAN
standards is shown in Table 2-1.
Table 2-1. WLAN Characteristics
Parameters
Frequency in GHz
802.11b
2.42.58
802.11g
2.42.58
Modulation
Data rate (Mbits/s)
DSSS CCK
1, 2, 5.5 & 11
Receiver sensitivity
(dBm)
Transmit power
(dBm)
Transmit EVM (dB)
74 @ 11 Mbps
OFDM
6, 9, 12, 18, 36, 48 &
54
65 @ 54 Mbps
802.11a
4.914.99 & 5.03
5.24 Japanese Bands
5.155.25 Lower
5.255.35 Middle
5.7255.825 Upper
OFDM
6, 9, 12, 18, 24, 36,
48 & 54
65 @ 54 Mbps
30
30
16, 23 & 29
25
25
2.3
WLAN TRANSCEIVER SYSTEMS
A basic diagram of a transceiver system used in the WLAN standards

is shown in Figures 2-4 and 2-5. It incorporates both base band and
radio frequency parts. The radio frequency part is common to all the
wireless standards (802.11a, b, and g) whereas the modem varies with
those standards. It provides both 2.4 and 5 GHz frequency bands for
the 802.11a, b, and g WLAN standards.
The transceiver incorporates both low frequency blocks like lowpass filters (LPF), variable-gain amplifiers (VGA) and high-frequency
blocks like mixers, a low-noise amplifier (LNA), a power amplifier
11
Figure 2-4. Transceiver System
Figure 2-5. WLAN Transceiver Architecture
(PA), and frequency synthesizers acting as local oscillators (LO). In

this book, emphasis is made on the research, design, and implementation
of those frequency synthesizers. The transceiver is conventionally divided into two paths: the transmitter and the receiver both incorporating
the local oscillator treated here. All those blocks are described below.
12
2.3.1
Chapter 2
The Transmitter
A detailed transmitter chain block diagram is shown in Figure 2-6.

The shown LPF are preceded by digital-to-analog converters (DAC)
that are implemented on the base band part of the transceiver chip.
Those image quality (IQ) filters are used for signal reconstruction. The
base-band signal level can be adjusted through a digitally controlled
VGA. The modulated base-band signal is then up-converted to either
5 GHz or 2 GHz. The two front-end signal paths take the same circuit
topology. Each cut is independently optimized for its own frequency
band. The upconverted differential signal is subsequently transformed
to a single-ended version by an active differential to single-ended
conversion (DSC) circuit to obviate the need for an external BALUN
(balanced to unbalanced transformer).
Figure 2-6. Transmitter Signal Path for the WLAN Transceiver
2.3.2
The Receiver
Figure 2-7 shows the receiver chain block diagram. The shared
receiver base-band section consists of a buffer amplifier, a digitally
controlled VGA, an LPF and an output buffer (A2) whose gain can be
adjusted. The base-band section of the Q-channel is identical, not
shown here for brevity.
The channel selection LPF is designed for its rapid increase of
attenuation outside the pass band, and thus a narrow transition band. A
nominal cutoff frequency of 8.7 MHz is automatically calibrated to
account for process variations. This satisfies the channel selection
requirement for 802.11a, b, and g standards. Due to a significantly
13
more severe adjacent channel rejection requirement, higher rejection

ratio at lower base-band signal frequency is needed for CCK modulation
in 802.11b mode. This extra filtering is implemented in the digital
domain.
Figure 2-7. Receiver Chain for WLAN Transceiver
Included in the receiver is a low-flicker noise mixer [3], active-LC

preselection notch filter (F1) and the look-up table (LUT)-based DC
offset compensation [4]. WLAN applications require the receiver to
accommodate an input signal range from a few microvolts to tens of
millivolts, often demanding two or more gain stages in the (LNA).
The radio frequency (RF) front-end circuits for both frequency
bands use exactly the same topology with independently sized devices.
The only difference is that a direct bypass across the LNA has been
implemented in 2 GHz to accommodate the even higher input power
requirement for 802.11b.
2.3.3
The Frequency Synthesizer (Local Oscillator)
In a direct conversion transceiver, the required local oscillation (LO)

frequency coincides with the RF, which entails adverse effects such
as LORF interaction and VCO frequency pulling [5]. The LO
generation scheme used consists of a quadrature VCO operating at
two-thirds of the LO frequency and a divide-by-2 circuit producing
quadrature outputs at one-third of the LO frequency. Two quadrature
mixers subsequently multiply the VCO signal by the divide-by-2
signal to generate the quadrature LO signals (upper band), with
significant suppression of the undesired lower band at one-third of the
LO frequency, alleviating the image problem in the receiver and the
spurious emission problem in the transmitter.
14
Chapter 2
Figure 2-8. Local Oscillator Frequency Synthesizer For WLAN Transceiver
The quadrature LO signals for 2 GHz band are then generated by

dividing the 5-GHz LO signal by two as shown in Figure 2-8. Two
quadrature VCOs are used (VCO1: 3.23.6 GHz, VCO2: 3.53.9
GHz) in order to cover the required frequency range with enough
margins for process, voltage, and temperature (PVT) variations.
REFERENCES
[1] IEEE Bluetooth Drafts Standards, http://grouper.ieee.org/groups/Bluetooth/
[2] IEEE 802.11 Drafts Standards, http://grouper.ieee.org/groups/802/11/
[3] G. Chien et al., A 2.4 GHz CMOS Transceiver and Baseband Processor
Chipset for 802.11b Wireless LAN Application, IEEE International
Solid-State Circuits Conference Digest of Technical Papers, Feb. 2003,
pp. 356357.
[4] B. Razavi and P. Zhang, Mixer Noise Reduction Technique, US
Patent, 6,748,204, June 2004.
CMOS Transmitter with Harmonic-Rejection Mixers, IEEE Solid-State
Circuits Conference, 2001. Digest of Technical Papers, 2001 IEEE
Chapter 3
PHASE-LOCKED LOOP FREQUENCY
SYNTHESIZERS
Principles, Analyses, and Design
3.1
INTRODUCTION
In this chapter, detailed analyses of PLL frequency synthesizers are

treated. Both integer and '6-based fractional-N are considered.
Open-loop and Closed-loop gain and phase equations are derived and
phase noise theory is introduced. Gain and noise contributions of
individual subblocks of the synthesizers are detailed. Loop filter design
is also included. Together with simulations performed in chapter 4,
the derived equations aid the optimum design and implementation of
the two presented fractional-N synthesizer chips described in chapters
5 and 6.
3.2
PHASE-LOCKED LOOP FREQUENCY

SYNTHESIZER
A PLL frequency synthesizer is a circuit that faithfully follows and

reproduces a scaled reference signal over a wide frequency range. A
typical frequency synthesizer block diagram is shown in Figure 3-1.
The phase )samp of a divided-down reference signal, namely
sampling signal, is compared to the phase )feed of the feedback signal
obtained by dividing down the oscillator output signal. The mean
value of the output signal from the PFD/CP combination is equal to
15
16
Chapter 3
the phase error between phases )samp and )feed. When passive loop
filter is employed, a CP is used to convert the voltage to current. The
CP phase error )CP then drives the loop filter. Other high-frequency
components also present at the output of the CP are removed by the
loop filter. The phase error at the output of the filter, )filt controls the
input voltage of the oscillator to obtain the frequency of interest fout
with a phase )out. A brief description of the PLL subblocks is listed
below.
VCXO
fref
)ref
f
Reference samp
PFD
Divider )
samp
Charge
Pump
)feed
ffdbk
Icp
fout
VCO
)CP
Z(s)
)filt
Kvco/s
)out
Divider
N
Figure 3-1. Phase-Locked Loop Frequency Synthesizer
3.2.1
Phase-Locked Loop Main Blocks
The main blocks used in the PLL are briefly described below.
Detailed description of those blocks is included in the appendices.
3.2.1.1
Phase-Frequency Detector
The PFD [2] compares the divided down reference signal with the
divided down feedback signal to generate a signal proportional to the
phase error. Several types of frequency detectors are used in PLLs
[13]; however, the most commonly used is the PFD as it offers both
phase and frequency comparison. A conventional PFD is shown in
Figure 3-2.
The timing diagram for this PFD for the case of a reference signal
lagging the VCO feedback signal is shown in Figure 3-3. The up and
down pulses shown control the source and sink currents that charge or
discharge the loop filter capacitor as described below. A detailed
description of this PFD as well as other types of PFDs is included in
Appendix A.
17
Phase-Locked Loop Frequency Synthesizers
'1'
Ref
D
R
'1'
VCO
D
R
UP
DN
Figure 3-2. Conventional Dual-Type DFF Phase-Frequency Detector
Ref
VCOf
Dn
Up
Reset
Figure 3-3. Phase-Frequency Detector Timing Diagram
3.2.1.2
Charge Pump
The CP is used to convert the PFD output signal voltage to a current

signal to drive the passive loop filter. Optimum CP design yield
matched source and sink currents [10]. The up and down signals
control two switches to source or sink current into the loop filter
18
Chapter 3
capacitive elements. The loop filter is usually of second order.

However, a third-order loop filter could be used if spurii of the PFD
sampling feed-through are to be suppressed [14]. A typical illustration
for the sourcing and sinking of the CP currents is shown in Figure 3-4.
The gain of such a CP is normally given by ICP and its unit is in
amperes.
Vsup
Vsup
Vsup
Iup
Iup
Iup
Up
Up
Up
Icp
Icp
Icp
Dn
Dn
Dn
Zs
Idn
Zs
Zs
Idn
Idn
Figure 3-4. Illustration of Sourcing and Sinking in Charge Pump
3.2.1.3
Voltage-Controlled Oscillator
The VCO converts a continuous input voltage to a high-frequency

signal. Several performance criteria for the VCO design are of
interest. Those are: power consumption, phase noise, jitter, linearity,
tuning range, supply voltage, and substrate noise rejection. The
frequency versus tuning voltage characteristics is usually nonlinear;
however, a linear approximation is often used in the analysis of the
entire PLL. The linear slope approximation for the VCO gain is called
KVCO and its unit is in Hz/V.

3.2.1.4
19
The crystal oscillator is used to generate the reference signal. Crystal

oscillators have high spectral purity and low phase noise performance.
3.2.1.5
Dividers
There are two types of dividers. The ones used as reference dividers;
those are usually low frequency. The others are high- frequency
dividers and those are used as feedback dividers. Detailed circuit
topologies of synchronous and asynchronous, as well as dual-modulus
prescaler dividers are found in the Appendix.
3.3
PHASE-LOCKED LOOP PARAMETERS
PLLs are of nonlinear nature. To simplify their analyses, a linear

approximation is often used. Important parameters that describe the
PLL are the open-loop and closed-loop transfer functions, as well as
the phase noise functions.
The PFD shown in Figure 3-1 is modeled as a subtractor with its
gain modeled as a multiplication factor Kd. The CP gain factor ICP is
the value of the current used. The oscillator transfer function is given
by KVCO/s. The feedback divider transfer function is given by 1/N.
The open-loop transfer function is derived from basic control
theory and is given by:
AOpenloop ( s )
K d I CP Z ( s )
K VCO 1
s N
(3.1)
Kd is equal to 1. The CP current ICP is in amps. The VCO gain KVCO is

given in Hz/V.
The closed-loop transfer function is given by:
AClosedloop ( s )
)out
)samp
AOpenLoop ( s )
1 AOpenLoop ( s )
(3.2)
A typical passive loop filter is a second-order filter that yields a

third-order PLL. Figure 3-5 shows a passive second-order loop filter
with optional third- and fourth- order extra spurious cancellation.
20
Chapter 3
ICP
R3
R2
C1
C2
R4
C3
Vtune
C4
Figure 3-5. A typical Second-Order Loop Filter with Optimal third-and-fourth order Spur
Cancelation Network
The transfer function for the loop filter shown in Figure 3-5 is
given by:
Z (s)
1 sC 2 R2
s C1 C 2 sR2 C1C 2
(3.3)
The loop bandwidth (LBW) frequency fp (radial frequency is Zp) is

defined as the frequency at which the absolute value of the open-loop
gain is equal to 1 (or 0 dB):
AOpenLoop ( s )
fn
(3.4)
The phase margin is defined in the following equation:
I 180 phase( AOpenLoop ( s ))
(3.5)
Equations (3.4) and (3.5) are the main equations used in the design of
the optimum loop filter.
3.3.1
Loop Filter Design
Using equations (3.4) and (3.5), values for the second-order loop filter
components can be easily derived. Those are shown below after some
algebraic manipulation [14]
C1
2 2
K VCO T1 1 Zp T2
I CP K d
N Zp2T2 1 Zp2T12
21
(3.6)
C2
C1 2 1
T1
(3.7)
R2
T2
C2
(3.8)
and
where
T1
sec(I ) tan(I )
(3.9)
Zp
and
T2
(3.10)
T1Zp2
For a stable loop, a good phase margin must be between 45o and
60 . The damping ratio of the loop is also given here as a function of
the phase margin
o
(tan(I )) 4
2
16(1 (tan(I )) )
0.25
(3.11)
For a 56o phase margin the damping ratio is equal to 0.55. The other
values R3, C3, R4, and C4 can be selected to reject the PFD feed-through
frequency signals. Other equations for third- and fourth- order loop filters
could be found in [14].
22
Chapter 3
CASE STUDY
The case presented here is for a possible usage in the WLAN
standard. The specified parameters are shown in Table 3-1.
Table 3-1. Phase-Locked Loop Specified Parameters
Parameter
Synthesized frequency
Sampling frequency
VCO gain
Charge pump gain
Loop bandwidth
Phase margin
Value
1.72 GHz
40/3 MHz
100 MHz/V
2 mA
100 kHz
56o
Using the above-derived equations, the values for the second-order

loop filter components are obtained. Together with other loop parameters, those are shown in Table 3-2.
Table 3-2. Loop Filter Designed Parameters
Parameter
Capacitor C2
Resistor R2
Capacitor C1
Main divider
Time constant T1
Time constant T2
Value
11.6 nF
447 :
1.2 nF
129
0.49 Ps
5.2 Ps
Figure 3-6 shows the open-loop gain and phase transfer functions
for the design of the PLL, whereas Figure 3-7 shows the closed-loop
gain and phase transfer functions. It can be seen from Figure 3-6 that
the gain drops to 1 (0 dB) at the specified LBW frequency (100 kHz)
and the phase is at its peak of 124o which corresponds to a phase
margin of 56o (180o124o).
The loop filter transfer function Z(s) is also plotted in Figure 3-8.
The gain of Z(s) shows the change in the 20 dB/decade slope for fp /10
(10 kHz) and 10fp (1 MHz).
23

Open-Loop Gain Transfer Function
200
100
20log Aol (f)
100
200
100
1 10
1 10
1 10
1 10
1 10
1 10
Opn-Loop Phase Transfer Function
100
120
180
arg (Aol (f))
140
S
160
180
100
1 10
1 10
1 10
1 10
Figure 3-6. Open-Loop Gain and Phase Transfer Functions
24
Chapter 3
Closed-Loop Gain Transfer Function
20 log Acl (f)
5
100
1 10
1 10
1 10
1 10
1 10
Closed-Loop Phase Transfer Function
50
180
arg (Acl (f))
S
100
150
100
1 10
1 10
1 10
1 10
Figure 3-7. Closed-Loop Gain and Phase Transfer Functions
1 10
25
20log(|Z(f)|)
Loop Filter Phase Transfer Function
180
arg(Z(f))
50
100
100
1.103
1.104
1.105
Figure 3-8. Loop Filter Transfer Functions
1.106
1.107
26
Chapter 3
The time-domain function for the closed-loop transfer function can

be obtained by performing an inverse Laplace transform. For the
third-order PLL (second-order loop filter), this is given by [14]:
F (t )
[ R2C2Zn
f 2 ( f1 f 2 )e [Z n t cos Zn 1 [ 2 t
sin Zn 1 [ 2 t
1[ 2
(3.12)
where [ is the damping ratio, Zn is the natural loop radial

frequency, and f1 is the new frequency after a jump from the
frequency f2 at the output. The locking time can be obtained from
equation (3.12) and is often approximated to be:
LockTime
tol
ln
1 [ 2
( f 2 f1 )
[Zn
(3.13)
A classical model for the settling time for the closed-loop PLL
with the second-order loop filter is shown in Figure 3-9.
Figure 3-9. Time-Domain Transfer Function for the PLL
27
3.4
NOISE IN PHASE-LOCKED LOOPS
Each sub-block of the PLL system contributes to the overall noise of

the loop. Those are: PFD/CP combination noise contribution, VCO, and
VCXO phase noise and phase noise of the low- and high- frequency
dividers. Extra noise is contributed by the thermal noise of the loop
filter resistance values.
Phase noise and amplitude noise contributions are not usually
specified separately. A linearized model for the noise contributions of
the subblocks in the PLL is shown in Figure 3-10. Each subblock is
assumed to contribute a small-signal noise source that can be referred
to the input or output of the subblock. In this monograph, the noise
source is placed after the functional transfer function of the subblock.
Vf
Ipd
1/R
)r
ICP
_
F(s)
)vco
Kv
1/s
)out
6
1/N
)n
Figure 3-10. Noise Contributions in the Phase-Locked Loop System
Table 3-3. Gain and Noise Terms and their Units
Gain terms
Reference Divider
R
Charge pump
Gain ICP
Loop filter Z(s)
VCO tuning gain
KVCO
PLL feedback
Divider N
Gain units
No units
Amps/rad
:
rad/V
Noise terms
Reference oscillator
Phase noise )r
Charge pump
Current noise Ipd
Loop filter Voltage
noise Vf
VCO phase Noise
)VCO
No units
Feedback Divider
phase Noise )n
Output phase Noise
)out
Noise units
rad-rms or radrms/Hz
Amps or Amps/Hz
Volt or Volt/Hz
The notations used in Figure 3-10 are listed below. Gain terms and
their units, as well as phase noise and their units are included (Table
3-3). From basic control theory, it is easy to determine the transfer
28
Chapter 3
function of the individual noise contributors. Those are given in the

following equations.
The output to reference transfer function is given by:
) out
)r
I CP K VCO Z ( s )
s
I CP K VCO Z ( s )
1
sN
(3.14)
The output to PFD/CP transfer function is given by:

) out
I pd
K VCO Z ( s )
s
I CP K VCO Z ( s )
1
sN
(3.15)
The output to filter transfer function is given by:

) out
Vf
K VCO
s
I CP K VCO Z ( s )
1
sN
(3.16)
The output to VCO transfer function is given by:

) out
) vco
1
I K Z (s)
1 CP VCO
sN
(3.17)
The output to feedback divider transfer function is given by:

) out
)n
I CP K VCO Z ( s )
s
I CP K VCO Z ( s )
1
sN

(3.18)
The output noise power is the product of the input noise power and
the magnitude squared of the transfer function. The total output noise
power is calculated by summing the output noise power contributed
from each noise source (assuming the noise sources are uncorrelated).
29
3.4.1
Component Noise Models
The component noise models must generally account for three

different types of noise power spectral density (Figure 3-11). These
types are primarily distinguished, for modeling purposes, by the slope
of the noise spectrum [15]:
x White noise is characterized by a flat, or uniform, noise power
density in the band of interest. Thermal and shot noise sources

have white noise spectra. Examples include resistors (including
MOSFET channel resistance) [16] (this is called white noise 1/f 0
noise, for consistency with the remaining spectra).
x 1/f noise is characterized by a noise power spectrum that decreases
at a rate of 3 dB per octave, or 10 dB per decade. Flicker noise
sources have 1/f noise spectra. Examples include MOSFET channel
(drain) current and polysilicon resistors [17].
x 1/f 2 noise is characterized by a noise power spectrum that decreases
at a rate of 6 dB per octave, or 20 dB per decade. Oscillator phase
noise in the thermal noise region has a 1/f 2 noise spectrum.
x 1/f 3 noise is characterized by a noise power spectrum that decreases
at a rate of 9 dB per octave, or 30 dB per decade. Oscillator phase
noise in the (upconverted) flicker noise region has a 1/f 3 noise
spectrum.
L(f)
(dB)
1/f3
1/f2
1/f1
fc32
fc21
1/f0
fc10
log(f)
Figure 3-11. Phase Noise slopes for White Noise (1/f 0 ) , Flicker Noise (1/f 1 ) , Oscillator Noise
in the Thermal Region (1/f 2), and Oscillator Noise in the Upconverted Flicker Noise Region
(1/f 3 ) .
30
Chapter 3
Noise power spectra for some components (such as the loop filter
resistors) can be directly calculated with good accuracy. More complex
noise sources, such as oscillator phase noise, must often be measured
in order to provide accurate results. Measured noise spectra can be
characterized by noting the actual noise power at a certain frequency,
the 1/f n region in which that frequency lies, and the corner
frequencies for the different 1/f n regions.
3.4.1.1
Reference Oscillator and VCO Phase Noise
Oscillators generally have 1/f 3, 1/f 2, and white noise (1/f 0) regions.
Phase noise models and simulations (e.g. Leesons equation [15],
impulse sensitivity functions [18], and periodic noise analysis [19])
can be used to estimate the phase noise spectra, but direct
measurements are preferred. Degradations to the VCO and reference
noise from the buffering and divider circuits should be included, as
well. For example, it is difficult to obtain noise floors below 145
dBc/Hz without significant effort at reference frequencies around
2030MHz.
3.4.1.2
Charge Pump Current Noise
The CP current sources have 1/f and white noise (1/f 0 ) regions, which
can be estimated with reasonable accuracy from simulations (e.g.
SPICE). A complication that arises in the CP PLL is the aliasing effect
caused by the periodic switching of the CP current. In lock, the CP has
a duty cycle determined by delays in the phase detector, leakage in the
loop filter, and other systematic design choices. While periodic noise
simulations should be used to accurately estimate the net noise power
spectrum coupled into the loop filter, in some cases a good
approximation is obtained by attenuating the CP current noise by the
(average) duty cycle of the CP pulses. The noise power is attenuated
by multiplying it by the average duty cycle.
3.4.1.3
Loop Filter Resistor Noise
For the loop filter of Figure 3-5 we calculate the voltage noise present
at the output from resistors R2 and R3 (a third-order loop filter). In
general, a noisy resistor is modeled as an ideal resistor of the same
value in series with a noise voltage generator [20]. The noise voltage
density is given by:
v2
31
(3.19)
4kTR
where k is Boltzmanns constant, T is the device temperature, and

R is the resistance value. At room temperature, 4kT = 1.66 1020 VC.
Using circuit analysis, the transfer function can be calculated from
each noise voltage generator to the filter output voltage. (These
equations are not simplified, but are reduced enough for computer
implementation. Note the low-pass characteristic on R2 and R3. R3
needs to be placed at much higher frequency to prevent oscillation.)
Vo
VR2
(4kTR2 )
Vo
VR3
3.4.1.4
C1
(3.20)
C1 ( sR3C3 1) ( sR2C1 1)( sR3C2C3 C2 C3 )
(4kTR3 )
sR2C1C2 C1 C2
(3.21)
C3 ( sR2C1 1) ( sR3C3 1)( sR2C1C2 C1 C2 )
Main Divider Noise
The divider is a periodically time-varying circuit. The fixed-ratio

frequency divider gives an ideal noise figure F = 20log(N). An internal noise contribution is also given by the divider and the output noise
spectral density in the case of fixed division ratio is given by [1, 14]:
S) ,n ( f )
3.4.1.5
S) ,in_divider ( f ) 1014.7

1016.5
2
N
f
(3.22)
Phase-Frequency Detector Phase Noise
Measurements made on frequency synthesizers with a decreasing

division ratio showed that there is a lowering in the phase noise
plateau [3]. However, this 20log(N) improvement of phase noise is
somewhat offset by the increase of sampling frequency at the PFD.
This has been proven in [4] and illustrated in the single-sided power
spectral density at the output of the PLL as given by:
+( f )
4S 2 't 2 f 02
1
SIout ( f ) 10 log10
[dBc/Hz]
2
fs
(3.23)
32
Chapter 3
Rewriting equation (3.23) in a more convenient dB format yield:

2
+ ( f ) FOM{dBc / Hz } 20 log10 f 0 10 log10 fs [dBc/Hz] (3.24)
Substituting the divider contribution in equation (3.24) gives [4]:

2
+ ( f ) FOM{dBc / Hz } 20 log10 N 10 log10 f s [dBc/Hz] (3. 25)
where FOM is a noise figure of merit of the PFD. FOM is a constant

at a specific frequency.
3.4.1.6
Overall Phase Noise Contribution
The contribution of the phase noise of individual subblocks to the

PLL is illustrated in Figure 3-12. As can be seen in this figure, the
logic noise (including divider noise) and the reference oscillator
phase noise are dominant within the PLL LBW. The VCO phase noise
is dominant outside the LBW.
Table 3-4. Phase Noise Parameters
Parameter
Reference
Oscillator Plateau
Reference Divider
plateau
PFD Normalized
Plateau
VCO noise Plateau
Main Divider
plateau
Symbol
Lref
Value
143
Units
dBc/Hz
Lrefdiv
173
dBc/Hz
Lpd
216
dBc/Hz
Lvco
Ldiv
159
173
dBc/Hz
dBc/Hz
Using equations 3.143.18, a Mathcad program (see Appendix F)

was written to predict the closed-loop phase noise contributions of the
individual subblocks and the entire PLL. The same loop parameters
used in the case study discussed in this chapter are used in the phase
noise calculations. Example phase noise plateaus used in this program
are shown in Table 3-4.
33
phase noise dBc/Hz
VCO phase noise
loop
bandwidth
logic plateau
noise
Filter roll
off
VCO Phase noise skirts
20log(fout/fref)
20log(fout/fsamp)
logic noise
VCXO phase
noise
1/f3 LBW
1/f2 frequency
offset
Figure 3-12. Phase Noise Contributions in PLL
The MathcadTM simulation results obtained using the data from the
case study and data from Table 3-4 are shown in Figure 3-13. They
correlate well with the conceptual phase noise contributions of Figure
3-l2.
34
Chapter 3
Figure 3-13. Phase Noise Contributions for the Case Study
3.5
FRACTIONAL-N SYNTHESIZERS
From the study of noise in the previous section, it was shown that the
noise improves if a higher sampling frequency is used [8, 9]. That
results in the usage of fractional division ratio to satisfy the output
VCO frequency and frequency step of interest. Frequency synthesizers
employing such fractional dividers are called fractional-N frequency
synthesizers. Figure 3-14 shows a conventional fractional-N frequency
synthesizer. Early Implementation of the fractional dividers employs a
digital accumulator [12] that controls a dual-modulus divider.
The synthesizer shown in Figure 3-14 is termed first-order
fractional-N frequency synthesizer. The fractional divider is composed
of two parts: the integral part N and the fractional part F and is often
35

VCXO
fref
1/R
fsamp
PFD
VCO
f out
DMD
N/N+1
overflow
Frac
latch
Figure 3-14. Conventional Fractional-N Synthesizer
represented by N.Frac (e.g. 10.5 where N is 10 and 0.Frac is 0.5). The

fractional part 0.Frac controls a digital accumulator whose overflow
controls a dual-modulus prescaler N/N + 1. The size of the accumulator used depends on the frequency error as well as the sampling
frequency. The output frequency is given by:
f out
fsamp u N .Frac
fsamp u N
F
(3.26)
The fractional part 0.Frac is usually represented by a fraction

whose integer numerator is called K and whose integer denominator is
called F.
Since the overflow controlling the DMD changes the value of the
divider from N + 1 to N within the cycle, this resets the phase error at
the output of the PFD, generating signals that modulate the VCO and
appear at the output of the VCO. These signals are deterministic in
nature and can be predicted, they are often termed fractional spurious
signals [13]. These spurious signals appear at fractional multiples of
the reference and are difficult to remove and hence are not used in
commercially viable solutions. However, fractional-N frequency
synthesizers that employ '6 modulators in place of the first-order
36
Chapter 3
digital accumulator have recently gained popularity as they provide

excellent phase noise suppression within the LBW of the PLL used
[5].
A typical frequency synthesizer employing a '6 modulator is
VCXO
fref
Reference
Divider
fsamp
Charge
Pump
PFD
ffdbk
VCO
fout
Divider
'6
Modulator
N.Frac
Figure 3-15. Typical DeltaSigma ('6-Based Fractional-N Frequency Synthesizer
3.5.1
'6 Modulators in Frequency Synthesizers
In this section, '6 modulators of third order are described as they are
unconditionally stable [57, 11]. This type of modulators is often
termed MASH-1-1-1 modulators as they incorporate three first-order
modulators in parallel. Figure 3-16 shows a basic block diagram of
this type of modulator.
Typical time-domain output of this modulator is obtained in
Matlab Simulation for the case of a fractional divisor of 0.835 and is
As can be seen from Figure 3-17, the '6 modulator emulates the
average fractional part of the divider into instantaneous several
integral levels. Those vary in a random manner between 7 and 8 for
this order of modulator. In general, for Norder MASH modulator, the
output would vary between ( 2 Norder 1 ) and 2 Norder [21]. The fractional
divider N.Frac would then be emulated by instantaneous dividers that
vary in a random manner between (N( 2 Norder 1 )) and ( N 2 Norder )
37
such that the average value of the sequence of those divisors is equal
to the desired fractional-N divider value.
X(n)
E 1(n)
Z -1
Y(n)
-E 1(n)
Z -1
E 2 (n)
Z -1
-E 2 (n)
Z -1
E 3 (n)
Z -1
Figure 3-16. A Third- Order MASH1-1-1 '6 Modulator Block Diagram
A linearized noise equation has been derived that accurately

predicts the divider output phase noise spectrum [3]:
L( f )
(2S ) 2
12 f samp N .Frac
[2sin(
Sf
fsamp
)]2( Norder 1)
[rad 2 /Hz] (3.27)
38
Chapter 3
MASH-1-1-1 Output
-2
-4
5200
5205
5210
5215
5220
5225
5230
5235
Figure 3-17. Time-Domain Output of MASH1-1-1 '6 Modulator
However, a fast Fourier transform and some algebraic manipulation

are usually performed on the sequence of instantaneous dividers to
yield the single-sidedband (SSB) power spectral density of the '6
modulators.
Typical SSB of this modulator is shown in Figure 3-18. As can be
seen from this figure, the phase noise of this modulator is very low,
close to base band (below 130 dB, below 500 kHz). This will help
suppress the in-band phase noise of the '6 frequency synthesizer.
Above 500 kHz, the PLL loop filter should filter out the phase
noise of the MASH modulator. Therefore, the usage of the MASH
modulator is a key factor in reducing the phase noise plateau in
fractional-N frequency synthesizer.
39

Baseband output spectrum of MASH
0
P OW E R S P E CTRUM (dB )
-50
-100
-150
-200
-250
100
200
300
400
500
600
FREQUENCY (KHz)
700
800
900
Figure 3-18. Typical SSB Power Spectral Density of third- Order MASH1-1-1
'6Modulator
3.5.1.1
Fractional-N Case Study
In this section, a case study is presented for a '6-based frequency

synthesizer used in the WLAN standard. The selected output frequency
was chosen to yield a fractional division ratio. The specified parameters are similar to those presented in the case of the integer PLL but
with a higher sampling frequency of 40 MHz as shown in the shaded
cell of Table 3-5. Similar analyses to those presented for the integer
PLL case will be repeated here.
40
Chapter 3
Table 3-5. '6 PLL Parameters Used

Parameter
Frequency
Sampling frequency
VCO gain
Charge pump gain
Loop bandwidth
Phase margin
Value
1.725 GHz
40 MHz
100 MHz/V
2 mA
100 kHz
56o
Using [14], the values for the third-order loop filter components
are obtained. Those are shown in Table 3-6.
Table 3-6. Loop Filter-Designed Parameters
Parameter
Capacitor C2
Resistor R2
Capacitor C1
Main divider
Capacitor C3
Resistor R2
Value
34.8 nF
150 :
3.6 nF
43.125
366 pF
25 :
The phase noise for this fractional-N frequency synthesizer was

analyzed using a MatlabTM program. The results obtained are shown
in Figure 3-19. They include the phase noise contributions of all the
subblocks of the PLL including the '6 modulator/divider combination
(top curve). Due to the suppressed phase noise of the '6 modulator,
the improvement in the overall phase noise is apparent in Figure 3-19
when compared to Figure 3-13. The '6 noise contribution is however
apparent outside the loop filter BW.
Detailed simulation for the '6 fractional-N frequency synthesizer
using a commercial circuit/system simulator package (CadenceTM) is
presented in chapter 4. The simulation in chapter 4 will help the
designer make the right implementation optimizations for such a
synthesizer.
41

Fractional-N PLL Phase Noise
-60
VCO Noise
Reference Noise
R2 LF noise
R3 LF noise
PFD/CP Sampling Noise
Delta-Sigma Noise
Total Synth. Noise
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
-170
2
10
10
10
10
Offset Frequency (Hz)
10
10
10
Figure 3-19. Phase Noise Contributions of SubBlocks in '6-Based Fractional-N Synthesizer
RMS PHASE ERROR ( Irms ) AND ERROR

VECTOR MAGNITUDE
3.6
Most wireless standards specify the noise in terms of rms phase

error unit rather than phase noise at spot frequencies [14]. The phase
error is the area under the phase noise mask between two spot
frequencies. It usually is obtained by integrating the normalized phase
noise plot between the mentioned spot frequencies. The rms phase
error in degrees is shown in Figure 3-20 and is given by:
Irms
f2
+( f )
10
f1
10
df
(3.28)
42
Chapter 3
(-1,1)
(1,1)
EVM
Irms
I
(-1-1)
(1,-1)
Figure 3-20. RMS Phase Error and Error Vector Magnitude in a QPSK System
The constellation diagram of a quadrature phase-shift key (QPSK)

system is shown in Figure 3-20, displaying the four possible
constellation points. At the receiver, the constellation point for the
symbol 11 due to anomalies in the transmission, is received with a
phase and amplitude error as shown in Figure 3-20 and is located at
the red point. The vector connecting the original constellation point to
the new location (outside the circle) is called error vector magnitude
and is usually referred to as EVM.
3.7
CONCLUSION
In this chapter, detailed analyses of PLL frequency synthesizers were

presented. Both integer and '6-based fractional-N were considered.
Open-loop and closed-loop gain and phase equations were derived.
Phase noise of individual PLL subblocks was introduced. White noise
(1/f 0), flicker noise (1/f 1), Oscillator noise in the thermal region (1/f 2),
and oscillator noise in the upconverted flicker noise region (1/f 3) were
also described. Loop filter design equations were shown and used in
the case study of a frequency synthesizer potentially used in the
WLAN standard.
43
The theory presented in this chapter as well as the detailed system

level simulation presented in the chapter 4 aid the design and
implementation of the two fractional-N synthesizer chips described in
chapters 5 and 6.
REFERENCES
[1] W.F. Egan, Modeling Phase Noise in Frequency Dividers, IEEE
Transactions on Ultrasonics, Ferroelectrics and Frequency Control, 37
(4), pp. 307315, July 1990.
[2] J.A. Crawford, The Phase Frequency Detector, R.F. Design, Feb.
1985, pp. 4657.
[3] I. Thompson and P.V. Brennan, Phase/Frequency Detector Phase
Noise Contribution in PLL Frequency Synthesizer, IEEE Electronics
Letters, July 2001, 37 (15), pp. 939940.
[4] I. Thompson and P.V. Brennan, Phase Noise Contribution of the
Phase/Frequency Detector in a Digital PLL Frequency Synthesizer,
IEE Proceedings on Circuits, Devices and Systems, Feb. 2003, 150 (1),
pp. 15.
[5] T.A.D. Riley, M.A. Copeland, and T.A. Kwasniewski, DeltaSigma
Modulation in Fractional-N Frequency Synthesis, IEEE Journal SolidState Circuits, 28, pp. 553559, May 1993.
[6] B. Miller and B. Conley, A Multiple Modulator Fractional Divider,
Proceedings of IEEE 44th Annual Symposium Frequency Control,
1990, pp. 559567.
IEEE Transactions of Instrumentation Measurement, 40, pp. 578583,
June 1991.
[8] V. Manassewitsch, Frequency Synthesizers, Theory and Design, 3rd
edn., Wiley: New York, 1987.
[9] R.E. Best, Phase Locked-Loop Design Simulation and Applications, 3rd
edn. MacGraw-Hill, New Jersey, 1997.
[10] F.M. Gardner, Charge-Pump Phase Lock Loops. IEEE Transactions
on Communication, COM-28:18491858, Nov. 1980. Description of
the charge pump mechanism in a PLL.
[11] B.-G. Goldberg. Digital Techniques in Frequency Synthesis, MacGrawHill, New Jersey, 1996.
[12] B.-G. Goldberg, Analog and Digital Fractional-n PLL Frequency
Synthesis: A Survey and Update, Applied microwave and wireless,
June 1999. Tutorial presenting fractional-N frequency synthesis.
[13] P.V. Brennan, Phase-Locked Loops, Principles and Practice, McGrawHill, New Jersey, 1996.
[14] D. Banerjee, PLL Performance, Simulation and Design, 3rd edn.,
2003, National Semiconductor, (http://www.national.com/appinfo/wireless/
files/Deansbook3.pdf)
[15] D.B. Leeson, A Simple Model of Feedback Oscillator Noise Spectrum,
Proceedings of the IEEE, MI, 54 (2), pp. 329330, 1966.
44
Chapter 3
[16] C.-H. Chen, et al., Direct Calculation of the MOSFET High Frequency
Noise Parameters, Proceedings of the 14th International Conference
on Noise and Physical Systems and 1/f Fluctuations, pp. 488491, July
1997.
[17] W. Liu, et al., RF MOSFET Modeling Accounting for Distributed
Substrate and Channel Resistance with Emphasis on the BSIM3v3
SPICE Model, IEDM Technical Digest, pp. 309312, Dec. 1997.
[18] A. Hajimiri and T.H. Lee, A General Theory of Phase Noise in
Electrical Oscillators. IEEE Journal of Solid-State Circuits, 33 (2), pp.
179194, Feb. 1998.
[19] Cadence Design Systems, Periodic S-Parameter and Noise Analysis
using SpectreRF PSP/PNOISE Analyses, Application Notes and White
Papers, http://www.cadence.com/whitepapers/pspapn1.pdf
[20] A. Mehrotra, Noise in Radio Frequency Circuits: Analysis and Design
Implications, International Symposium on Quality Electronic Design,
ISQED San Jose, Mar. 2001.
[21] M. Kozak, I. Kale, A. Borjak, and T. Bourdi, A pipelined All-Digital
DeltaSigma Modulator for Fractional-N Frequency Synthesis, IEEE
Instrumentation and Measurement Technology Conference (IMTC
2000), Vol. 2, pp. 11531157, Baltimore, MD, May 2000.
Chapter 4
SYSTEM SIMULATION OF '6-BASED
FRACTIONAL-N SYNTHESIZERS
Efficient Modeling and Characterization
4.1
INTRODUCTION
The aim of the work presented in this monograph is the research,

study, design, and implementation of high-speed '6-based fractional
synthesizers for WLAN standards (802.11a, b, and g). In chapter 3,
detailed analyses of integer-N and '6-based fractional-N phaselocked loops have been presented. Open-loop, closed loop, and phase
noise equations have been derived. In this chapter, behavioral modeling
for a proposed fractional-N '6-based PLL is carried out to evaluate
architectural limitations, identify dominant noise sources, automate
loop filter optimization, and generate PFD/CP linearity specifications.
Also, a phase-domain model of the proposed architecture is constructed
using The CadenceTM Verilog-A Language. The model combines the
VCO, reference, and divider integrators into one resettable integrator
within the PFD. The '6 modulator model is also included. The
divider adds '6 noise to the frequency variable then divides the sum
by the average divide ratio. The simulation results obtained in this
chapter and measured results of subblocks of the chip designed in
chapter 5 contribute to the optimum design and implementation of
fractional-N synthesizers presented in chapters 5 and 6.
45
46
Chapter 4
4.2
PHASE-DOMAIN MODEL
Figure 4-1 shows a block diagram of a '6-based fractional-N

synthesizer. This synthesizer employs voltage-controlled oscillators
synthesizing 802.11a frequencies that will be described in chapter 5.
However, for simplicity, Figure 4-1 shows the synthesized frequency
to be two-thirds of the desired frequency. This is mixed with a
divided-by-2 version of it to generate the LO for the 802.11a bands.
The CadenceTM model of this synthesizer is shown in Figure 4-2. The
PLL model is a phase-domain model; in steady state, the VCO model
generates a ramp instead of an oscillatory voltage (voltage-domain
model).
Figure 4-1. A Conventional '6-Based Fractional-N Frequency Synthesizer
Tuning
Curve
PFD/CP
LUT
)
40 MHz
= 40V
Integrator
CP
Divider
'6 MMD
Frequency
VCO
Frequency
Figure 4-2. Phase-Domain Model of the Synthesizer
VCO
phase
System Simulation of '6 -Based Fractional-N Synthesizers
47
The purpose of behavioral modeling of the fractional-N '6-based

PLL is to check for performance limitations, identify dominant noise
sources, automate loop filter optimization, and generate PFD/CP
linearity specifications. Phase-domain models have several advantages
over voltage-domain models:
1. A phase-domain model is time-invariant. Consequently, the DC
operating point analysis quickly brings the model to steady state
conditions, eliminating the need to simulate long startup transients.
A legitimate DC operating point also makes the AC and noise
analysis available. The AC and noise analyses are very fast
because they run in the frequency domain with linearized models.
Small signal frequency- domain analyses are used to minimize the
rms. phase noise with respect to the loop filter, subject to
bandwidth and phase margin constraints.
2. PFD/CP nonlinearities are easily modeled and specified by a
simple transfer curve.
3. Phase-domain models are compatible with the CadenceTM
environment, which means that the architecture can be changed
without having to rewrite any code, top-down design flow.
4. A phase-domain model suppresses the carrier, making time domain
faster than voltage-domain models in the CadenceTM environment.
Rather than simulating transient voltage, the model simulates
phases/frequency of the individual blocks. The voltage at the output of
the reference signal represents the frequency used in the design (in
this case a 40 MHz, hence the reference is 40 V).
The PFD model simulates cycle slips by combining the reference
and VCO integrators into one resettable integrator within the PFD
model. The PFD integrates frequency error to generate a duty cycle
that in turn drives the CP model.
The PFD model gives a duty cycle output that can take values in
the range of 1 to +1. When the duty cycle is negative there is discharge
to the loop filter and when the duty cycle is positive there is a charge to
the loop filter.
48
Chapter 4
Figure 4-3. PFD/CP Characteristics Showing the Dead-Zone Region
49
The PFD/CP linearity curve, whether taking into account the deadzone or not, is provided by a lookup table immediately after the PFD.
One case where the PFD suffers from the dead-zone [4, 5] is presented
in Figure 4-3. The non-linear PFD data could be easily stored in a file
and loaded within the used block. The output of this lookup table is a
voltage driving the subsequent CP that has normalized up and down
currents yielding the desired CP values.
The output of the CP current creates a voltage at the output of the
loop filter that in turn drives the VCO.
The VCO gain characteristic can either be a lookup table obtained
by either simulating or measuring the gain of the VCO or a
polynomial generated by curve fitting the characteristic gain curve [8].
The gain curves of this multiband VCO are shown in Figure 4-4. The
output of the VCO is a frequency which is represented by a voltage
value in this proposed model. To obtain a phase value at the output of
the VCO, it is mandatory to use an integrator as shown in Figure 4-2.
What follows is a brief description of the behavioral models of each
constituent blocks in the synthesizer.
Figure 4-4. Multiband VCO Tuning Characteristics Showing the Frequency (a Voltage in the
Phase-Domain Model) Versus the Tuning Voltage
50
Chapter 4
4.2.1
A Constituent Blocks Behavioral Models
4.2.1.1
The Reference Oscillator
For the reference oscillator phase-domain model, the reference is

represented by a fixed DC voltage representing reference frequency
instead of phase. This is possible and beneficial as the reference
integration has been moved to the PFD and hence DC analysis can
now be used to skip long startup transients. In this work, the selected
reference signal frequency Fref which is equal to 40 MHz is represented
by a fixed 40 V DC source. At the oscillator sampling time Tref Fref1 ,
the oscillator phase noise data could easily be superimposed on the
reference signal. The measured open-loop single-sided power spectral
density (PSD) for the employed reference oscillator Lref ( f ) is 145
dBc/Hz. The noise updated reference frequency signal is given by:
Fref
Fref 10Lref ( fO ) / 20 u f O u Tref u normal _ dist ( rand ,0,1)

1
(4.1)
u
white _ noise(10Lref ( fO ) /10 u fO2 )
Tref
The noise term has two parts as shown in the equation above. The
first term is taken at each reference sample time. It should be noted
that the noise here is frequency noise. f O is the offset frequency
where the measured PSD Lref ( f O ) is read. The normal distribution
and the white noise functions are Verilog-A built-in proprietary
functions.
4.2.1.2
The '6 Modulator/ Feedback Integer Divider
The '6 modulator and the feedback divider are treated jointly. The
combined model represents the model of the desired fractional
divider. The third-order '6 MASH modulator model is derived by
employing the sampled difference equations of each node. The
modeled '6noise; mainly quantization noise; enters the loop linearly
after passing thorough a digital integrator [6]. Since integration is a
linear operation and since operation is at frequencies where the digital
integrator could be replaced with an analog integrator, both integrators
51
(divider and VCO) could be pulled into the PFD model, and hence the
'6 divider as well as the VCO operate on frequency rather than
phase.
'6quantization noise is straightforward to model in the time
domain; it just implements the difference equations. An equivalent
frequency-domain noise source for the third-order '6 MASH
modulator can be found from the z-domain expression for the output
noise. Consider the linearized noise transfer function and PSD of the
input quantization [2]:
H n ( z)
1 z
1 3
(4.2)
And the PSD = T / 12, where T is the clock period. The output
PSD is:
PSD. H n ( z )
(4.3)
Note that differentiation as first order with respect to time can be

approximated as 1 z 1 / T , where T is the sampling period. The
continuous time equivalent of the discrete time output PSD is found
by replacing 1 z 1 / T with s. Thus, the equivalent continuous time
3 2
noise PSD is sT T /12 , which is a white noise source with PSD
7
equal to T / 12 , differentiated three times.
4.2.1.3
The VCO
The noisy signal generated by the VCO is generated in a similar

manner to the one described for the reference signal. However, here
tuning curves of the VCO are first generated with the aid of
polynomial fitting performed on the measured gain characteristics [8].
K VCO
F1 2 F2 u x 3F3 u x 2 4 F4 u x 3
(4.4)
Where x is the tuning voltage. The noise modeled here is frequency

noise and hence to get phase noise, integration of this frequency noise
is required at the VCO output.
52
4.2.1.4
Chapter 4
The PFD/CP
The noise sources of the PFD and CP are added as random noise
similar to the reference oscillator case [1]. The PFD/CP linearity curve
could also be included as a data file, showing the duty cycle versus
CP, to gauge the effect of the dead zone as shown in Figure 4-3.
4.2.1.5
The Loop Filter
The loop filter uses real components rather than a transfer function
and therefore the noise due to the resistors although negligible adds up
to the overall noise of the loop; thus their noise should be taken into
account when phase noise frequency-domain analysis is performed.
4.2.2
Noise Modeling Summary
Placing all non-loop-filter integrations inside the PFD reduces the

VCO model to a tuning curve (Figure 4-4). The VCO block generates
a voltage representing the VCO frequency, not the VCO phase. To get
phase noise, we must integrate the VCO frequency noise. That is why
the synthesizer model has an ideal extra integration at the VCO
output.
Placing the VCO integration in the PFD means the reference and
VCO noise sources are now white noise sources. The reference and
VCO are both oscillators and their noise sources are assumed to result
from Wiener processes [3]. A Wiener process integrates white noise.
The PSD of an oscillators white noise process is chosen to align the
integrated noise and measured VCO noise at one frequency. The
reference and VCO models have noise sources for frequency-domain
and time-domain analysis. For time-domain analysis, the VCO and
reference models add a Gaussian random variable to their outputs. The
random variable is updated at a user-defined rate. 40 MHz was chosen
for the update rate because that was the '6 clock frequency. The
standard deviation of the random variable depends on the sample rate
and is automatically scaled to produce the correct PSD.
The open-loop single-sided power spectral densities of all the
aforementioned blocks are shown in Figure 4-5. Those results are
obtained by direct Cadence PSD transform on the phase-domain
time-domain signals. The produced phase noise plots are as expected.
53
Figure 4-5. Open Loop of Synthesizer Constituent Blocks Obtained by Direct PSD Transform
4.3
SYNTHESIZER PLATFORM EVALUATION
The simulation in the proposed platform can be carried out in both

time domain and frequency domain. The time-domain simulation aids
the monitoring of the settling in the phase-locked loop. Figure 4-6
shows the phase-domain model time-domain simulation illustrating
the voltages at each individual node in the loop. The reference
frequency of 40 MHz (represented here by 40 V) is shown along with
the feedback frequency (divider output) illustrating its average to 40
MHz (i.e. 40 V) after 7 Ps. The PFD output is showing its convergence
to 0 in 7 Ps (i.e. locking condition). The settling of the loop is best
viewed by monitoring the tuning voltage that reaches its desired value
as illustrated in the figure. The synthesized VCO frequency and its
correspondent local oscillator frequency are both shown to reach their
respective values within 7 Ps. It can be easily seen that after 10.5 Ps
the '6 fully settles and the effect of the initial seed disappears
completely, hence increasing the modulator activity. It should be
54
Chapter 4
mentioned here that this simulation takes a couple of seconds compared

to a few days if transistor-level transient simulations were run.
In frequency-domain, open- and closed-loop phase noise can be
characterized. At this level, open-loop phase noise data must be
included in the phase domain model mentioned above. Each of the
individual blocks except the loop filter employs noise data derived
from a phase noise mask that has been simulated and measured. The
phase noise masks data obtained from Figure 4-6 are incorporated in
the phase model. Those can be enabled when loop phase noise is
needed.
Figure 4-6. Time-Domain Simulation of the Phase-Domain Model of the Platform Showing
the Voltages at each Node in the Synthesizer
55
Closed-loop phase noise of the synthesizer is then obtained by

performing a PSD transform on the integrated signal shown in Figure
4-2. The divider and the '6 modulator are combined into one unique
block. The block simply divides the voltage in fractional mode and
contains the phase noise mask of the '6 modulator.
All the results of individual blocks have been discussed separately
above and it is time now to close the synthesizer loop by implementing
initial off-chip loop filter components. With the aid of this platform
with fast simulation time, it is possible to optimize those filter
components to yield optimum phase noise performance. Initial loop
filter values were calculated using [8] and are shown in Table 4-1.
Table 4-1. Frequency Synthesizer Loop filter Parameters
Parameter
C1
R2
C2
R3
C3
R4
C4
Charge pump, Max current
Average divider ratio
Value
270p
1000
2.5n
91
120p
91
120p
1 mA
91.65
The performance in the frequency domain (i.e. phase noise) can be

easily obtained by performing power-spectral density transform on the
time-domain phase-domain model results of the synthesizer in locked
condition. A snapshot of the time-domain phase model of this synthesizer in lock is shown in Figure 4-7a and b, unzoomed and zoomed,
respectively.
To show the efficacy of the developed model, the synthesizer is
simulated with two different loop filter bandwidths, namely 300 kHz
and 1 MHz. Figure 4-8 overlays the phase noise mask for both cases.
It could be easily demonstrated that this model correlates well with the
phase noise mask for the synthesizer if linear-model control loop
equations were used outside this platform. Clear observations can be
summarized as follows: As the loop bandwidth is increased, the closein phase noise plateau is suppressed. However, the deterministic
spurious noise as well as the quantization noise due to the '6
modulator is exacerbated.
56
Chapter 4
(a)
(b)
Figure 4-7. Voltages at Each Node in the Synthesizer during Lock (a) Unzoomed,
(b) Zoomed
57
Figure 4-8 also shows the presence of several spurious signals that
can be suppressed if further dithering is applied to the '6 modulator
as will be discussed in the ensuing section. These spurious signals are
due to close-to-integer operation.
Figure 4-8. Phase Noise Waveforms for the LO Synthesizer Obtained by PSD Transform for
Two Loop Bandwidth Cases (a) 300 kHz and (b) 1 MHz
4.3.1
Dithering Effect
It is useful to describe the dithering applied to the '6 modulator

before discussing the performance of the synthesizer with dithering.
One of the consequences of using '6 modulators with DC inputs
is the presence of limit cycles or spurs [2] that are strongly visible for
inputs that are inverses of power of 2 such as 0.75, 0.5, and 0.25. This
is due to the fact that the binary representation of such DC values has
much less randomness. Figures 4-9 and 4-10 show the noise spectrum
for 0.5 dc input with and without spurious limit cycles in linear and
log scales, respectively.
58
Chapter 4
Figure 4-9. Power Spectral Density of DeltaSigma Noise Shaper with and without
Dithering
Dithering, Log Scale
59
The effect of these limit cycles are reduced greatly as we introduce

dithering or randomness. Here, the spurs have been eliminated by
introducing an error (nonzero initial condition) in the least significant
bit (LSB) of the input word [7]. The error is too small to affect the
synthesized frequency within the permissible frequency error but is
good enough to eliminate the spurs to some extent.
As can be seen from Figure 4-11, there are two remnant fractional
spurs seen in the region of 1 MHz. Those spurs exist despite the LSB
dithering applied to the '6 modulator. Those can be further removed by
increasing the efficiency of the dithering employed. The low-frequency
effect below 25 kHz is a deficiency in the power-spectral density
transform function built in CadenceTM. If low-frequency phase noise
is of interest, it is advisable to export the data to a mathematical
package for further accurate processing [3].
Figure 4-11. Phase Noise Mask for the LO Synthesizer with 300 kHz Loop Bandwidth with
and without Dithering
Figure 4-11 shows the phase noise profile for the frequency
synthesizer local oscillator at 5.5 GHz with a loop bandwidth of 300
60
Chapter 4
kHz. Two cases are superimposed. The first case (bottom trace) is when
no dithering is employed which shows the presence of spurious
fractional content whereas the top trace is the case where dithering is
applied. In this case, the spurious energy is spread across the spectrum
and hence the lifting of the phase noise as illustrated in the figure. This
effect must be taken into account when designing synthesizers to strike
a compromise between deterministic spurious noise and random phase
noise.
4.3.2
Close-to-Integer Operation
One of the practical issues that are often overlooked in fractional-N

PLL designs is the problem of having to synthesize frequencies that
are integer multiples of the reference frequency, i.e. the divider value
is an integer. This becomes a problem if not catered for in advance in
the design. If the input is an integer, the '6 noise shaper input is
zero. Above, we have introduced an error to remove any fractional
spurs that may arise from limit cycles. That error will propagate in the
modulator and cause the accumulators to overflow in a determined
and cyclic manner causing spurious tones for integer frequencies. For
an input dc value of 0.998, Figures 4-12 and 4-13 show the PSD of the
modulator without and with dithering, respectively.
It can be clearly seen in Figure 4-12 that the modulator exhibits lowfrequency spurs due to insufficient dither. This problem is rectified by
effectively increasing the dither via introducing an initial seed [7] in the
modulator as illustrated in Figure 4-13. Figure 4-14 illustrates the phase
noise masks when 1-LSB and 5-LSB (nonzero initial condition)
dithering is applied to the modulator when operating with a fractional
division close to integer. With 5-LSB dithering the spurious level is
reduced at the expense of lifting the phase noise level.
4.3.3
Noise Folding
One important factor that deteriorates the close-in phase noise and that
is easily seen in measurement but not proven by simulation is the
effect of noise folding [2]. The platform developed in this research
proves this phenomenon with ease. Figure 4-15 shows the effect of
noise folding due to the PFD/CP nonlinearity. The high-frequency '6
quantization is folded back to within the loop bandwidth. This is
illustrated in the 10 dB deterioration of the phase noise plateau
rendering the fractional-N synthesizer unattractive. Fortunately, the
developed platform outlines this problem and shows how to mitigate
Figure 4-12. Modulator Output for DC input 0.998
Figure 4-13. Modulator Output for DC Input 0.998 with Dither Applied
61
62
Chapter 4
Figure 4-14. Effect of 1-LSB and 5-LSB Dithering for Close-to-Integer Divide Ratio
the PFD/CP nonlinearity. To solve the problem of noise folding, offset

charge pump current could be added to shift the PFD/CP gain characterristics to a linear operating region. Figure 4-16 shows the effect of introducing such currents on the phase noise profile. It is easily seen how
the phase noise is improved first with introducing a 5% offset current.
With 10% increase in offset CP for this case, it was possible to
mitigate the noise folding effect almost completely. It should be noted
that the amount of offset current is crucial and hence further increases
to its value might deteriorate the phase noise. This was observed in both
measured and simulation in the presented platform. With more than
12% increase in the offset CP current, the phase noise got worse and
hence demonstrated the presence of an optimum offset CP current to be
employed.
4.3.4 Effect of Prescaler Divider

The synthesized VCO frequency in the 34 GHz region warrants the
usage of high-frequency dividers. To reduce the power consumption in
those dividers, it is possible to employ a prescaler preceding the main
63
Figure 4-15. Effect of Noise Folding on phase Noise Profile Due to Noise Folding
Nonlinearity
Figure 4-16. Introduction of Offset Leakage current to Mitigate the Effect of Noise Folding
Due to Delta-Sigma Modulation
64
Chapter 4
divider that is controlled by the '6 modulator as shown in Figure 4-17.

However, this comes at a hefty price in phase noise performance as
will be illustrated in this section. Figure 4-18 shows the lifting of the
phase noise when a divide-by-4 prescaler is used to drive the multimodulus divider (MMD). This increases the '6 quantization noise by
12 dB. Therefore, it is recommended to incorporate the prescaler within
the main divider.
PFD/CP
LUT
)
40 MHz
= 40V
Tuning
Curve
Integrator
CP
Divider
'6 MMD
Frequency
Div-by-4
VCO
Frequency
VCO
phase
Figure 4-17. Phase-Domain Model for the Synthesizer Employing a Divide-by-4 Prescaler
Preceding the Main Feedback Divider
Figure 4-18. Deterioration of Phase Noise Performance due to Placement of a Divide-by-4

Prescaler before the Deltasigma-Controlled Multi-Modulus Divider
4.4
65
CONCLUSION
A thorough simulation-based system analysis of '6-based fractional-N

synthesizer was studied. This system was based on an implemented
model platform constructed with a combination of measured raw data
and behavioral Verilog-A models to speed up the simulation. It was
demonstrated that by having direct division versus the use of prescaler
preceding the main feedback divider controlled by the '6 modulator,
the quantization noise increases by 20*log10(N ) dB, where N is the
preceding divider value. It was also shown that the nonlinearities in
the CP/PFD combination cause the noise to fold back to the in-band.
Removing those nonlinearities shows the elimination of this
phenomenon. Hence, this platform has enabled the reproduction of all
witnessed behaviors in the laboratory of my first implemented
synthesizer chip that showed unpredicted phenomenon at the time.
The platform presented in this chapter can help predict accurately the
effect of nonlinearities of the frequency synthesizer subblocks on the
overall performance. The developed platform has aided the design and
successful implementation of the synthesizers presented in chapters 5
and 6, respectively.
REFERENCES
[1] Affirma RF Simulator (SpectreRF) User Guide, An Introduction to the
PLL Library: How the PFD Model Works.
[2] M.H. Perrott, M.D. Trott, and C.G. Sodini, A Modeling Approach for
SigmaDelta Fractional-N Frequency Synthesizer Allowing Straightforward Noise Analysis. IEEE Journal of Solid-State Circuits, 37 (8),
Aug. 2002.
[3] K. Kundert, http://www.designers-guide.com/Analysis/PLLnoise+jitter.pdf
[4] J. Crawford, Frequency Synthesizer Design Handbook. Equation (7.81)
on page 349.
[5] B. De Muer and M. Steyaert. CMOS Fractional-N Synthesizers.
[6] J. van Engelen, R. van de Plassche. Bandpass Sigma Delta Modulators.
[7] N.M. Filiol, T.A.D. Riley, C. Plett, and M.A. Copeland An Agile ISM
Band Frequency Synthesiser with Built-In GMSK Data Modulation,
IEEE Journal of Solid-State Circuits, 33 (7), July 1998.
[8] D. Banerjee, PLL Performance, Simulation and Design, 3rd edn., 2003,
National Semiconductor, (http://www.national.com/appinfo/wireless/files/
Deansbook3.pdf )
Chapter 5
MULTIMODE '6-BASED FRACTIONAL-N
FREQUENCY SYNTHESIZER
5.1
INTRODUCTION
In chapter 4, we performed system-level simulation to aid the

implementation of fractional-N synthesizers presented in this chapter.
Effects of the different subblocks in the PLL on the entire phase noise
of the closed-loop fractional-N synthesizer were monitored. In this
chapter, unconditionally stable '6 modulators of the third order
(namely MASH-1-1-1) are implemented and employed in a phaselocked loop fractional-N synthesizer providing a good average
estimate for fractional-N dividers. Using a deep sub micron 0.18 Pm
CMOS process with a supply voltage of 1.8 V, a '6-based fractional-N
synthesizer is designed, simulated, laid out, fabricated, and tested.
Results obtained from measurements on this synthesizer outperform
all synthesizers reported to date [16].
5.2
AN OVERVIEW
Fractional-N frequency synthesizers employing '6 noise shapers

have been developed extensively in the past decade [716] replacing
the conventional single accumulator-based synthesizer. Figure 5-1
shows the block diagram of a fractional-N frequency synthesizer.
Conventional fractional-N synthesizers employing first-order '6
modulator (single accumulator) are known to suffer greatly from
fractional spurs that occur every time the accumulator cyclically
67
68
Chapter 5
overflows to control the dual-modulus divider to switch between N + 1

instead of N [14].
VCXO
fref
Reference
Divider
fsamp
Charge
Pump
PFD
ffdbk
VCO
fout
Divider
'6
Modulator
N.K
Figure 5-1. Fractional-N PLL Frequency Synthesizer
Techniques to correct for those spurs include the use of analog

compensation [15] using a digital-to-analogue converter, which injects
an analog format of the error to cancel out the spurious signals.
However, those analog techniques require great precision and
matching, which is difficult to implement in practice rendering the
counter measures insufficient to totally suppress the spurious signals
within the band of interest.
Digital compensation techniques using higher-order '6modulators
have been demonstrated [7-12] to work well in dithering and shaping
the noise pushing it to high frequencies. The loop filter can therefore
filter out the noise at those frequencies.
In this chapter, the design and implementation of a complete
fractional-N PLL frequency synthesizer is described in details. The
synthesizer is designed using a commercial 0.18 Pm CMOS process.
All the subblocks including the PFD/CP, VCO, dividers, and loop
filter were optimized for implementation using simulation results
obtained in chapter 4.
69
Multimode '6-Based Fractional-N Frequency Synthesizer
5.3
A MULTIMODE MULTISTANDARD '6-BASED

PLL SYNTHESIZER DESIGN
The aim of this chapter is to show the results of a '6-based PLL

synthesizer operating in the 2.4/5 GHz region. A typical use of such a
synthesizer is in the WLAN standard 802.11a, b, and g. The synthesizer
(operates from a 1.8 V supply voltage and is simulated over PVT
Process [fast, slow, and typical], voltage [1.7, 1.8, and 1.9 V] and
temperature [40o, 40o, and 125o]) corners. The obtained performance
is excellent and supersedes most published results in the WLAN
arena. In what follows, the detailed design and implementation of the
synthesizer is described. The specification of each individual subblock
in the synthesizer is derived from the set of specifications shown in
Table 5-1.
5.3.1
Design Methodology
The first step is to devise the architecture for the frequency synthesizer
that covers all the frequency ranges shown in the specification table
(Table 5-1). A scheme based on oscillator synthesis that generates
two-thirds of the desired frequency mixed with a divided-by-2 version
of it is employed for the 802.11 standards. This architecture is shown
below in Figure 5-2. As can be seen from Figure 5.2, the required
frequencies of interest are not directly generated by the respective
voltage-controlled oscillators. That was done to avoid frequency
pulling in the transceiver [17].
Table 5-1. Frequency Ranges for the Proposed Synthesized Architecture
Parameters
Frequency
B, g
(GHz) for
a
802.11
Current consumption (mA)
Supply voltage (V)
Locking time (us)
Minimum
2.4
4.8
1.7
Nominal
20
1.8
224
Maximum
2.5
5.805
1.9
70
Chapter 5
f802.11a
f802.11b,g
/2
40MHz
VCXO
PFD
VCO1
VCO2
LF
CP
/2
MMD
n 6
'6
30
Figure 5-2. Proposed Synthesizer Architecture for 802.11WLAN Standards
The steps taken in the design of the proposed synthesizer

architecture are listed below.
1. Initial frequency planning is required for the employed oscillators
derived from the required synthesized frequencies of interest for
the 802.11a, b, and g WLAN standards [18].
2. VCO design is dictated by the specified phase noise requirement.
Phase noise requirement is typically derived from the standards
specification and usually derived from exhaustive system-level
simulation that relates the EVM and bit error rate (BER) to the
phase noise of the entire transmitter/receiver chain [18].
3. Once the frequencies of the oscillators are selected, the current
consumption for the front-end divide-by-2 prescalers is estimated.
4. The MMD architecture is determined based on its input frequency
(1.72.4 GHz for 802.11a, b, and g, respectively). A typical implementation of the MMD warrants the usage of a P/P + 1 dual-modulus
5.
6.
7.
8.
71
prescaler controlling two low-frequency counters, namely A and B

(see Appendix D).
The reference frequency of the crystal oscillator is chosen to be
high (40 MHz) to yield improved settling time and phase noise
performance. However, it can not be too high to worsen the system
performance (see the 20 log10(N) and a 10 log10( fsamp) contributions
to the phase noise plateau in Chapter 3).
To cover all the channels while preserving the switching speed, a
fractional divider is required and hence the use of a '6
modulator.
Once the VCO frequencies are selected, the limits for the required
division ratios needed are obtained.
The PFD and CP have to be modeled correctly to show the effect
of noise and nonlinearity on the performance of the entire PLL.
The simulation results obtained in chapter 4 aid the implementation

of the proposed synthesizer architecture. The implementation and
simulation of the individual subblocks of the PLL are described next.
5.4
THE '6 FREQUENCY SYNTHESIZER

SUBBLOCKS IMPLEMENTATION
5.4.1 The Phase-Frequency Detector

The PFD circuit used in the design presented in this chapter is based
on the standard Dual type flip-flop (DFF) circuit. Figure 5-3 shows
the block diagram of the PFD. Since the delay of the reset can affect
the PFD behavior in the vicinity of zero phase difference (e.g. dead
zone in the PFD characteristic as shown in Appendix A) [19], an
adjustable two-state delay circuit is added in the reset path. This
circuit allows the choice between two modes of short and long delay
in the reset line of the PFD.
The delay in the reset path is used when operating the synthesizer
in integer mode to get rid of the dead zone. The delay is minimized
when operating the synthesizer in fractional mode as the synthesizer
operates at an offset of the dead zone. One of the main contributions
to the phase noise from the PFD point of view is its inability to drive
the CP switches at the required high sampling frequency associated
with the fractional-N PLL. Figure 5-4 shows the implemented PFD
circuit using hand-crafted gates instead of the flip-flops to ensure the
72
Chapter 5
Ref
'1'
D
R
UP
Q
Q
Mux
delay
VCO
'1'
delay
set
D
R
DN
Q
Q
Figure 5-3. PFD with Enabled Delay in the Reset Path
Up
Ref
delay
Enable
Dn
VCOf
Figure 5-4. PFD Schematic Used in the Synthesizer
best noise performance. The UP and DN pulses are designed in order

to easily drive the required CP switches without compromising the inband phase noise due to the PFD.
73
This PFD is best simulated in conjunction with the CP to check for

the linearity of both blocks and the effect on the overall performance
of the frequency synthesizer. However, time-domain characterization
of the PFD in Figure 5-4 is found in Appendix A.
5.4.2
The Charge Pump
The behavioral model of the CP was shown in Figure 3-4 and repeated
here in Figure 5-5. In this section, a detailed circuit design for a CP is
described. CP parameters that affect the performance of the PLL are:
UP and DOWN current mismatches, unequal rise and fall times,
glitches, and feed-through [20]. Several circuit simulations that
characterize the CP are shown.
Vdd
Iup
SwP
Icp
Dn
SwN
Zs
Idn
Figure 5-5. Behavioral Model for the Charge Pump
A single-ended CP circuit was designed using a 0.18 Pm CMOS

process. The schematic of this CP is shown in Figure 5-6.
74
Chapter 5
Vdd
Up
P3
Vdd
N3
SwP2
SwP1
P2
P1
N4
N5
N2 Dn
SwN1
P8
P7
Iout
ip
P5
P6
'I
N9
Vdd
N1
P4
ip='I
Z(s)
N8
N6
N7
(a)
Vdd
Ip
+
Iout
Ib
Vss
(b)
Figure 5-6. Circuit Schematic of the Charge Pump (CP Block) used in the '6-based
Synthesizer (a) CP, (b) PushPull Op-amp in the CP circuit
The position of the UP and DN switches of Figure 5-5 was

swapped with the current sources to buffer the switching spikes at the
loop filter. SwP1 and SwN1 are the PMOS and NMOS UP and DN
75
Figure 5-7. UP, DN, and Charge Pump Currents versus Tuning Voltage
switches, respectively. P2 and N5 are the UP and DN PMOS and

NMOS current sources, respectively. Usually these UP and DN
currents are mismatched and for higher tuning voltage at the loop
filter, the UP current is smaller than the DN current and vice versa. A
typical DC performance of a unit 62.5 PA CP with the mismatch
cancellation technique disabled is shown in Figure 5-7. It is seen that
ICP deviates from its horizontal zero net when the tuning voltage
exceeds the 1.2 V value.
At PLL lock, there is a net current given by:
'I
I UP I DN
(5.1)
The role of this proposed architecture of Figure 5-6 is to minimize

the mismatch ('I ). This is achieved by using an always-on replica UP
and DN CP (P4, P7, N8, and N9) and a rail-to-rail op-amp in pushpull
architecture (figure 5.7). The op-amp senses the mismatch, from ip,
and feeds it back via N6, N7, P5, and P6 to the PMOS DN current as
illustrated by P8 PMOS current source. This will yield a near-zero
76
Chapter 5
mismatch between the UP and DN currents. A residual mismatch

helps suppress the spurious feed-through signals that modulate the
VCO and appear at the output of the synthesizer.
The mismatch cancellation technique shown in Figure 5-6 is useful
when the frequency synthesizer is operating in integer division mode.
However, as we will see later, this op-amp sensing cancellation
technique is disabled when operating the synthesizer in fractional
division mode. This is due to the need for an extra offset in the CP to
guarantee linearity of the PFD/CP combination (refer to chapter 4 for
more simulation details).
5.4.2.1 Dead-zone nonlinearity
The dead-zone issue is well known in integer PLL and is the

consequence of the PFD narrow output pulses as the PLL approaches
lock. Those pulses get smaller due to the finite reset pulse which is the
Figure 5-8. PFD/CP Linearity Curve (the Dead Zone Shown inside the Eclipse)
77
result of UP and DN pulses driving reset logic. Those pulses drive the
CP switch transistors that have some time constants related to their
input capacitances. Those switches cannot respond to small pulses and
never fully switch ON depending on the speed of operation, hence the
dead-zone effect.
Figure 5-8 shows the dead-zone nonlinearity plot for an ideal PFD
(with no delay in the reset path) driving a real CMOS CP. The
reference frequency used is 40 MHz.
Figure 5-9. Nonideal PFD Characteristic Showing the Dead zone
Figure 5-9 shows a zoomed in view around the dead-zone

nonlinearity region. The dead-zone nonlinearity causes an increase in
the in-band phase noise of the synthesizer due to the PFD not being
able to correct for small errors creating a state where the loop keeps
going into and out of lock all the time. The size of the dead-zone is
proportional to the PFD sampling clock speed and therefore becomes
78
Chapter 5
more serious at higher frequency. Correcting this problem is very

simple and requires the use of a longer reset pulse by putting a delay
in front of the reset logic. This ensures that the UP and DN pulses of
the PFD are ON for a longer period of time allowing the CP to
respond fully.
5.4.2.2 Linear Range and Cycle Slipping
Cycle slips due to PFD range limits in the PLL is a long-standing

problem that has been addressed in the past [21]. This issue arises if
the feedback VCO frequency and the reference frequency at the PFD
inputs are too different and their comparison phase error is too large
and falls outside the range of the PFD. This problem can cause the
PLL to cycle slip and hence increase its settling time. For fractional-N
PLL, this is of a concern only if the '6 modulator is of higher order.
This can be resolved by extending the range of the PFD.
5.4.2.3 DC Offset Current
When both PFD inputs are in phase, the PFD/CP combination is

subject to a dead zone in the characteristic curve. Moreover, if the
positive and negative currents are not exactly the same, there would
be a mismatch between the gains of the PFD/CP for positive and
negative phase difference between the inputs. This can degrade the performance of the PLL when used in the fractional-N mode because the
input of the PFD in this mode is never zero; instead, it is a variable
number with a zero mean. This poses more stringent requirements on
the PFD/CP in the fractional mode. One way to avoid the issues
around the zero is shifting the operating point away by adding some
offset current. This, in fact, gives a systematic phase offset which is
not important in a fractional synthesizer.
Figure 5-10 shows the schematic of the offset current circuit. The
output current of this circuit is not an absolute value. Instead, it adds
(or subtracts) a percentage of the CP current to the loop filter. Therefore, it should have the same topology as the CP with some extra
logic to control the offset current. This circuit has two control signals
79
Figure 5-10. Offset Current for the Charge Pump
(OFFSET<1:0>) that set the offset current. As shown in the table of

Figure 5.10, the offset current can have four values: 0, 10%, 20% or
10% depending on the control signals.
A positive current means a current provided by the PMOS
transistors and alternatively a negative current is drawn by the NMOS
transistors. The table on the right-top corner of the figure summarizes
the output current value based on control signals.
Figure 5-11 shows the CP blocks and their corresponding offset
current circuit. Each CP can have a current of 1 or 2 mA, depending
on CP<0>. The offset current is proportional to the total CP current.
For 1 mA CP current the offset is +100, +200, and 100 uA which
corresponds to +10%, +20%, and 10% respectively.
Figure 5-12 shows the schematic of the simulation setup for the
offset current and Figure 5-13 shows the transient response of the
offset current circuit.
80
Chapter 5
Figure 5-11. Charge Pump Block and Its Offset Current Block
Figure 5-12. Simulation Setup of the Offset Current Circuit
81
In this simulation, the control signals of the circuit are varied and the
output current is changing accordingly from 0 to 100, 200, and 100 PA
for a CP current of 1 mA (CP<0> = 0) and 200, 400, and 200 PA
for a CP current of 2 mA (CP<0> = 1).
Figure 5-13. Transient Response of the Offset Current Circuit
82
Chapter 5
5.4.2.4 PFD/CP Transient Simulation
Figure 5-14 shows the simulation setup of the PFD/CP circuit. In this
simulation, the output short circuit current of the CP is measured.
Figures 5-155-17 show the transient responses of the PFD and CP
outputs for three different cases in which the two inputs (a) have
almost the same phase, (b) the reference signal from the crystal is
leading, and (c) the output of the divider in the PLL is leading. As it
can be seen, there is always a positive glitch after the output is reset.
This is due to the extra delay in the signal that turns off the PMOS
switch of the CP and also the PMOS switch itself.
Figure 5-14. PFD/CP Simulation Setup
Figure 5-15. Transient Response of the PFD/CP (Case [a])
83
84
Chapter 5
Figure 5-16. Transient of the PFD/CP (Case [b])
85
Figure 5-17. Transient Response of the PFD/CP (Case [c])
5.4.3
3.6 GHz Voltage-Controlled Oscillator
The main types of oscillators employed in radio frequency synthesizers

are namely: the ring oscillator and the LC-tuned oscillator. The ring
oscillator is simple and is typically constructed with multistage
86
Chapter 5
inverters. The ring oscillator usually has worse phase noise performance
[22] and is not suitable for high-performance design as the one
presented in this chapter. Figure 5-18 shows a current supplied LC
VCO used in the design. This VCO provides an in-phase and
quadrature-phase signals (namely I and Q) as it is used to drive an IQ
image rejection mixer. The structure is fully differential as it offers
better power supply rejection. The LC oscillator is constructed using
all PMOS transistors as PMOS provide better noise performance since
they have lower flicker noise compared to their NMOS counterparts
[23] (more on that in Appendix B).
Vdd
X1
X4
X4
Vdd
Vdd
X4
X4
750u
Q- I+
Q+
I+
I-
Q+
I-
Q-
Vcntl
Vss
Figure 5-18. Simplified Schematic of the Implemented Quadrature VCO
The oscillator shown in Figure 5-18 employs a bank of tunable

varactors to cover the entire frequency range of interest for 802.11a, b,
and g (see Table 5-1). The oscillation is obtained for the described
VCO and it is illustrated in Figure 5-19 for the middle tuning range of
0.9V (3.663 GHz).
Figure 5-19. VCO Oscillations for the Mid-tuning Range
Figure 5-20. Phase Noise Profile for the Employed LC VCO
87
88
Chapter 5
Figure 5-20 shows the simulated phase noise profile VCO. The
phase noise at 100 kHz offset from the carrier is 103 dBc/Hz and at
20 MHz is 156 dBc/Hz.
Figure 5-21 shows the simulated VCO tuning curves covering all
the VCO-synthesized frequencies for 802.11 standards. These are the
synthesized frequencies at point X in Figure 5-2.
Figure 5-21. VCO Tuning Curves for all WLAN Bands
Figure 5-22. VCO Gain KVCO in MHz/V
89
The gain of the VCO is directly derived from the simulated data in
Figure 5-21 and is shown in Figure 5-22 for VCO1 and VCO2.
5.4.4
The Multimodulus Divider
The MMD employed in the designed synthesizer incorporates a P/P

+1 dual-modulus divider (in this case 8/9) designed in current-mode
logic (CML) technology. The P/P + 1 divider controls two lowfrequency dividers A and B whose control bits are derived from the
fractional divider noise shaper as discussed in the following section.
The A and B counters are implemented in CMOS technology.
Figure 5-23. Multimodulus Divider Used in the Designed Synthesizer
The block diagram of this MMD is shown in Figure 5-23. The

MMD circuit and system implementations are described in detail in
Appendix D, however, its operation is shown briefly below:
90
Chapter 5
5.4.4.1 MMD Operation
1. B and A are loaded (B t A) and modulus control = low, the

prescaler divides by P + 1.
2. Counters decremented after rising edge of prescaler until counter A
reaches 0.
3. Modulus control = high, the prescaler divides by P until the
content of B is 0.
4. Counters are reset and cycle begins again.
5. Prescaler divides by P + 1 for A and by P for (BA). The total
division is BP + A.
5.4.5
The Fractional Noise Shaping Coder

(the '6 Modulator)
In implementing the '6-based fractional-N frequency synthesizer, a

close look at the hardware implementation of the noise-shaping
modulator is required. In the next few pages, a detailed design
description of the implementation of the MASH-1-1-1 '6 modulator
is given [28]. A step-by-step methodology is used from linear system
model to actual hardware implementation. The basic system-level
block diagram of the '6 modulator was shown in Figure 3-17 and its
implementation is detailed below.
5.4.5.1 The Digital Accumulator and the First-Order Linear Model
Figure 5-24 shows the first-order linear model of the '6 modulator
and its hardware accumulator-based implementation. To establish the
link between the model and the hardware implementation, its time
domain behavior is first analyzed.
Using Figure 5-24, the time-domain equations of the '6modulator
are as follows:
u[n]
X b[n 1]
v[n] u[n] v[n 1]
(5.2)
(5.3)
91
u[n]
X[n]
6
+ 6
-
v[n]
-1
-1
E[n]
b[n]
X(n) m
b(n)
X+Y
m
-E[n]
-E(n)=v(n)-b(n)
(a) Linear Model
Latch
(b) Hardware Implementation
Figure 5-24. The First-Order modulator (a) Linear Model, (b) Hardware Implementation
b[n]
1 if v[n] t 0
1 otherwise
(5.4)
The quantization error is defined as:

E[n] b[n] v[n]
(5.5)
Substituting equation (5.3) in equation (5.2), yields

v[n]
X b[n 1] v[n 1]
(5.6)
Substituting equation (5.5) in equation (5.6), yields

v[n]
X E[n 1]
(5.7)
To illustrate the equivalence between the modulator and the

accumulator, the following example is considered:
x No. of input bits m = 2
x Maximum accumulator range = 3
x Input X = 2, Input Y = 2
92
Chapter 5
On the next calculation cycle, the accumulator content and the

carry are shown in equations (5.8) and (5.9), respectively:
E[n] 1
(5.8)
b[n] 1
(5.9)
Straightforward accumulation and quantization is assumed, then

v[n]
Hence E[n]
(5.10)
X Y
1 and
(5.11)
Accumulator content = E[ n] 1
5.4.5.2 The 30-bit Structural MASH Coder Implementation
Using the above-described analogy between the digital accumulator

and the first-order '6 modulator, the digital implementation of the
MASH-1-1-1 '6 modulator of Figure 3-17 is shown in Figure 5-25.
Y[n]
6
X[n]
LATCH
C1[n]
X+Y
LATCH
C2[n]
-e1[n]
C3[n]
LATCH
X+Y
-e2[n]
LATCH
X+Y
Y
LATCH
Figure 5-25. Third-Order Noise Shaper Hardware Implementation
93
The third-order MASH '6 modulator of Figure 5-25 is

implemented using 30 bits representing the divider value, with 6 bits
for integer part, and 24 bits for the fraction part. The clock speed
(sampling clock) at what the modulator can operate up to is critical.
This is very important since the higher the clock of operation, the
better is the noise shaping.
Other requirements such as area and/or power consumption can
also be important depending on the application. However, since noise
performance is critical in frequency synthesizers, the speed of
operation forms a major part of the modulator design.
5.4.5.3 The 24-bit Pipelined Adder Design
The implementation of high-speed accumulators is the most important

part in the implementation of the modulator. Each accumulator is
implemented using a 24-bit pipelined adder. The resolution of the
accumulator can easily be calculated using the frequency error
allowed in the IEEE standards specification [18].
Figure 5.26a shows the implementation of the adder of the first
accumulator stage and Figure 5.26b the adder implemented in the
subsequent accumulators.
The 24-bit pipelined adder is implemented using three-stage 8-bit
carry look-ahead (CLA) adders to achieve very high clocking speed.
Since at each CLA stage, the output is calculated during one clock
cycle, the second-stage input is delayed one clock cycle and the thirdstage CLA input is delayed two clock cycles. The clocked delays
synchronize the output of the CLA adders so that the output of the 24bit adder is arrives at the same time. The implementation of the 8-bit
CLA adder uses the following logic equations:
Si X i Yi x ( X i x Yi ) Ci
Ci1 X i Yi x X i x Yi Ci
(5.12)
Where Si is the ith full sum of the ith input vectors and Ci + 1 is the
carry of the next operation.
94
Chapter 5
C in '0'
24-bit Pipelined Adder

CLA
C in 8-bit C out
1-bit
Latch
x(23:0)
8-bit
Latch
24
s(23:0)
1-bit
Latch
16-bit
Latch
8-bit C
CLA out
C in
24
C in
8-bit C
CLA out C 1
clk
24 y(23:0)
Cout
(a)
1-bit
Latch
clk
Cin
8-bitC
CLA out C1
y(23:16)
8-bitC
CLA out
x(23:16)
clk
Cin
y(15:8)
1-bit
Latch
x(15:8)
y(7:0)
x(7:0)
8-bitC
CLA out
s(23:16)
s(15:8)
s(7:0)
(b)
Figure 5-26. Pipelined 24-bit Adder (a) for First-stage Accumulator, (b) for Subsequent
Stages
95
5.4.5.4 Error Cancellation Algorithm
Using the accumulator-based implementation of Figure 5-25, the

modulated fractional output with respect to the accumulators overflow
is given by [2426]:
Yout3 ( n )
k 1
r 1
(1)
r 1
(5.13)
. D r . Ck n r 1
where D r are the coefficients taken from Pascals triangle.

Equation (5.13) represents the error cancellation algorithm due to the
integration mechanism of the second and third accumulators. The
correction is implemented by equally weighted differentiators.
Expanding equation (5.13) gives:
Yout3 ( n )
C1
C2
C3
C1 ( n ) C2 ( n ) C2 ( n 1) C3 ( n ) 2C3 ( n 1)
+ C3 ( n )2
Logic1
3-bit
Latch
+
C2(n-1)
C3(n-1)
C3(n-2)
Logic2
(5.14)
Yout(n)
CLK
Figure 5-27. Error Cancellation Network
Figure 5-28 shows the implementation of the error cancellation

algorithm based on the 2s complement network of Figure 5.27. The
Mapping Logic1 (Map_log1) and Mapping Logic2 (Map_log2) are
determined by the truth table shown in Table 5-2 and implemented
using the logic of equations (5.15) and (5.16), respectively. Figure 5-29
96
Chapter 5
Table 5-2. Error Correction Network and Logic 1 and Logic 2 Truth Tables
C1
0
0
0
0
1
1
1
1
C2
0
0
1
1
0
0
1
1
C3
0
1
0
1
0
1
0
1
Out1
0
1
1
2
1
2
2
3
C2(n 1)
0
0
0
0
1
1
1
1
C3(n 1)
0
0
1
1
0
0
1
1
C3(n 2)
0
1
0
1
0
1
0
1
Out2
0
1
2
1
1
0
3
2
and Table 5-3 show the special 2s complement representation and the
special handling of number 4.
ML2
Map _ Log1
ML
1
C2 x C1 C3 (C3 x C1 )
C x C x C C x C C x C x C (C x C )
1
3
2
1
3
1
3
2 1 3
(5.15)
ML1
Map _ Log 2 ML2

ML
3

A
B
C

A B C A
B C B C
A B xC
x
x B
1 - b it
Latc h
cl
k
B
C
cl
k
1 - b it
Latc h
C3
C3
1 - b it
Latc h
1 - b it
Latc h
1 - b it
Latc h
C2
C2
cl
k
C1
1 - b it
L atc h
(5.16)
ML1
M a p p ing M L
2
L og ic 2
'0 '
X
Y
M L3
M a p p ing
L og ic 1
M L1
Y
M L2
'0 '
Y
C1
Figure 5-28. Error Correction Algorithm Implementation
C o ut
A d d er
y3
C in
C o ut
A d d er
y2
C in
C o ut
A d d er
C in
y1
97

Table 5-3. 2s Complement Arithmetic with Specila Handling of Number 4
Yout(2)
0
0
0
0
1
1
1
1
Yout(1)
0
0
1
1
0
0
1
1
Yout(0)
0
1
0
1
0
1
0
1
Mapping
000000
000001
000010
000011
000100
111101
111110
111111
Figure 5-29. Divider Interface
5.4.5.5 Design Issues: Limit Cycle Cancellation in Fractional Mode
One of the consequences of using '6 modulators with DC inputs is

the presence of limit cycles or spurs [1] that are strongly visible for
inputs that are inverses of power of 2 such as 0.75, 0.5, and 0.25. This
is due to the fact that the binary representation of such DC values has
much less randomness. Figures 5-30 and 5-31 show the noise
spectrum for 0.5 DC input with and without spurious limit cycles in
linear and log scales, respectively.
The effect of these limit cycles is greatly reduced as we introduce
dithering (or randomness). Here, the spurs have been eliminated by
introducing an error in the LSB or the input word [1].
98
Chapter 5
Dithering (Linear Plot)
Dithering (Log Plot)
99
5.4.5.6 Design Issue: Integer Mode and Close-to-Integer Option
One of the practical issues that are often overlooked in fractional-N PLL
designs is the problem of having to synthesize frequencies that are integer
multiples of the reference frequency, i.e. the divider value is an integer.
This becomes a problem if not catered for in advance in the design.
If the input is an integer, the '6 noise shaper input is zero.
Previously, we introduced an error to remove any fractional spurs
that may arise from limit cycles. That error will propagate in the
modulator and cause the accumulators to overflow in a determined
and cyclic manner causing spurious tones for integer frequencies.
Figures 5-32 and 5-33 show that the modulator behaves like a secondorder '6 with small DC input that eventually produces fractional spurs.
It is advisable to bypass the noise shaper when selecting to operate
in integer division in the synthesizer. In other words, only use the '6
noise shaper when operating the synthesizer in fractional mode.
Figures 5-34 and 5-35 show the spectral densities of the modulator
when the input is a DC with values of 0.998 and 0.005, respectively.
It can be clearly seen that for both cases, the modulator exhibits lowfrequency spurs due to insufficient dither. This problem is rectified
by effectively increasing the dither via the introduction of an initial
seed [1] in the modulator as illustrated in Figure 5-36.
Figure 5-32. Modulator Output in Integer Mode, Linear Plot
100
Chapter 5
Figure 5-33. Modulator Output in Integer Mode, Logarithmic Scale
Figure 5-34. Modulator Output for DC Input 0.998
101
Figure 5-35. Modulator Output for DC input 0.005 Showing Low-Frequency Spurs due to
Insufficient Dither
Figure 5-36. Increasing Dither Suppresses the Spurs to Some Extent in the Fractional-N
Modulator for Close-to-Integer Divider Values
102
5.5
Chapter 5
MEASURED PERFORMANCE
OF THE IMPLEMENTED SYNTHESIZER
All the subblocks of the implemented synthesizer have been described.

In what follows, we describe detailed performance of the implemented
synthesizer and compare the obtained results with published performance of similar state-of-the-art synthesizers.
Figures 5-37 and 5-38 show a detailed block diagram and a
photomicrograph of the fabricated synthesizer, respectively. It must be
noted that this synthesizer was incorporated in an entire transceiver.
The synthesizer performance was also monitored at the transmit node
to show the effect of several anomalies of the RF section on the
overall synthesizer performance.
Figure 5-37. Detailed Block Diagram of the Fractional-N Synthesizer
This synthesizer was fabricated in 0.18 Pm mixed-mode CMOS

process and was incorporated in an entire transmitter/receiver chip
whose die size is 17 mm2 [6]. The synthesizer/VCO chip area is 2
mm2. The entire chip is packaged in a 64-pin micro-lead frame (MLF)
and operates from a 1.8 V power supply. The entire LO generation
consumes 20 mA including the synthesizer and VCO. A 3.3 V power
supply is also provided for chip I/Os.
103
The measured band switching curves are shown in Figure 5-39 for
the VCO1 part. They correlate pretty well with those simulated and
Figure 5-38. Synthesizer Photomicrograph
104
Chapter 5
Figure 5-39. Measured Switching Curves for the Implemented VCO1 at LO Frequency
Figure 5-40. 802.11g Synthesizer-Measured Frequency Spectrum
105
The spectrum at the output of the local oscillator is shown in

Figure 5-40. Adjacent 20 MHz-spaced channels are shown for the
802.11g case. The 2442 MHz was measured with a 5 kHz resolution
bandwidth whereas the 2462 MHz was measured with a 200 Hz
resolution bandwidth. No reference or fractional spurs are visible
above 70 dBc for close-in or 68 dBc for far-out offset frequencies.
The frequency synthesizer achieves an integrated phase error of
0.54o/1.1o for 2/5-GHz band with a loop filter bandwidth of 400 kHz
[6]. This is illustrated in Figure 5-41. The LO signal is monitored and
FM demodulated while the receiver and transmitter are switched on
and off, respectively. It is found that the LO signal settles to 2 ppm
(<5 kHz) of accuracy within 4 s, indicating a fast settling of the PLL.
This is shown in Figure 5-42.
Figure 5-41. Phase Noise Profile of the Synthesizer for 802.11a, b, and g
106
Chapter 5
Figure 5-42. PLL During Receive/Transmit Switch
Figure 5-43. 64-QAM Constellation and EVM at the Output of the Transmitter
107
Figure 5-43 shows the measured transmit constellation and EVM

for the 802.11g standard showing the minimized phase noise effect of
the employed synthesizer.
5.6
SUMMARY AND CONCLUSION
In direct-conversion WLAN transceivers, the required LO frequency

coincides with the RF, which entails adverse effects such as LORF
interaction and VCO frequency pulling. Hence, an LO generation
scheme that consists of a quadrature VCO operating at two-thirds of
the LO frequency and a divide-by-2 circuit producing quadrature
outputs at one-third of the LO frequency is employed.
Two quadrature mixers subsequently multiply the VCO signal by
the divide-by-2 signal to generate the quadrature LO signals (upper
band), with significant suppression of the undesired lower band at
one-third of the LO frequency, alleviating the image problem in the
receiver and the spurious emission problem in the transmitter.
The quadrature LO signals for the 2-GHz bands are then generated
by dividing the 5-GHz LO signal by two. Two quadrature VCOs are
used (VCO1: 3.23.6 GHz, VCO2: 3.53.9 GHz) in order to cover the
required frequency range with enough margins for PVT variations.
The main challenge in the frequency synthesizer design for this
multistandard transceiver lies in reducing the in-band phase noise
while maintaining a fast loop locking time [15]. Phase noise degrades
signal EVM by introducing inter-subcarrier interferences. A narrower
loop filter BW reduces out of band phase noise.
On the other hand, during receive/transmit switching, the existing
perturbation to the VCO produces a transient LO frequency offset. If
the loop filter BW is narrow and the loop takes too long to settle,
frequency estimation in the baseband modem becomes inaccurate,
thus degrading the total system performance. These two seemingly
conflicting requirements can be fulfilled with the described fractionalN PLL.
The main advantage of a fractional-N PLL is that it breaks the
traditional relationship between the channel spacing and the reference
frequency in an integer-N PLL. By having a fractional divider, the
reference frequency can be much higher, thus reducing the overall
division ratio and in-band phase noise floor.
Moreover, with a higher reference frequency, the PLL loop BW
can be increased to reduce the locking/settling time.
108
Chapter 5
An automatic VCO band selection scheme is employed [12, 16].

Designed in a 0.18 Pm process, the 8/9 prescaler works well above 4
GHz. The N-counter consists of an 8/9 prescaler and a 7-bit pulseswallow A/B counter. A 4-bit A counter with a 3-bit B counter covers
the required frequency range.
The '6modulator employs a third-order noise-shaping (MASH)
architecture for its higher-order noise shaping capability and better
stability than a single loop high-order modulator [17]. The final
'6MASH modulator is programmed by a 27-bit digital word with
7-bit in the integer portion and 20-bit in the fractional portion,
producing a minimum frequency step of 38.2 Hz (relative to VCO
frequency), more than sufficient for any standard channel-spacing
requirement.
As a noisy digital circuit, the modulator may generate substantial
cross talk noise. Since the VCO is an analog component, running
continuously, it should be placed sufficiently far away from the
'6modulator with proper isolation guard rings. Furthermore, noise
cross talk between the modulator and the PFD/CP can also produce spurs
and degrade phase noise.
Table 5-4. Performance Comparison with Other State-of-the-art Work
Work
Process
PLL
type
Int-N
Freq.
Rategh
2000
0.24
um
CMOS
Liu
2000
0.25
um
CMOS
Int-N
5
GHz
Zargari
2002
0.25
um
CMOS
Int-N
5
GHz
8
MHz
250
kHz
This
work
0.18
um
CMOS
FracN
56
GHz
40
MHz
400
kHz
4.8
5
GHz
PFD
freq.
11
MHz
Loop
BW
280
kHz
Lock
time
4 uS
PN @
Offset
101
dBc/Hz
@1
MHz
112
dBc/Hz
@1
MHz
112
dBc/Hz
@1
MHz
113
dBc/Hz
@1
MHz
Power
Vsup
25
mW
3V
180
mW
2.5 V
36
mW
1.8 V
In this design, the '6modulator and the instant divider ratio

loading flip-flops (DFFA, DFFB) are negative edge-triggered.
Knowing that the duty cycle of the feedback signal Nout (see Figure
5-39) is almost always less than 10%, the '6modulator and the
divider ratio loading will have enough time to settle before Nout goes
109
high and the PFD/CP becomes active. In essence, noise cross talk is
avoided by time-domain isolation.
As a conclusion, in this chapter, the author has detailed the design
and performance of a multimode fractional-N synthesizer. The
synthesizer was designed as a local oscillator and constructed as part
of a complete direct conversion transceiver. The measured results
obtained for this synthesizer supersede most published results (see
Table 5-4). The developed platform of chapter 4 has helped the
designed synthesizer in achieving the best performance to date. In
chapter 6, we propose a new adaptive and enhanced synthesizer
architecture that offers optimum performance.
REFERENCES
[1] N.M. Filiol, T.A.D. Riley, C. Plett, and M.A. Copeland An Agile ISM
Band Frequency Synthesiser with Built-In GMSK Data Modulation,
IEEE Journal of Solid-State Circuits, 33 (7), July 1998.
[2] B. De Muer, M.S.J. Steyaert A CMOS Monolithic -Controlled
Fractional-N Frequency Synthesizer for DCS-1800, IEEE Journal of
Solid-States Circuits, 37 (7), pp. 835844, July 2002.
[3] Z. Shu, Ka Lok Lee, B.H. Leung A 2.4-GHz Ring-Oscillator-Based
CMOS Frequency Synthesizer with a Fractional Divider Dual-PLL
Architecture, IEEE Journal of Solid-States, 39 (3), pp. 452462, Mar.
2004.
[4] P. Zhang, T. Nguyen, C. Lam, D. Gambetta, T. Soorapanth, B. Cheng,
S. Hart, I. Sever, T. Bourdi, A. Tham, and B. Razavi, A Direct-Conversion
CMOS Transceiver for IEEE 802.11a WLANs, ISSCC Digest of
Technical Papers, pp. 354355, Feb. 2003.
[5] P. Zhang, T. Nguyen, C. Lam, D. Gambetta, T. Soorapanth, B. Cheng,
S. Hart, I. Sever, T. Bourdi, A. Tham, and B. Razavi, A 5-GHz DirectConversion CMOS Transceiver, IEEE Journal of Solid-State Circuits,
38 (12), pp. 22322238, Dec. 2003.
[6] P. Zhang, L. Der, D. Guo, I. Sever, T. Bourdi, C. Lam, A. Zolfaghari,
J. Chen, D. Gambetta, B. Cheng, S. Gower, S. Hart, L. Huynh, T. Nguyen,
and B. Razavi, A CMOS Direct-Conversion Transceiver for IEEE
802.11a/b/g WLANs, IEEE Custom Integrated Circuits Conference,
Digest of Technical Papers, Sect. 18, No. 4, Oct. 2004.
[7] T.A.D. Riley, M.A. Copeland, and T.A. Kwasniewski, DeltaSigma
Modulation in Fractional-N Frequency Synthesis, IEEE Journal of
Solid-State Circuits, 28, pp. 553559, May 1993.
Proceedings of IEEE 44th Annual Symposium Frequency Control, 1990,
pp. 559567.
IEEE Transactions on Instrumentation Measurements, 40, pp. 578583,
June 1991.
110
Chapter 5
[10] M. Kozak, I. Kale, A. Borjak, and T. Bourdi, A Pipelined All-Digital

[11] B.M. Miller, HP Multiple-Modulator Fractional-N Divider, US Patent
No 5,038,117, 6 Aug. 1991.
[12] T.A.D. Riley, Osgoode, Canada Frequency Synthesizers Having
Dividing Ratio Controlled by SigmaDelta Modulator, US Patent No.
4,965,531, 23 Oct. 1990.
[13] C.E. Hill, Sciteq/Osicom All Digital Fractional-N Synthesizer for High
Resolution Phase Locked Loops, Applied Microwave and Wireless,
Nov./Dec. 1997.
[14] Cosmo Little, Fractional-N Synthesisers, Electronics World, Mar. 1996.
[15] B.G. Goldberg, Sciteq Electronics Inc. The Evolution and Maturity of
Fractional-N PLL Synthesis, Microwave Journal, Sept. 1996.
[16] U.L. Rohde, Synergy Microwave Corp. Fractional-N Methods Tune
Base-Station Synthesizer, Microwaves & RF, Apr. 1998.
CMOS Transmitter with Harmonic-Rejection Mixers, IEEE SolidState Circuits Conference, 2001. Digest of Technical Papers, 2001 IEEE
[18] IEEE 802.11 Drafts Standards, http://grouper.ieee.org/groups/802/11/
[19] H.O. Johansson, A Simple Precharged CMOS Phase Frequency
Detector, IEEE Journal of Solid-State Circuits, 33 (2), pp. 295299, Feb.
1998.
[20] B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River, NJ,
1998.
[21] P.V. Brennan, Phase-Locked Loops, Principles and Practice, McGrawHill, New Jersey 1996.
[22] S. Verma, J. Xu, and T.H. Lee, A Multiply-by-3 Coupled-Ring
Oscillator for Low-Power Frequency Synthesis, IEEE Journal of
Solid-State Circuits, 39 (4), Apr. 2004.
[23] H.-W. Chiu, Y.-C. Chen, and S.-S. Lu, Optimization of CMOSIntegrated LC Oscillators using the Generic Algorithm, Microwave
and Optical Technology Letters, 42 (2), July 20, 2004.
[24] T. Bourdi, et al., A Novel Delta-Sigma Based RF Frequency
Synthesizer Architecture For Cellular Applications, IEEE Transactions
of Instrumentation and Measurement, Under Review, Submitted June
2002.
[25] T. Bourdi, et al., Agile Multi-band Delta-Sigma Frequency Synthesizer
Architecture, IEEE International Symposium on Circuits and Systems
2002 (proc ISCAS 2002).
[26] T. Bourdi, et al., A Delta-Sigma Frequency Synthesizer with Enhanced
Phase Noise Performance, IEEE Instrumentation and Measurement
Technology Conference, May 2002.
[27] A. Borjak, T. Bourdi, Intermodulation Products in a Mixer Subjected
to a Multi-Carrier Signal, Microwave Journal, Jan. 2002.
[28] M. Kozak, I. Kale, A. Borjak, and T. Bourdi, A Pipelined All-Digital
DeltaSigma Modulator for Fractional-n Frequency Synthesis, IEEE
Instrumentation and Measurement Technology Conference, May 2000.
Chapter 6
IMPROVED PERFORMANCE FRACTIONAL-N
FREQUENCY SYNTHESIZER
6.1
INTRODUCTION
In chapter 5, we detailed the design, implementation, and measurement

of a multimode fractional-N frequency synthesizer for WLAN standards.
The synthesizer offered the best performance to date. However,
additional circuit could be designed to enhance the performance of the
synthesizer at the cost of increased circuit complexity. Those additions include adaptive CP architecture to maintain loop gain and phase
transfer functions while operating in fractional mode, i.e. instantaneous different integer divisions. Also included is an adaptive band
switching control to maintain frequency agility while offering optimum
phase noise performance in the band of interest. Along with other
additional techniques that improve the synthesizer performance, those
additions will be described in this chapter in detail.
6.2
OVERVIEW
Figure 6-1 shows the basic fractional-N architecture that was implemented in chapter 5. Several circuit techniques could be added to this
synthesizer architecture to enhance its performance.
111
112
VCX
O
Chapter 6
fref
Reference
Divider
fsamp
Charge
Pump
PFD
ffdbk
fout
VCO
Divider
'6
Modulator
N.K
Figure 6-1. Conventional Fractional-N Synthesizer Architecture
Half-Band
Improved Band
Switching
VCXO
fref
/
R
fsamp
PFD
Noise Shaped
Charge
Pump
ffeedback
Loop
Filter
Vtune
VCO
Mult
i
Modulus
Divider
ffeedback
Noise
Shaper
Nfrac
fref
+
-
A/D
Controller
Reg1
Reg2
Figure 6-2. Fractional-N Synthesizer with Enhanced Performance
fout
Improved Performance Fractional-N Frequency Synthesizer
113
Those circuit improvements are shown in Figure 6-2 using the

dashed blocks and lines and are identified as follows:
1. '6-controlled adaptive CP architecture
2. VCO gain calibration to maintain best loop dynamics for best
phase noise performance
3. Improved VCO band switching to maintain linear PLL gain
operation
Those improvements could be used jointly for best performance.
Each one of those is described in detail in the next few pages and
measured results based on all these joint techniques applied to the
synthesizer are shown at the end of the chapter.
6.3
DELTASIGMA-CONTROLLED ADAPTIVE
CHARGE PUMP
'6-based fractional-N frequency synthesizers similar to the ones

described in chapter 5 have been introduced to alleviate integer-N
PLL frequency resolution problems as the requirement for fast
switching time and low phase noise become increasingly stringent.
Until recently [15], the use of noise shaping has been limited to
fractional divider control. The '6 modulator generates a pseudorandom
sequence of bits representing random integer divider values, at the
speed of the sampling clock, yielding an average fractional divisor to
synthesize the required frequency whose resolution is a fraction of the
sampling clock frequency. These instantaneous divider variations
continuously alter the PLL loop dynamics and deteriorate phase noise
performance.
In what follows, we will describe a new fractional-N synthesizer
architecture based on an adaptive CP that was fully implemented in an
RF CMOS process and show measured phase noise results that satisfy
several system requirements.
6.3.1
PLL Gain and Phase Variations
In conventional '6 fractional-N synthesizers the divider ratio is

modified while the CP current is fixed. This alters the loop dynamics
that impact the phase noise performance. It also has direct influence
on the PLL open loop dynamics, as is proven in the following
derivation.
114
Chapter 6
The open loop gain of the PLL synthesizer of Figure 6-1 at the
averaged fractional divider ratio is given by:
Aolaverage
I cp F ( s )
K vco
N frac
(6.1)
Icp is the CP current,

F(s) is the loop filter impedance transfer function,
Kvco is the VCO gain, and
Nfrac is the operating fractional division.
Also, the open loop gain of the PLL synthesizer with the
instantaneous divider ratio Ninst is given by [6, 7]
Aolinst
I cp F ( s )
K vco
s N inst
N 2 m 1 1 N inst N 2 m 1
(6.2)
(6.3)
N is the integral part of Nfrac and m is the order of the '6MASH

modulator. Therefore, the output of a third-order MASH modulator
would vary between 3 and 4 and equation (6.3) becomes:
N 3 N inst N 4
(6.4)
The closed-loop equation for the PLL with the average case is
given by:
Aclaverage
Aolaverage
1 Aolaverage
(6.5)
and the closed loop equation for the PLL with the instantaneous case
is given by:
Aclinst
Aolinst
1 Aolinst
(6.6)
115
Notice here that since equations (6.1) and (6.2) yield different results,
equations (6.5) and (6.6) also yield different results. So the higher the
order of the '6 modulator, the larger the divider variations and
consequently the more loop gain and phase disturbances, as shown in
Figure 6-3.
Closed Loop Gain (dB)
3.5
Nmin
3
2.5
Ncenter
2
1.5
Nmax
1
0.5
Closed Loop Phase (rad)
10
-0.6
-0.8
Nmin
-1
Ncenter
-1.2
Nmax
-1.4
-1.6
10
Frequency (Hz)
Figure 6-3. Closed-Loop Gain and Phase Characteristics
The example given here illustrates a typical system and clearly

shows the gain and phase variations during the synthesis of the middle
frequency band. A solution to this problem has been reported in [6, 7],
alleviating these issues by introducing an adaptive noise-shaped Charge
Pump (NSCP) architecture (see the block diagram in Figure 6-2 in
orange color), which is controlled by the same '6 modulator that is
controlling the divider. Manipulating equations (6.1)(6.5) the new
proposed PLL architecture is achieved.
116
Chapter 6
The modified open-loop equation that takes into account the

above-mentioned variations is then given by:
Aolinst
I cp(inst) F ( s )
K vco
s N inst
(6.7)
where the Icp(inst) is the instantaneous adaptive CP value that is directly

controlled by the '6 modulator. Notice that since Ninst changes
according to equation (6.5) for a third-order modulator, Icp(inst) would
be varying accordingly to keep the value of Aolinst Aol .
Aol is the open-loop gain corresponding to the case with the PLL
running at the instantaneous integral divisor N and is given by:
Aol
I cp F ( s )
K vco 1
s N
(6.8)
where I cp is the nominal CP current (corresponding to PLL case with

integral division N) that around which I cp(inst) varies. For a third- order
modulator I cp(inst) is then given by:
I N 4 I cp(inst) I N 3
(6.9)
I N 4 is the minimum CP value and corresponds to the case of the

instantaneous divider having a maximum value of N 4 and I N 3 is
the maximum CP value and corresponds to the case of the

instantaneous divider having a minimum value of N 3 .
The new closed-loop equation for the proposed architecture would
then be given by equation (6.6) but with Aolinst Aol .
6.3.2
Charge Pump System
Figure 6-4 shows the system overview of the control of the implemented
adaptive CP architecture. The coding method employed on the b bits
is thermometer coding as used in current-segmented digital-to-analog
converters [8]. The outputs of the thermometer encoders control two
banks of UP and DOWN CP circuitry.
117

b<5:3> Thermometer M<7:1>
b<5:0>
Encoder 3to 7
bits
D
ck
UP
Q
Thermometer L<7:1>
Encoder 3to 7
b<2:0>
bits
IupMatrix
Encoder
Control Logic
& Unit Cells
Iup
ck
IdownMatrix
Encoder
Control Logic
& Unit Cells
DOWN
Idown
ck
Figure 6-4. Adaptive Charge Pump Architecture
6.4
SYNTHESIZER LOOP CALIBRATION
Calibrating the PLL synthesizer to maintain a constant loop gain and

phase is very important, as these variations affect the phase noise
performance due to the CP and loop filter elements. The loop gain
affects the loop bandwidth, phase noise performance, and predistortion
matching. Equation (3.1) shows that the loop gain is determined by
the CP current, Icp, the VCO gain, KVCO, divider ration, N, and the
loop filter capacitance.
In a multimode PLL frequency synthesizer, the integrated loop
filter pole and zero locations, vary greatly from frequency to
frequency, as well as with process. The pole and zero locations are
determined by the loop filter RC time constant.
To minimize the CP current and loop filter noise contribution to
the VCO, the CP current and loop filter need to be designed to meet
phase noise specifications with the worst KVCO gain at nominal. This
will make sure exceeding or at least meeting those specifications after
the final calibration is done.
Starting from the previously defined loop gain in chapter 3 as
shown in equation (3.1), the actual loop gain constant may be
expressed as a function of the typical loop gain and the loop element
physical and process tolerances:
118
Chapter 6
Aol
( I CP I CP .' Icp ).( K VCO K VCO .' Kvco )

( N nom N nom ' N ).(Cnom Cnom ' C )
(6.10)
The delta terms in equation (6.10), represent the variations or

tolerances from the nominal or desired values. Similarly we can derive
the typical RC time constant as:
RC ( Rnom Rnom .' R ).(Cnom Cnom .' C )
(6.11)
From equations (6.10) and (6.11), it is apparent that in the PLL

loop, there are five different element variations that need to be
corrected for, N divider variations, VCO gain variations, CP current
reference variations, and RC process variations.
N divider variations have been taken care of in section 6.3. The
VCO gain is designed to be within a well-determined window that can
meet the specified performance criteria at nominal and hence will not
be calibrated directly. Hence, the CP current are the only elements of
the loop that will be calibrated. The slew rate, I/C, and RC can be
independently calibrated against the reference clock. Therefore, we do
not need to program the capacitance, C, and only need to calibrate the
CP current and the resistor R to account for all five PLL loop elements
variations.
Rearranging equations (6.10) and (6.11), gives:
Aol
I CP .K VCO .(1 ' Icp ).(1 ' Kvco )

N nom .Cnom .(1 ' N ).(1 'C )
(6.12)
and,
RC
Rnom Cnom .(1 ' R ).(1 ' C )
(6.13)
The calibration can be thought of as correction factors that null

out the deviations from the various sources of error, setting the loop
gain and the RC time constant to their desired, nominal values.
Hence, the final open loop gain can be expressed as:
Aol
fI
f I .I CP .K VCO .(1 ' Icp ).(1 ' Kvco )

N nom .Cnom .(1 ' N ).(1 ' C )
I CP .K VCO
,
N nom.Cnom
(1 ' N ).(1 ' C )

(1 ' Icp ).(1 ' Kvco )
119
(6.14)
and the time constant,

RC
f R .Rnom Cnom .(1 ' R ).(1 ' C ), f R
1
(1 ' R ).(1 ' C )
(6.15)
fR and fI are the correction factors.

Looking at the above equations, we can see that the CP current
need to adjust for three sources of errors in the loop. In addition to the
divider, N, variations that have already been addressed in the adaptive
part of the CP, the Icp correction factor, fI, need to compensate for the
VCO gain and I/C ratio. Hence,
fI
f IN . f IKvco . f IIC
(6.16)
Since N variations have been taken care of, equation (6.16) can be
written as:
fI
1 'I
(1 ' Kvco ).(
)
1 'C
(6.17)
These adjustments will be determined by calibrations for I/C and KVCO.

I/C calibration can be done in conjunction of RC calibration.
6.5
PROCESS CALIBRATION I/C SLEW RATE

AND RC TIME CONSTANT
The CP current is derived from a well-defined bandgap reference

voltage, VBG and a reference resistor R, Figure 6-5. The reference
current is derived as:
120
Chapter 6
Figure 6-5. Reference Current Generation from Bandgap
VBG
R
I ref
(6.18)
Using the same reference current and using a counter clocked by

the crystal reference clock used in the PLL, we can charge a capacitor,
C and note the time variations, 'T, from nominal corresponds to the
RC and I/C variations, and hence the capacitor, C, in the loop can be
adjusted to compensate for those variations based on the counter word
output. Hence,
I ref .R
T
VBG
T
I ref
C
(6.19)
Therefore,
T
and,
RC
(6.20)
VBG
T
I
C
121
(6.21)
From the above equations, it is apparent that as long as the bandgap

voltage reference is accurate and that all the used resistor and
capacitors have a good matching and of the same type, the calibration
will be accurate.
6.6
VCO TUNING GAIN CALIBRATION
The VCO tuning gain (KVCO) differentiates the sensitivity of the VCO
output frequency (FVCO) to changes in its tuning voltage (Vtune). It is
defined as:
K VCO
dFvco
dVtune
(6.22)
The tuning gain is not constant, as illustrated in the plots of VCO

frequency and tuning gain versus tuning voltage (Figure 5-21 and 5-22).
It is apparent that the VCO gain changes across the tuning voltage
curve. Instead of compensating the VCO directly, the loop gain of the
PLL can be compensated by adjusting another gain term of the CP
current to cancel out the variations in the KVCO tuning gain. The
compensation requires a method of measuring the tuning gain, and
hence an algorithm can be derived and applied appropriately for the
KVCO tuning gain adjustment.
6.6.1
VCO Calibration Algorithm Description
The used tuning gain calibration system approximates the tuning gain
by measuring the difference in tuning voltage for a predetermined
difference in VCO frequency. This approximates the tuning gain with
finite number differences:
K VCO
dFvco
( F2 F1 )
#
dVtune (Vtune2 Vtune1 )
'F
'Vtune
(6.23)
122
Chapter 6
The calibration algorithm works such that it locks the PLL

synthesizer to a slightly different frequency close to the final required
frequency and the tuning voltage is recorded. It then locks to the
actual frequency of interest recording the final tuning voltage. A
difference in the measured tuning voltage is then calculated and hence
the ratio of the difference of the measured tuning voltage 'Vtune to the
nominal difference 'Vtune_nom equates to the ratio of the nominal
tuning KVCO called KVCO_nom to the measured tuning KVCO, as
illustrated in the following equations.
K vco_nom
'F
'Vtune_nom
(6.24)
and
K vco
'F
'Vtune
(6.25)
Hence,
K vco
K vco_nom
'Vtune_nom
(6.26)
'Vtune
Using an analog-to-digital converter (ADC) as illustrated in Figure

6-2, the ratio in equation (6.26) is expressed in binary word format:
'Vtune
Vtune2 Vtune1 'ADBits
ADBits2 ADBits1
(6.27)
where ADBits represents the binary output word of the ADC and the
'ADBits is the binary difference of final and first ADC readings.
For the nominal tuning gain, there is a nominal difference in ADC
output values, 'ADBitsnom. The ratio of the measured to the nominal
ADC value is then equal to the ratio of the nominal to the measured
tuning gain.
K vco_nom
K vco
'Vtune
'Vtune_nom
'ADBits
'ADBitsnom
(6.28)
123
Introducing the above ratio to the loop gain of equation (6.14), it

can be used to adjust the CP current and hence null out the VCO gain
variations with respect to the golden design value:
Aol
I cp K vco
NC
'ADBits
I cpnom
K vco
'ADBitsnom
NC
(6.29)
After calibrating the loop, the effect of the loop gain Aol on the
loop should be the same as the golden nominal loop gain Aolnom. This
can be verified by examining the loop gains ratio, equation (6.30):
Aol
Aolnom
I cp .K vco
N .C
N .C
I cp_nom .K vco_nom
'ADBits
I cp_nom .
.K vco
'ADBitsnom
I cp o K v o
K vco_nom
I cp_nom .
.K vco
K vco
I cp_nom .K vco_nom
(6.30)
I cp_nom .K vco_nom
I cp_nom .K vco_nom
1
The CP mirror ratio is implemented as shown in Figure 6-6. The

mirror devices are binary weighted and hence can be driven directly
by the ADC word, 'ADBits. The nominal CP current corresponding
to the nominal VCO gain and hence nominal loop gain is designed
into the input current mirror.
124
Chapter 6
$<1>
$<0>
$<n-1>
2n

To CP
switch
Icp_nom
Icpp
Figure 6-6. CP Mirror Ratios

VDD
$<0>
$nom
$<n-1>
$<n-1>
$<0>
Vbp
Vbp
2n

Icp_nom
UP
VDD
DN
Charge
Pump
Switches
Icp_nom
Iref
$<0>
Vbn
$<0>

Vbn
$<n-1> 2
$<n-1>
$nom
VSS
Figure 6-7. Charge Pump Employing Mirroring as in Figure 6-6 for VCO Gain Calibration
Figure 6-7 shows the CP circuit employing the mirror ratio. The
CP comprises a typical current reference cell, with the first current
branches mirrors weighted according to the expected 'ADBitsnom
125
(denoted ' nom in the figure), and the output mirrors binary weighted,
and switched according to the measured 'ADBits (denoted '<> for
simplicity).
6.6.1.1 'N Values
The ' N values are chosen based on the nominal VCO gain KVCO_nom
and the nominal ADC output, 'ADBitsnom. Based on the ADC size
and the nominal KVCO, the nominal tuning voltage, 'Vtune_nom is
determined by:
'Vtune_nom
'ADBitsnom .VDD
2n
(6.31)
VDD is the supply voltage and n is the number of bits of the ADC
used in the algorithm. The nominal VCO frequency change is
determined by 'Fnom:
'Fnom
'Vtune_nom .K VCO_nom
(6.32)
'N is the change in N value which is related to the change in

frequency, 'F, and hence is:
'N
'Fo
Fref
(6.33)
Fref is the PLL synthesizer sampling frequency. Equation (6.33) can be

rewritten as shown in equation (6.34).
'N
'ADBitsnom .VDD.K vco

2n Fref
(6.34)
6.6.1.2 Summary of Tuning Algorithm Operation
To summarize the operation of the PLL synthesizer VCO gain calibration system, the calibration algorithm is outlined as follows:
x The channel frequency is set and hence determines the final divider
value, N.
x A 'N value is then chosen based on the ADC size and the nominal
VCO gain that is determined by design.
126
Chapter 6
x The divider is then programmed to (N'N) value and the

synthesizer is given time Tlock which is set by allowing a counter
clocked by the reference clock within the algorithm implementation
to count down from it to zero indicating PLL lock.
x Once the counter reaches zero after Tlock, the value of the tuning
voltage (Vtune) is read by the ADC and registered in regiser-1.
x The synthesizer is then programmed to lock to the final frequency,
N*fref. After Tlock, Vtune is similarly read by the ADC and the value
is stored in register-2.
x The algorithm calculates the difference between register-2 and
register-1 giving 'ADBits which then program the CP current
accordingly to null out the VCO gain variations.
Figure 6-8. Half-Band Tuning Shown in Terms of third Band from the Bottom
6.7
127
IMPROVED VCO BAND SWITCHING
Here we describe a technique to improve the VCO band switching

used in chapter 5. An additional bit is added to the 8-bit VCO tuning
to control half-band tuning. In other words, once lock has been
achieved with the coarse tuning using of eight bands, an additional
half band is switched on to further enhance the phase noise performance of the synthesizer. This is illustrated in Figure 6-8. The half
band in red can be switched between any two full bands by switching
additional half-unit capacitance. This can be regarded as fine tuning to
reduce the tuning window and hence allow for an efficacy in CP
linearization used as we employ the synthesizer across bands.
6.8
EXPERIMENTAL RESULTS
The design, implementation, and measurement of the proposed

multiband fractional-N PLL synthesizer using an RFCMOS technology
have been undertaken. The complete synthesizer architecture has been
Figure 6-9. Phase Noise for the Enhanced Fractional-N PLL @ 2.4 GHz, Spurs are Shown
Transposed on Phase Noise Curve
128
Chapter 6
built for performance and to establish structure viability. Figure 6-9

shows the measured phase noise performance for the WLAN standard
at 2.4 GHz band. The measured phase noise curve has two parts: phase
noise curve and spurious transposed on the phase noise curve. The
result shows an improvement when the NSCP, VCO calibration, and
improved VCO band switching are employed.
6.9
COMPARISON WITH PUBLISHED RESULTS
A summary of the achieved results obtained by measuring the fractional-N synthesizer is shown in the Table 6-1.
Table 6-1. Comparison with other Work
Ref.
Process
(CMOS)
PLL
Type
Freq.
(GHz)
PFD
Freq.
(MHz)
Loop
BW
(KHz)
[9]
[10]
[11]
This
work
0.24
0.25
0.25
0.18
Integer
5
5
5
2.45
11
280
8
40
250
280
6.10
Integer
Fractional
L (f) @
offset
(d Bc / Hz
@ 1 MHz)
101
112
112
119
Power
Usage
(mW)
Supply
Voltage
(V)
25
180
40
3
2.5
1.8
CONCLUSION
We have presented a novel frequency synthesizer structure based on

noise-shaped fractional-N PLL employing a '6-controlled adaptive CP.
Extensive calibration techniques were employed through out the PLL.
Measurement results obtained from testing the new architecture
showed enhancement in the noise performance by 10 dB. This noise
improvement was translated into a reduction in the synthesizer locking
time since wider loop filter BW is used. The above improvements
come at a price of increased complexity, current consumption, and
chip area.
REFERENCES
[1] T. Riley, M. Copeland, and T. Kwasniewski, Delta-Sigma Modulation
in Fractional-N Frequency Synthesis, IEEE Journal of Solid-State
Circuits, 28, pp. 553559, May 1993.
129
[2] P.T. Kenny, T. Riley, N. Filiol, and M. Copeland, Design and

Realization of a Digital DeltaSigma Modulator for Fractional-N
Frequency Synthesis, IEEE Transactions on Vehicular Technology,
48, pp. 510521, Mar. 1999.
[3] B. Miller and R. Conley, A Multiple Modulator Fractional Divider,
IEEE Transactions on Instrumentation and Measurements, 40, pp.
578582, June 1991.
[4] M. Kozak, I. Kale, A. Borjak, and T. Bourdi, A Pipelined All-digital
[5] W. Rhee, B. Song, and A. Ali, A 1.1-GHz CMOS Fractional-N
Frequency Synthesizer with a 3-b Third-Order DS Modulator, IEEE
Journal of Solid-State Circuits, 35 (10), Oct. 2000.
[6] T. Bourdi, A. Borjak, and I. Kale, Agile Multi-Band Delta Sigma
Frequency Synthesizer Architecture, Proceedings of ISCAS 2002, pp.
413416.
[7] T. Bourdi, A. Borjak, and I. Kale, A Delta Sigma Frequency
Synthesizer with Enhanced Phase Noise Performance, Proceedings of
IMTC 2002, pp. 247251.
[8] J. Vandenbussche, et al., Systematic Design of High-Accuracy CurrentSteering D/A Converter Macrocells for Integrated VLSI Systems, IEEE
Transactions on Circuits and Systems II, 48 (3), Mar. 2001.
[9] H.R. Rategh, H. Samavati, and T.H. Lee, A CMOS Frequency
Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz
Wireless LAN Receiver, IEEE Journal on Solid-state Circuits, 35 (5),
May 2000.
[10] T.-P. Liu and E. Westerwick, 2- 5-GHz CMOS Radio Transceiver
Front-End Chipset, IEEE Journal of Solid States Circuits, 35 (12), Dec.
2000.
[11] M. Zargari, D.K. Su, C.P. Yue, S. Rabii, D. Weber, B.J. Kaczynski, S.
Mehta, K. Singh, S. Mendis, and B.A. Wooley, A 5-GHz CMOS
Transceiver for IEEE 802.11a Wireless LAN Systems, ISSCC Digest
of Technical Papers, Feb. 2002.
Chapter 7
CONCLUSION AND FURTHER WORK
7.1
CONCLUSION
The work presented in this monograph focused on an enhanced design

and implementation of low phase noise frequency synthesizers as
local oscillators in transceivers for multimode WLAN applications
covering all 802.11a, b, and g standards.
Brief descriptions of those standards were discussed in terms of
frequency bands for the radio frequency transmission. A suitable
transceiver operating in all WLAN modes was described along with
its transmitter/receiver chains. Architecture for the frequency synthesizer
acting as local oscillator for the transceiver was proposed and
employed in this book. Direct frequency synthesis was not used to
avoid frequency pulling in the transceiver [1].
Detailed analyses of integer and fractional-N phase-locked loop
frequency synthesizers were treated. Open-loop and closed-loop
transfer functions of the phase-locked loop were derived. Noise
contributions of individual subblocks of the synthesizers were detailed.
Loop filter design is also included. The thorough analyses, derived
equations, and simulation results obtained from the undertaken
research formed the basis for an optimum design and implementation
of the implemented frequency synthesizer chips described in this book.
Unconditionally stable '6 modulators of the third-order (namely
MASH-1-1-1) were studied and employed in the analyzed phaselocked loop fractional-N synthesizer providing a good average
estimate for fractional-N dividers. Using a deep submicron 0.18 Pm
CMOS process with a supply voltage of 1.8 V, a '6-based
131
132
Chapter 7
fractional-N synthesizer was designed, simulated, laid out, fabricated,

and tested. The obtained phase noise performance was superior to all
WLAN synthesizers in the literature [24].
Novel circuit techniques and advanced design ideas were also
proposed and incorporated in the design, enhancing the overall
performance of the synthesizer. Those additions included adaptive CP
architecture to maintain loop gain and phase transfer functions while
operating in fractional mode; adaptive band switching control to
maintain frequency agility while offering optimum phase noise
performance in the band of interest was also incorporated and tested.
One of the main demonstrations and achievement of the work inhand is the development of the behavioral synthesizer platform using
the existing Cadence tools. The platform has been used in the accurate
simulations and predictions of all observed anomalies associated with
fractional-N '6-based frequency synthesizers. The author did not
leave anything to chance by rigorously analyzing the synthesizer
performance before and after different fixes and remedies have been
applied. Issues like dead-zone, close-to-integer operation, and CP
mismatch nonlinearity to name but a few have been observed as they
affect the synthesized VCO frequency. Various techniques have been
developed to mitigate these anomalies. Techniques such as operating
in well simulated and determined linear region of the PFD/CP to
mitigate the quantization noise folding phenomenon has been
developed. Additionally, methods of '6 dithering with the right
amount to completely reduce the fractional spurs to levels acceptable
by the system specifications have been proven. Last but not least, the
viability to optimize the loop BW on the fly in a closed loop PLL in
the presence of all noise sources and nonlinear effects made the design
much more predictable. Once all the tools and methods have been
developed, the results have been demonstrated in the design and
implementation of an ultra low noise synthesizer system for
deployment in the WLAN standards. The developed techniques can be
used in any synthesizer development and design with an emphasis on
fractional-N '6-based systems.
7.2
FURTHER WORK
Although the work presented in this book formed a major contribution

to the superior implementation of frequency synthesizers acting as
local oscillator in WLAN transceivers, a few concept ideas could be
133
Conclusion and Further Work
identified to form major future research work for the implementation

of low phase noise frequency synthesizers. These are as follows:
1. The use of the developed techniques to study the feasibility of a
totally calibrated and digitally controlled frequency synthesizer
that can form the basis of an all digital transmission system. Such
system can make use of DSP functions to solve some of the system
anomalies that are usually difficult to fix using analog techniques.
2. Direct modulation frequency synthesizer to reduce nonlinear
analog component count like mixers and analog modulators. In
addition to a power amplifier, such synthesizers form the basis of
ultralow power transmitters. '6-based direct modulation transmitters
can take the in-phase and quadrature base-band data and modulate
it using the '6 modulator then upconvert directly using the VCO
to drive the power amplifier. The main difficulty in such work will
be the wide range of bandwidths used by different systems. The
loop BW needs to be at least as wide as the transmitted data
bandwidth. Hence, issues like quantization noise will be significant
unless the '6 modulator is sampled at much higher frequency
than the loop BW.
An all digitally controlled '6-based frequency synthesizer capable
of data modulation will have many benefits over its traditional
counterparts. Since all signals are digital, the use of known signal
processing techniques to alleviate most of the anomalies and issues
normally present in a PLL system will be much easier. The fixes will
be much more robust and predictable in the digital domain. An
example of such a system is shown in Figure 7-1.
Data
Data
Ref.
TDC
m-bits +
-
error
n-bits Filter
C-bits
Synthesized
Freq
NCO
TDC
Time to digital
Converter
Figure 7-1. An all Digital Frequency Synthesizer Example
134
Chapter 7
The proposed system of Figure 7-1 can either use a frequency to

digital converter (FDC), or a time to digital converter TDC [5], to
convert the reference signal to a digital word that will be used for
comparison with the feedback data coming from an NCO. The data
representing the resulting comparison error can be processed using a
'6 modulator acting as a digital filter before it is passed on to
control the NCO. Data modulation can be applied to either the '6
modulator or directly to the NCO.
REFERENCES
[1] J.A. Weldon, et al., A 1.75 GHz Highly-integrated Narrow-band CMOS
Transmitter with Harmonic-rejection Mixers, IEEE Solid-State Circuits
Conference, 2001. Digest of Technical Papers, 2001 IEEE International
57 Feb. 2001, pp. 160161, 442.
[2] H.R. Rategh, H. Samavati, and T.H. Lee, A CMOS Frequency
Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz
Wireless LAN Receiver, IEEE Journal on Solid-State Circuits, 35 (5),
May 2000.
[3] T.-P. Liu and E. Westerwick, 2- 5-GHz CMOS Radio Transceiver
Front-End Chipset, IEEE Journal Solid States Circuits, 35 (12), Dec. 2000.
[4] M. Zargari, D.K. Su, C.P. Yue, S. Rabii, D. Weber, B.J. Kaczynski,
S. Mehta, K. Singh, S. Mendis, and B.A. Wooley, A 5-GHz CMOS
Transceiver for IEEE 802.11a Wireless LAN Systems, ISSCC Digest of
Technical Papers, Feb. 2002.
[5] A. Mantyneemi, An Integrated CMOS High Precision Time-To-Digital
Converter Based on Stabilised Three-Stage Delay Line Interpolation,
Academic Dissertation, Faculty of Technology, University of Oulu, Dec. 3,
2004.
Appendix A
PHASE-FREQUENCY DETECTORS
AND CHARGE PUMPS
PHASE-FREQUENCY DETECTORS
The typical PFD employed in frequency synthesizers is shown in

Figure A-1. IN1 and IN2 are the input signals to the PFD and they
conventionally represent the reference and feedback signals in the
PLL, respectively. The state diagram of the PFD of Figure A-1 is
shown in Figure A-2. Three states can be distinguished. Those are
denoted state 1, state 0, and state +1. The state diagram can be further
illustrated with the aid of a timing diagram.
IN1
'1'
UP
Q
Q
RESET
IN2
'1'
D
R
DN
Figure A-1. Phase-Frequency Detector Block Diagram
135
136
Appendix A
Three cases can be distinguished. The first case is when IN2 is

leading IN1. In this case, the UP goes high with the rising edge of IN1
and is reset to low with the rising edge of IN2. The DN goes high with
the rising edge of IN2 and resets instantaneously. The second case
IN2 is lagging IN1. In this case, the DN goes high with the rising edge
of IN2 and is reset to low with the rising edge of IN1. The UP goes
high with the rising edge of IN1 and resets instantaneously. The third
case is when IN2 tracks IN1, while the phase-locked loop is locked.
All the three cases are illustrated in Figures A-3A-5.
Figure A-2. State Diagram of the PFD in Figure A-1
Phase-Frequency Detectors and Charge Pumps

IN1
IN2
DN
UP
RESET
Figure A-3. Timing Diagram of the PFD, Case IN2 Leads IN1
IN2
IN1
UP
DN
RESET
Figure A-4. Case IN2 Lags IN1
IN2
IN1
UP
DN
RESET
Figure A-5. Case IN2 Tracks IN1
137
138
Appendix A
In practice, the UP and DN signals do not reset to low instantaneously but go to zero after a certain delay. This is illustrated in Figure
A-6 for the case of Figure A-3.
IN1
IN2
UP
DN
RESET
Delay in Reset Path
Figure A-6. Practical Timing Diagram of the PFD for IN2 Leading IN1. The Figure is not to Scale
as in Reality the RESET Pulse is a Full Pulse and not an Impulse as the Figure might Suggest
One important disadvantage of the PFD described above is the dead

zone. Dead zone occurs when IN1 and IN2 are very close and there is
not enough delay in the reset path. This causes the UP and DN pulses
not to fully turn ON and stay ON for a short time to allow for the CP
switches to respond. Too much delay in the reset path, however, can
adversely cause additional increase of phase noise due to the inherently
noisy current sources that are ON for a longer time.
CHARGE PUMP
A behavioral model for a CP is shown in Figure A-7. The CP UP

current source sources current into the loop filter whereas the loop
filter sinks currents into the DN CP current source. The effect of
sourcing and sinking the CP current is also illustrated in Figure A-7.
139

Vsup
Vsup
Vsup
Iup
Iup
Iup
Up
Up
Up
Icp
Icp
Icp
Dn
Dn
Dn
Zs
Zs
Zs
Idn
Idn
Idn
Figure A-7. Charge Pump Sourcing and Sinking Illustration
Vdd
Vdd
UP
vp
vp
UP
V dd
V dd
Icp
vn
Vss
Icp
DN
Vss
vn
DN
(a)
(b)
Figure A-8. Single-Ended Charge Pump and its Modification
A conventional single-ended CP circuit is shown in Figure A-8a.

Figure A-8b shows a modification of the CP circuit to isolate the
feed-through obtained by the switches UP and DN pulses as the
current sources act as buffers for the switches.
140
Appendix A
There are few issues that need to be considered when designing a

CP. These are as follows:
x
x
x
x
Output impedance of CP
Current mismatch between UP and DN parts
Switching time and switch feed-forward
Leakage when UP and DN are off (CP Icp = 0)
Example charge pump UP, DN, and net currents are shown in
Figure A-9. It can easily be seen from the net current that there is a
mismatch between the UP and DN currents for tuning voltage values
less than 0.3 V and greater than 1.2 V.
Figure A-9. Example DC Current Curves of the Charge Pump
PFD/CP CHARACTERISTICS
The combined PFD/CP performance is of particular interest. The

characteristic curve is important because it can be used in system
simulation to predict the PLL behavior in presence of the PFD/CP
nonlinearity.
Figures A-10 and A-11 show the PFD/CP characteristics and the
gain slope variations. Figure A-10 is very useful as it shows the areas
where the CP gain has most of the variations for a specific PFD/CP
architecture. The more variations in the gain the more susceptible the
PLL loop will be to nonlinearities and noise folding. The average
current here is the total charge multiplied by the reference frequency
(40 MHz), i.e. the measured charge over the sampling period.
Figure A-10. PFD/CP Characteristic
Figure A-11. PFD/CP Gain Slope Variations
141
Appendix B
CONTROLLED OSCILLATORS
REFERENCE OSCILLATORS
Wireless frequency synthesizers have very stringent phase noise

requirements. Working those requirements backwards to the various
blocks of the PLL, the first block that determines the initial purity of the
system is the reference oscillator. The main contributors to the phase
noise plateau of the PLL are the reference oscillator, the PFD and the
dividers. A low phase noise plateau warrants the usage of a clean and
very stable reference oscillator.
1.1
VCXOs are the most accurate, clean, and stable frequency sources
that are used as frequency references in the PLL. The crystal is made
of a piezoelectric resonator that is electromechanical in nature. Figure
B-1 shows a basic crystal model and a configuration that forms the
basis of a VCXO.
The motional capacitance Cs and the motional inductance Ls determine the series resonance of the crystal equation (B.1) as their
impedances cancel out. The crystal impedance at the series resonance is
approximated to Rs, the motional resistance. This resonant frequency is
the operation frequency.
143
144
Appendix B
Ls
Rs
Cs
Cp
(a)
(b)
Figure B-1. Crystal Oscillator (a) Equivalent Circuit, (b) Simplified VCXO Circuit
Implementation
fs
1
2 LsCs
(B.1)
Another crystal resonant frequency is achieved when the parallel

capacitance becomes significant. This happens when the inductance
Controlled Oscillators
145
impedance becomes much larger than the capacitance impedance and

dominates. The magnitude of the inductive impedance becomes equal
to the magnitude of the parallel capacitive impedance, Cp, and cancels
out at a parallel resonance frequency equation (B.2).
fp
1 Cp Cs
'f
2S LsCpCs
(B.2)
where 'f is the shift in frequency from series to parallel resonance

and is determined by the load capacitance, CL, of the VCXO circuit
configuration. This shift in frequency is given by:
'f
1.2
Cs
2(CL Cp )
(B.3)
Temperature-Compensated Crystal Oscillator
VCXOs have a superior phase noise characteristic and hence are very
suitable for PLL synthesizers with stringent phase noise requirements.
However, crystal oscillators exhibit a fundamental drift in frequency
with temperature. Equation B.4 [B1] shows frequency drifts due to
ambient temperature variations of an AT-cut1 crystal.
'f
[D1 (T T0 ) D 2 (T T0 ) 2 D 3 (T T0 )3 ] f 0
(B.4)
where f 0 is the nominal resonant frequency at T0 25o C ambient

room temperature, D1 , D 2 and D 3 are constants that depend on the
physical properties of the crystal and its angle of cut, and T is the
ambient temperature.
For highly accurate applications, a temperature-compensated crystal
oscillator (TCXO) can be built where by the crystal temperature is kept
constant. Compensation is achieved using temperature-dependent circuit elements such as thermistors and negative temperature coefficient
(NTC) capacitors. Figure B-2 shows a typical circuit implementation
of a TCXO using a colpitts oscillator topology [B2].
146
Appendix B
VCC VDD
R b1 Rg1
M1 M1
Re2
Crystal
Crystal
Cc
RT
RT
CNPO1CNPO1CNPO2CNPO2CNPO3CNPO3
R b2 Rg2 C
1
C2
C1
C2
Cc
Output
M2
Output
R e1 RS
Figure B-2. TCXO Circuit
VOLTAGE-CONTROLLED OSCILLATORS
VCO are the heart of PLL frequency synthesizers. The stringent

requirement on their spectral purity requires very good design
practices and guidelines. Improving phase noise and jitter requires,
however, the exploring of new techniques such as the ones cited in
[B3B6]. To design the VCOs with low noise performance, proper
noise analysis have is required as presented in the next paragraphs.
2.1
Voltage-Controlled Oscillators: Phase Noise Analysis
Equation B5 shows the SSB power spectral density (PSD) of the total
phase noise.
P
(Z 'Z ,1Hz )
Ltotal {'Z} 10 log sideband 0
(dBc/Hz)
Pcarrier
(B.5)
147
where Psideband(Z0 + 'Z, 1 Hz) represents the SSB power at a

frequency offset of 'Z from the carrier over 1 Hz bandwidth. For LC
tank oscillators, Leesons equation, B6, models the phase noise based
on a linear time invariant (LTI) system.
2 FkT
L('Z ) 10.log
P
sig
L('Z)
(dB)
Z 2 'Z1/ f 3
0
1
1
Z
2
Q
'
'Z

(B.6)
1/f3
1/f2
1/f1
'Z1
f3
1/f0
'Z
Figure B-3. Typical Curve of the Phase Noise of an Oscillator Versus Offset from Carrier
F is called the device excess noise number, k is Boltzmans

constant, T is the absolute temperature, Psig is the average power
dissipated in the lossy resistive part of the tank, Z 0 is the oscillation
frequency, Q is the loaded quality factor of the tank, 'Z is the offset
from the carrier and 'Z1/f 3 is the frequency of the corner between 1/f 3
and 1/f 2 region (as shown in Figure B-3). This equation, however,
makes use of F and 'Z1/f 3 that are fitting factors and cannot be
calculated beforehand.
Using LTI method [B5] treats oscillator as a feedback system and
considers each source noise as an input X( jZ) (Figure B-4). The phase
noise at the output, Y( jZ), is made of the noise contributions of
various elements in the circuit and the noise shaped by the feedback,
equation (B.7).
148
Appendix B
X(jZ) +
H(jZ)
Y(jZ)
Figure B-4. Oscillator as a Linear System
Y
> j(Z0 'Z )@
X
1
dH
('Z )
dZ
(B.7)
B7 can be used to get the output noise PSD. This approach,

however, is based on linear analysis and cannot be used to predict
realistic phase noise of real VCOs.
Linear time variant (LTV) method used in [B6], however, is more
useful for predicting and optimizing phase noise in oscillators. This
analysis makes use of a special function, ISF that describes how much
phase shift results from applying a unit impulse at any point in time.
Equation (B.8) shows the phase shift due to applying a unit impulse.
h) (t ,W )
*(Z0t )
u (t W )
qmax
(B.8)
where *(Z0t) is the ISF function of the output and qmax is the
maximum charge offset across the capacitor. The total excess phase
due to a noise current can be described by the following equation:
t
f
T (t )
f
h) (t ,L )i (L )dL
*(Z0L )
i (L )dL
qmax
f
(B.9)
The phase can hence be converted to voltage to get the SSBPSD,

equation (B.10).
149
in2 f 2
cn
'f
n 0
L{'Z } 10 log 2
2
8q max 'Z
(B.10)
in2
is the power spectral density of the input noise current, cn
'f
is the coefficient of the Fourier transform of the ISF function, and 'Z
is the frequency shift from the carrier frequency.
where,
2.2
VCO Design Methodology
Figure B-5 shows the steady state parallel LC oscillator model. The
tank loss is represented by gtank, and the effective negative conductance
of the active devices, required to compensate for the tank losses is
represented by gacitve.
Typically, LC oscillators operate in two different modes: namely
current- and voltage-limited modes [B7]. In the current-limited mode,
the tank amplitude, Vtank, linearly increases with the bias current
according to Vtank = Ibias/gtank until the oscillator enters the voltagelimited mode where the amplitude is limited to Vlimit, which is
determined by the supply voltage. Vtank can be expressed in Equation
(B.11) where Ibias is the independent variable.
Figure B-5. Steady State parallel LC oscillator model
150
Appendix B
Vtank
I bias
g tank
V
limit
( I Limited )
(B.11)
(V Limited )
Using the tank inductance, L, as the independent variable, we can

express equation Vtank in equation B.12 as:
2
Vtank
2 Etank
C
2 EtankZ02 L
(B.12)
where Etank is the tank energy defined in equation B.13 as:
Etank
2
CVtank
2
(B.13)
and, Z 0 1 / LC is the oscillation frequency. The tank amplitude

grows with L for a given Etank and Z0. This is referred to as
inductance-limited mode where the inductance is limited by the given
size or available area. The V limit is constrained by the supply
voltage; hence Vtank can be expressed as:
2
Vtank
2.2.1
2E tankZ02 L
2
Vlimit
(L Limited)
(V Limited)
(B.14)
VCO Design
Figure B-6 shows the building block of the used LC VCO core. In
addition to the inductor dimensions, Figure B-7, the core can be
optimized by optimizing the MOS W/L dimensions, the varactor
tuning range, and the bias current.
Using the parallel oscillator model on the Figure B-7, the tank loss
gtank, the negative conductance -gactive, the tank inductance Ltank, and
the capacitance Ctank are given by:
151
2 g tank
2 g active
Ltank
2Ctank
g op g v g L
(B.15)
(B.16)
g mp
(B.17)
2L
CPMOS CL Cv C load
(B.18)
where g L and gv are the effective parallel conductance of the

inductors and varactors, respectively.
Figure B-6. VCO Core Schematic
152
Appendix B
Figure B-7. Equivalent Oscillator Model and Symmetrical Spiral Inductor Model
The primary parameter in the oscillator specifications requiring

optimization is the phase noise. This is followed by the power
consumption, frequency tuning range, start-up conditions, tank
amplitude, and diameter of spiral inductor.
Derived from the system power budget, the maximum power
constraint is imposed in the form of maximum bias current Imax drawn
from a given supply voltage, i.e.
(B.19)
I bias d I max
The tank amplitude is required to be large, Vtank,min is to provide a

large enough voltage swing to drive the next stage:
Vtank
I bias
g tank,max
t Vtank,min
(B.20)
The tuning range of the oscillation frequency needs to be

maximized for greater frequency coverage, hence:
L tank Ctank, min d
1
2
Zmax
, Max. tuning frequency
(B.21)
153
L tank Ctank, max t
1
2
Zmin
, Min. tuning frequency
(B.22)
To guarantee a reasonable start-up condition with a small-signal

loop gain of at least Dmin, the worst case condition can be expressed in
equation (B.23), where gtank,max guarantees start-up in the worst case,
hence:
g active t D min g tank,max
(B.23)
The final spec. is size or area which needs to be kept small. Being
the most area-consuming component in the VCO core, the inductor
has its size specified so as not to exceed a certain value and hence its
diameter is specified as dmax, i.e.
(B.24)
d d d max
For a given chip area or specified dmax, the inductance, L, is also

constrained and so is the tank amplitude as shown earlier in equation
(B.14).
2.2.2
Phase Noise Optimization
Using the LTV method of analysis, phase noise is given by:
L ^ f off `
in2
1
1
2
rms,n
2
8S 2 f off2 qmax
n 'f
(B.25)
in2
'f
represents the equivalent differential noise PSD due to drain current
noise, inductor noise, and varactor noise, expressed as:
where foff is the offset frequency from the carrier frequency.
i M2 ,d
'f
2 kTJ ( g d 0 ,n g d 0 , p )
(B.26)
154
Appendix B
2
iind
'f
2kTg L
(B.27)
2
ivar
'f
2kTg v,max
(B.28)
where J is approximately
2
3
and
5
2
for long- and short-channel
transistors, respectively. It has been proven [B8] that drain current noise
is predominantly amongst the three noise sources. Taking only the drain
current noise term into consideration in B.25, and replacing qmax by
Vtank
2 I drain
, and g d0
for short-channel transistors, (* 2rms = 1/2
2
LtankZ
Lchannel Esat
is used for pure sinusoidal waveform), the phase noise can be expressed
as:
L2 g L2 / I bias
L{ f off } v 2
2
L I bias / Vsupply
(L Limited)
(V Limited)
(B.29)
B.29 states that for a given bias current, the phase noise rises with
increasing L in the voltage-limited mode, hence once the V-limit is
reached any excess in inductance, L, will worsen the phase noise.
Additionally, for a given inductance, increasing the bias current
translates to an increase of the phase noise in the voltage-limited
mode, inducing power wastage. For a typical on-chip spiral inductor,
the minimum effective parallel conductance gL decreases with an
increasing inductance; the factor L2g2L also increases. Thus, for a
given Ibias, the phase noise increases with the inductance in the
inductance-limited mode and hence a smaller inductance results in a
better phase noise. So the design needs to be based on finding the
smallest inductor that satisfies both the tanks amplitude and start-up
condition for the maximum allowable bias current allowed by the
current budget.
155
Here is a summary of the described design methodology:

x Set the bias current to Imax, and pick an initial guess for inductance
value minimizing gL.
x Plot C versus W of the active device for the chosen inductance
x If there are more than one possible points on the graph, reduce the
inductance and replot until the possible region reduces to a single
point. That optimum point represents the optimum C and W,
corresponding to the optimum inductance yielding the optimum
phase noise. A summary of constraint and design optimization
methodology is given in Figure B-8 [B9].
Figure B-8. CW plane, Summary of Constraint and Design Optimization Methodology
REFERENCES
[B1] Frerking and E. Marvin, Crystal Oscillator Design and Temperature
Compensation, Van Nostrand, New York, 1978.
[B2] M.A. Haney, Design Technique for Analog Temperature Compensation of Crystal Oscillators, Master thesis, Faculty of the Virginia
Polytechnic Institute and State University, Blacksburg, VI, 2001.
156
Appendix B
[B3] T.C. Weigandt, B. Kim, and P.R. Gray, Analysis of Timing Jitter in
CMOS Ring Oscillators, Proceedings of ISCAS, June 1994.
[B4] J. McNeill, Jitter in Ring Oscillators, IEEE Journal of Solid-State
Circuits, 32, pp. 870879, June 1997.
[B5] B. Razavi, A Study of Phase Noise in CMOS oscillators, IEEE
Journal of Solid-State Circuit, 31, pp. 331343, Mar. 1996.
[B6] A. Hajimiri and T.H. Lee, A General Theory of Phase Noise in Electrical
Oscillators, IEEE Journal of Solid-State Circuits, 33, pp. 179194, Feb.
1998.
[B7] D.B. Leeson, A Simple Model of Feedback Oscillator Noises Spectrum, Proceedings on IEEE, 54, pp. 329330, Feb. 1966.
[B8] D. Ham and A. Hajimiri, Concepts and Methods in Optimization of
Integrated LC VCOs, IEEE Journal of Solid State Circuits, 36,
pp. 896909, June 2001.
[B9] F. Fang and K. Phang, Phase Noise Analysis of VCO and Design
Approach to LC VCOs, Term Paper University of Toronto, pp. 314,
2001.
Appendix C
PHASE NOISE
Analysis
CALCULATION OF GLOBAL PHASE ERROR

FROM L(f )
A signal s(t) having a peak amplitude A, a radian frequency Zc, and a

periodic phase modulation with peak amplitude 'Ipk and radian
frequency Z m is given by:
s (t )
(C.1)
A cos(Zct 'Ipk sin Zm t )
Using trigonometric identities,
s (t )
A cos(Zct ) cos('Ipk sin Zmt ) A sin(Zct ) sin('Ipk sin Zm t )

(C.2)
If the phase modulation index is small, 'Ipk << 1, then the second
cosine term approaches unity and the second sine term approaches its
argument.
s (t ) | A cos(Zct ) A'Ipk sin(Zc t) sin(Zm t )
A'Ipk
[cos(Zc Zm )t cos(Zc Zm )t ] ,
A cos(Zct )
2
157
(C.3)
158
Appendix C
which is a single carrier tone having two sideband tones with relative
amplitude ('Ipk/2), spaced by Z m from the carrier.
Note that the peak phase error is related to the amplitude and
power of the phase modulating signal. Similarly, the RMS phase error
is given by the RMS amplitude of the phase modulating signal,
'Irms
'Ipk
(C.4)
Single-sideband phase noise (SSBN) is a measure of the power in a

sideband region relative to the carrier power. The sideband noise ratio
(SBNR) is defined numerically for the sideband tone as:
SBNR
power in sideband
power in carrier
A'Ipk
2
A
2
'Ipk
2
'Irms
2
(C.5)
SSBN, expressed in dBc/Hz is the most common measure of phase

noise, describing the power in a 1-Hz bandwidth relative to the carrier
at an offset frequency f from the carrier. The script-L symbol is used.
'I 2 ( f )
L( f ) 10 log10 rms
(C.6)
where the variable ( f ) indicates the power is measured in a 1-Hz

bandwidth at an offset f Hz from the carrier. L( f ) is a convenient term
because it can be measured directly using a spectrum analyzer or
similar setup in the laboratory.
We can also calculate the total RMS phase error contribution for
phase noise in a span of frequencies offset from the carrier. In that
case the sideband noise power is integrated over the bandwidth of
interest.
'Irms
f2
f1
2
'Irms
( f )df
f2
2 10L(f ) /10 df
f1
(C.7)
This is the relationship between total, or global, RMS phase error

and the phase noise spectrum L( f ). The equation returns the RMS phase
error in radians.
159
Phase Noise
As an example, the GSM system requires a total global RMS phase

error of 5q degree symbol. To allow margin for other transmit path
impairments, we can arbitrarily set a specification of less than 2q for
the PLL and VCO. Using the above relationship, and assuming that
the in-band phase noise is constant and will dominate the result, we
find:
2
'Irms
L( f ) 10 log10
2 BW
(C.8)
where BW is the loop bandwidth. For a 150 kHz bandwidth and 2q

error, L( f ) must be less than 84 dBc/Hz in-band.
PHASE NOISE AND PHASE MODULATION
Random noise in the vicinity of a signal causes both amplitude and

phase noise modulation of that signal.
A single noise sideband (at any offset from the carrier), produces
both amplitude and phase modulation and can be represented
vectorially (Figure C-1).
B
A
Resultant
T
Figure C-1. Single Sideband and Carrier
The resultant vector changes in both amplitude and phase, the

amplitude varying from A B to A + B, with a modulation depth of
B/A multiplied by 100%. The phase varies by r ), where ) = B/A,
in radians, provided B is small compared to A.
160
Appendix C
B
B
A
T
Figure C-2. Carrier and Phase Modulating Sidebands
Two sidebands (Figure C-2), with equal initial phase, each in

quadrature with the carrier A, but at equal frequency offsets at either
side of it can be represented as positively rotating vectors, producing
only phase modulation. The peak phase variation is r2B/A. This is
representative of what occurs when we measure the noise of signals
where phase noise dominates, which is the usual case (the natural
limiting of the oscillator in a phase-locked loop restricts the amplitude
noise, but not the phase noise). The single-sideband power level is
thus 20log10 (B/A) dBc.
At a particular offset frequency, the sum vector is:
e(t ) A cos(Zct ) B cos(Zc Zm )t B cos(Zc Zm )t
(C.9)
If we assume that 2B/A << S/2, then we can arrive at a value for e(t),
representative of the phase modulation of this carrier at this particular
frequency offset, m:
e(t ) A cos(Zct 2AB sin(Zm t ))
where 2B/A sin(Z mt) is the phase modulation.
(C.10)
161
Phase Noise
RMS PHASE ERROR FROM PHASE NOISE
The output of a PLL is a sinusoid with phase noise. The ultimate goal
is to calculate from this phase noise spectrum the RMS phase error of
this sinusoid. First considering a pure sinusoid with white noise, such
as that associated with a resistor, in communications terminology
there is an associated signal-to-noise ratio, (S/N), and bandwidth.
Here C will be used to represent the carrier replacing S, the sinusoid,
in the commonly accepted 1 Hz bandwidth of SSB phase noise, L(f ).
If we look at a 1 Hz bandwidth of this noise power at an offset
frequency fm, from the carrier, and calculate the effect of this small
amount of noise, the effect of all the noise in the total bandwidth can
be found. The relationship between the vector and spectral representations of the carrier with noise is shown in Figure C-3;
Vc
C
N
fo + fm
fo
fo
Vn
fo + fm
Figure C-3. Single Sideband and Carrier

V2
where C, N are the powers c R , Vn R .

Calculation of the ratio of carrier to noise is as follows:
T pk tan 1 ( VV ) | VV , in power
n
N
C
(C.11)
The RMS phase deviation is:
T pk
2
N
2C
(C.12)
162
Appendix C
In the case of two sidebands at r fm with respect to fo, the

incoherent random phase noise contributions add in a sum of squares
fashion (Figure C-4).
C
Vc
Vn
T
fo
fo - fm
fo + fm
Figure C-4. Carrier and Phase-Modulating Sidebands
VnTotal
Thus T pk
Vn21 Vn22
2 Vn
Vc
2N
C
2Vn2
2 Vn
in RMSI
T pk
2
(C.13)
N
C
rad RMS
(C.14)
Before looking at the total noise in a given bandwidth, it is

important to note what kind of noise spectrum is being considered.
Superimposed noise vectors, from such things as amplifiers or thermal
noise sources, create both AM and FM sidebands. The diagrams
above considered this case. However, if the spectrum is phase noise
AM noise is insignificant (because of the self-limiting action of the
VCO), requiring the above equations to be altered from noise, N, to
phase noise N P. Since the noise power is split evenly into AM and
PM noise, N has twice the power of NP. Thus, the equations can be
altered with the relationship N 2 NP .
For white noise from amplifiers or resistors, the noise can be viewed
as many single sidebands and integrated over the required bandwidth.
Phase Error
1800
N
C
df
1800
N
b 2C
df
(C.15)
For the case of a phase noise spectrum:

Phase Error
1800
b
NP ( f )
C
df Deg RMS
(C.16)
163
Phase Noise
Thus, it is possible to integrate the normal SSB phase noise

spectrum, which expresses phase noise as a noise power at a particular
offset from the carrier, with respect to the total carrier noise power.
RESIDUAL FM
Residual FM is a measure of frequency instability related to SI( f ) (the

spectral density of phase fluctuations), expressing the total RMS
frequency deviation within a specified bandwidth. Commonly used
bandwidths are 50 Hz3 kHz, 300 Hz3 kHz and 20 Hz15 kHz. Only
the short-term frequency instability occurring at rates within the
bandwidth is indicated and no information regarding relative instability
rates is conveyed. The presence of large spurious signals at frequencies
near the carrier frequency can greatly exaggerate the measured level of
residual FM, since the spurious signals are detected as FM sidebands.
S 'f ( f )
2
'f rms
(f)
B
res FM
f 2 SI ( f )
S 'f ( f )
(C.17)
f 2 SI ( f )
B
[Hz]
(C.18)
To convert the quantity SI( f ) to L( f ) (SSBN), the following can be

used.
L( f ) =
Power density ( one phase modulation sideband) dBc/Hz

Hz
Carrier Power
(C.19)
L( f )
SI ( f )
2
(C.20)
L( f ) is the ratio of the power in one phase-modulated sideband per Hz,

to the total signal power.
Appendix D
FREQUENCY DIVIDERS
REFERENCE DIVIDER
The reference divider operates at low frequencies (frequencies below

500 MHz for 0.18 um CMOS technology). This type of divider is
constructed as a programmable counter designed in standard CMOS
standard cell logic. This divider usually divides the reference frequency
down to the sampling frequency of the PFD.
There are two types of counters used as reference frequency
dividers. These are either synchronous or asynchronous. Both dividers
will be described below.
1.1
Synchronous Dividers
Synchronous frequency dividers can be constructed as pseudorandom

binary sequence (PRBS) counters. A 6-bit PRBS-based counter is
shown in Figure D-1.
These dividers are formed from a shift register of length N with
some taps (either 2 or 4) fed to a modulo-2 adder whose output is
connected to the input of the shift register. If the correct taps are used,
the shift register will clock through a PRBS of length 2N1. It also has
a forbidden state of all zeros; a state if it falls into then it never leaves.
The sequence of 2N1 states does not include the all-zeros state.
Therefore, the divider cannot get into the forbidden state from its
normal counting mode. A problem can possibly occur at switch-on,
which may yield all zeros, or if the counter is accidentally loaded with
all zeros. A good way to protect the divider from this state is to fix the
165
166
Appendix D
terminal count as a code which will be zero. This makes the bit which is
1 a dont care bit. With this arrangement, terminal count is detected
at the defined value and for the forbidden all-zeros state. The terminal
count forces a parallel load on the shift register as part of the normal
divider operation, so it will load a permissible code if the forbidden
state occurs.
q6
q5
L<5:0>
S Q
q1
D1
D0
C
S Q
q2
D1
D0
C
S Q
q3
D1
D0
C
S Q
q5
D1
D0
C
S Q
q4
D1
D0
C
S Q
q6
D1
D0
C
fin
q5
q4
q3
fout
q2
q1
Figure D-1. A 6-bit PRBS Synchronous Divider
These dividers are fast, simple, and fully programmable. They are
nearly as fast and simple for big division ratios as for small ones. The
disadvantages are that they count in pseudorandom fashion (not binary)
so a lookup table is required for division ratios versus parallel load
value. They also consume more power than ripple counters because all
the D-type flip-flops used are clocked at the input clock-rate. If
designed carefully however, the maximum frequency of operation is not
much less than that of a single divide by two using the same D-type
flip-flop.
1.2
Asynchronous Reference Frequency Divider
A simple 6-bit programmable reference divider is shown in figure D-1.

Figure D-2 shows an asynchronous divider comprised of six toggle
flip-flop (TFF) stages. Each TFF can be designed from a simple
set/reset D-type flip-flop and some logic (see Figure D-3).
167
Frequency Dividers
Rout
SN
Rsyn
R<5>
R<4>
R<3>
R<2>
Q
QN
X
Y
SN
D
C
R<1>
Q
QN
RN
Vdd
R<5:0>
QN
L
QN
L
QN
L
Q
QN
R<5>
R<0>
Q
QN
R<4>
R<3>
Q
QN
R<2>
R<1>
Rin
Figure D-2. A Simple Programmable Reference Divider
Q
QN
SN
D
QN
RN
RN SN
Figure D-3. A Basic Toggle Flip-Flop Implementation
The clock drives only the first TFF and each subsequent stage is
driven by the previous output stage. Figure D-4 shows the timing
diagram of the reference divider programmed to divide by 16.
Additional flip-flops and gates are used as decision logic to detect when
the count reaches final count and to reload the divider value.
168
Appendix D
Figure D-4. Reference Divider Timing Diagram
FEEDBACK DIVIDER
The RF feedback divider is the only high-frequency block that

operates at the VCO frequency. Driven by the VCO output clock
frequency, the divider scales the feedback RF signal to the PFD input
clock frequency for comparison with the reference VCXO clock.
2.1
Specification and Different Architecture Evaluation
High speed, power consumption, and low noise are the main
requirements of the VCO frequency divider. The divider needs to
operate at the VCO frequency making it unavoidably power hungry.
However, some architectures have shown to consume less power than
others. A good design is one that can be low noise and consume low
power. These requirements are important as most wireless communication devices are portable and battery operated.
2.1.1
Direct Division versus Prescaler Method
Ideally a MMD such as the one in Figure D-5 driven directly by the
RF VCO frequency (RFin) will give minimal noise as the ratio
169
Frequency Dividers
between RFin and the clock frequency of the fractional '6 modulator
is at a maximum. However, the MMD is implemented using
synchronous CML and hence each stage is driven and operated at the
RF VCO frequency. This implementation yields maximum power
consumption and is difficult to design especially as the divider
modulus is increased from 6 to 7 bits to cover frequency bands such as
802.11b, 802.11g, and BluetoothTM (2.42.5 GHz) or higher
frequency bands such as 802.11a (4.95.805 GHz). Additionally, if
the divider is designed to marginally meet its highest frequency of
operation, this leads to worst noise performance.
The following example illustrates the speed constraint of the
feedback divider: taking the 802.11b band, if the RF channel
frequency is:
2.46 GHz
f RF
(D.1)
and the crystal oscillator frequency is:

40 MHz
f VCXO
(D.2)
then the required divider ratio is:

2460
40
f RF
f VCXO
61.5
(D.3)
Div
Out
AND
MUX1
MUX2
Y B
S
div0
Y B
S
MUX3
MUX4
Y B
S
div1
MUX5
Y B
S
div2
MUX6
Y B
S
div3
A
Y B
S
div4
DFF1
DFF2
DFF3
DFF4
DFF5
DFF6
C Q
C Q
C Q
C Q
C Q
div5
C Q
RF in
XNOR
NOR
XORa
XOR
NAND
XNORa
NORa
NANDa
Figure D-5. Multimodulus Divider Implementation
XNORb
170
Appendix D
Ref.
VCO
PFD/CP
fcomp
MMD
fp
RF
2/4
Prescaler
Feedback Divider
Figure D-6. Divide-by-2/4 Prescaler and MMD in the Feedback Divider
Using a simple third-order Mash modulator, the divisor can have a

maximum value of 65 which clearly cannot be covered by a 6-bit
MMD. To overcome this constraint, a prescaler such as a divide-by-2
or a divide-by-4, as shown in Figure D-6, can be used.
Having an intermediate RF prescaler in the feedback path reduces
the speed constraints of the MMD, this in turn reduces the power
consumption of the MMD as it operates at half the VCO frequency for
the 2.4 GHz bands and a quarter of the VCO frequency for the 56
GHz bands. However, this prescaling in the feedback increases the
noise of the PLL as the quantization noise of the '6 modulator gets
amplified in the loop by a factor of:
20 log10 N p
(D.4)
where N p is the intermediate prescaler value. The additional phase

noise due to this phenomenon is approximately 12 dB for a 5 GHz
synthesized frequency which significantly increases the in-band phase
noise of the fractional-N PLL.
Other architectures that have been used in the past based on dualmodulus architectures such as the phase switching dual-modulus
divider (PSDMD) are reported in [D1, D2].
The PSDMD architecture of Figure D-7 has a much lower power
than the conventional direct MMD as only the first and the second
divide-by-2 prescalers operate at full and at half VCO speeds, respectively. The divide-by-2 prescalers are single ended input to differential
output and operate from rail-to-rail and hence do not require level
shifting to interface to the low frequency CMOS phase multiplexers.
The main drawbacks of this architecture are the possibility of
spikes occurring as the multiplexer switch transitions between phases.
171
Frequency Dividers
INP
INN
/2
0
90
/2
180
270
MUX
4 to 1
/16
OUT
Control
Vdd
INP
Vdd
Vdd
Vdd
INN
OUTP
OUTN
Figure D-7. The Phase Switching Dual-Modulus Prescaler
This could send the wrong information to the modulus control and
hence divide by the wrong divisor. Also the input sensitivity of the
divide-by-2 is much worse than its CML counterpart [D3].
The low frequency CMOS divide-by-16 counter needs to operate at
a quarter of VCO frequency which might be fine for a 2 GHz range
VCO frequency. However, as we move higher in the spectrum to
cover the 802.11a high band of (5.805 GHz), that might be difficult to
achieve. From a noise standpoint, this architecture is similar to that of
the divide-by-4 prescaler-driven MMD as it exhibits similar quantization noise amplification of 12 dB, equation (D.4).
The ordinary DMD in Figure D-8 works somewhat differently
from the PSDMD. A and B counters are loaded with the desired
divider ratio and the prescaler divides by P + 1 as long as the modulus
control is low. When the content of the B counter reaches 0, the MC
goes high and the prescaler divides by P until the content of the
counter A reaches 0. For proper division, counter A has to be greater
172
Appendix D
STATIC CMOS
A
A,B Value
RFin
P/P+1
Logic
Fdiv
Modulus Control
Figure D-8. P/P + 1 Dual-Modulus-Based Prescaler architecture
or equal to B. Hence the prescaler divides by P + 1 for B and by P for

A B, yielding a division of:
B( P 1) ( A B) P
AP B
(D.5)
where A and B values can be determined as follows:
RFin
B
Fdiv
and B
P
RFin
AP
Fdiv
(D.6)
The advantage of this method of feedback division is illustrated in

the synchronized operation of the critical high-frequency P/P + 1
prescaler with the low-frequency A/B counters. Its feedback operation
makes it behave as if it were a direct division MMD without the
disadvantage of high power consumption. Consequently, this method
does not amplify the quantization noise. Its major disadvantage is its
continuous minimum divider value that is limited to P 2 P . The
maximum divider value however is only limited by the size of the A
and B counters.
173
Frequency Dividers
Figure D-9 shows logic implementation of 2/3 DMD. Having the

reset signal at logic high, the divider divides by 3 for MC signal at
logic high and divides by 2 for MC signal at logic low. Figure D-10
shows a simulated operation of a 2/3 DMD.
Using the designed divide-by-2/3 dual-modulus prescaler architecture of Figure D-9, we can design any higher modulus divider.
Figures D-11 and D-13 show the implementation of a 4/5 and 8/9 dualmodulus prescalers, respectively. Figures D-12 and D-14 show their
respective simulated behaviors.
NOR
DFF
D
Output
NOR
C Q
R
DFF
D
Control
Input
Reset
Figure D-9. Divide-by-2/3 Dual-Modulus Prescaler Logic
Figure D-10. Simulated Divide-by-2/3 DMD
174
Appendix D
Divide by 2/3
NOR
DFF
D
NOR
C Q
R
DFF
D
C Q
R
Input
Reset
Output
Divide by 2
DFF
D
NOR
C Q
R
Control
Figure D-11. Divide-by-4/5 MMD implementation
Figure D-12. Simulated 4/5 Divider
175
Frequency Dividers
Divide by 2/3
NOR
DFF
D
DFF
NOR
C Q
R
D
C
Q
R
Input
Reset
Divide by 4
Output
OR
DFF
DFF
D
C Q
R
D
C
Q
R
Control
Figure D-13. Divide-by-8/9 DMD implementation
Figure D-14. Simulated 8/9 DMD divider
176
Appendix D
In implementing the multistandard WLAN of Figure 5-2, the

synthesized frequency is two-thirds of the transmitter frequency. This
indirect method of transmission is used to prevent power amplifier (PA)
pulling of the VCO. The minimum and the maximum synthesized
frequencies are 3.2 and 3.9 GHz, respectively. Bearing in mind that the
reference used is 40 MHz, the minimum divider value is:
RFmin .
Re f
2
3 n
min
4800.
40
2
3 3 77
(D.7)
where RFmin is the minimum transmitter frequency in MHz, Ref is the

reference frequency in MHz and nmin is the order of the '6 MASH
modulator. The maximum divider value is:
RFmax .
Re f
2
3 n
max
5805.
40
2
3 4 100
(D.8)
RFmax is the maximum transmitter frequency in MHz and n max is

the maximum '6 MASH modulator offset value. Examining all the
required divisors, the divider modulus needs to be 7 bits with the MSB
set to logic high.
Another observation is the fact that only the first three bits of the
divisor are modulated due to the implemented third-order '6
modulator. Having this in mind, we can use a 8/9 prescaler method
with the A/B swallow counter with four and three bits, respectively
and the MSB of the A counter (fourth bit) set to a logic high. Figure
D-15, shows the implemented divider architecture.
Having the MSB of counter A tied to Vdd (logic high), the
fractional divider value can be programmed as follows:
N frac
8 >8 N 5 : 3 ! ] N 2 : 0 ! @
(D.9)
where N<5:0> is the output of the '6 modulator described in

chapter 5.
The A and B counters are full-scale static CMOS and operate at a
maximum frequency of 500 MHz. The 8/9 prescaler is the bottleneck
177
Frequency Dividers
Decision Logic
SN
Q
C QN
Reset
SN
Q
C QN
RN
Mod Control
RFin
8/9 Prescaler
0
SN
Q
C QN
RN
Nout
Vdd
<3:0>
Q<3:0>
Counter A Clk
D<6:3>
L<3:0>
Q<2> Q<1> Q<3>

Clk Counter B
D<2:0>
L<2:0>
N<5:0>
N <2:0>
N <5:3>
Vdd
Figure D-15. Multimodulus Divider (MMD) Architecture using 8/9 Prescaler
of the MMD operating at high VCO frequency. It is implemented

using CML. The design of the 8/9 prescaler is described and covered
in the next section.
HIGH-SPEED CMOS DIVIDER DESIGN
Implementing the high-speed prescaler in CMOS requires careful attention. The high-frequency operation means high power consumption.
178
Appendix D
However, using the architecture outlined in Figure D-13, only the flipflops of the front divide-by-2/3 stage operate at full VCO speed. The
rest of the logic operates at half speed. The flip-flops of the divide-by-4
stages operate at half and quarter speeds. All 8/9 prescaler blocks are
designed in high-speed CML.
3.1
Current-Mode Logic Design: An Overview
Unlike static CMOS, CML gates can operate at high frequency in the
GHz region. To help us understand the various elements that set the
speed and hence the power consumption of a CML gate, let us
examine a simple differential CMOS amplifier also a CML inverter.
Figure D-16 shows a basic CML inverter gate.
The speed of the gate is determined by the transient characteristics,
the current drive capability of its load and the propagation delay.
Vdd
Vdd
R
Vdd
Vswing
CL
A
CL
vin
vin
Vb
(a)
Rs
(b)
Figure D-16. Basic CML Gate (a) Biased Gate (b) Simplified Gate with Capacitive Load
179
Frequency Dividers
Rg
vg
C gd
Cgs
vd
gmVgs
Csb
gmVbs
Ro
vs
CL
Cdb
Rs
Figure D-17. CML Gate Half-Circuit Model
Using the half circuit of Figure D-16b, we can derive the propagation
delay of the CML inverter gate. Figure D-17 shows half the CML gate
circuit model.
We can treat the delay as four components for simplicity:
W1 W 2 W 3 W 4
(D.10)
Each delay component can be studied separately. For W 1 , delay term

due to gatesource capacitance, use Figure D-18, we can ignore gmb
and Ro:
R1
vT
iT
W1
R1Cgs
Rg Rs
1 g m Rs
Rg Rs
Cgs
1 g m Rs
where VT is the input voltage at the gate of the MOS gate.
(D.11)
(D.12)
180
Appendix D
Rg
vd
iT
gmVs
gmVT
VT
Ro
vs
Rs
Figure D-18. Simplified Model to Derive First Delay Term
To derive the second delay term due to gatedrain junction

capacitance, we ignore gmb and Ro, Figure D-19 is used as follows:
R2
vT
iT
Rg R
vg
Rg
gm
Rg R
1 g m Rs
vT
(D.13)
vd
iT
gmvgs
gmbvbs
Ro
vs
Rs
Figure D-19. Simplified Model to Derive Second Delay Term
181
Frequency Dividers
W2
gm
Rg R Cgd
Rg R
1 g m Rs
(D.14)
For the third delay term, W 3 due to sourcebulk junction capacitance,

the simplified circuit model of Figure D-20 is used:
-g mv T
-g mb v T
Ro
iT
vT
Rs
Figure D-20. Simplified Model to Derive Component due to Sourcebulk Capacitance
R3
Rs
1 g m Rs
W3
R3Csb
Rs
Csb
1 g m Rs
(D.15)
(D.16)
Similarly for the fourth delay term, W 3 due to the capacitive load
CL and drainbulk junction capacitance, Figure D-21 shows the
simplified circuit model, where we can ignore Ro:
W4
R Cdb CL
(D.17)
182
Appendix D
Ro
iT
vT
Rs
Figure D-21. Simplified Circuit Model to Derive fourth Delay Term
The total propagation delay of the CML inverter then becomes:
Rg Rs
RC
gm
Cgs Rg R
Rg R Cgd s sb
1 g m Rs
1 g m Rs
1 g m Rs
Cdb CL R
(D.18)
Rs 0 (AC ground for differential mode) and consider Rg

negligible series gate resistance. This leads to:
R Cgd Cdb CL
Vswing
I
WC
ov
WLd C jd CL
(D.19)
Where Cov is the oxide capacitance, Cjd the drain junction capacitor, W
and L are transistor dimensions. Vswing is the required output voltage
swing. Knowing the required swing and the required speed we can
choose the transistor dimensions and the differential tail current
required to drive the CML gate.
183
Frequency Dividers
IMPLEMENTED CML GATES

NOR/OR
alternative
NOR
Vdd
R
Vdd
R
Q
Or
B
Nor
B
A
Vb2
A
V b1
Vb
(a)
(b)
Vdd
NAND/AND
R
R
Q
Vb
(c)
Figure D-22. Basic CML Gates Implementation (a), (b) NOR/OR, and (c) NAND/AND
184
Appendix D
MUX
XOR/XNOR
Vdd
Vdd
A B
A
A
Vb
Vb
(a)
(b)
D-Latch
Vdd
Q
D
Clk
Clk
Vb
(c)
Figure D-23. CML gates (a) Multiplexer, (b) XOR/XNOR, and (c) Latch
185
Frequency Dividers
Vdd
Vdd
R
Nor
Or
Vb2
Clk
Clk
Clk
Vb1
Vb1
Slave
Master
(a)
Vdd
Vdd
Vdd
Q
Q
Clk
Clk
Master
Clk
Clk
Vb
Vb
Vb
MUX
Slave
(b)
Figure D-24. Combination CML Logic (a) NOR/OR Mater/Slave D-Type Flip-Flop
(b) MUX/D-Type Flip-Flop
REFERENCES
[D1] J. Craninckx and M. Steyaert A 1.75-GHz/3-V Dual-Modulus Divideby-128/129 Prescaler in 0.7-m CMOS, JSSC, 31, 7, pp. 890897,
July 1996.
[D2] R. Ahola and K. Halonen, A 4 GHz CMOS Multiple Modulus Prescaler,
Proceedings of IEEE ICECS 1998, Lisbon, Portugal, Sept. 1998,
pp. 2.3232.326.
[D3] T. Seneff et al., A Sub-1 mA 1.6 GHz Silicon Bipolar Dual Modulus
Prescaler, IEEE Journal of Solid-State Circuits, 29, pp. 12061211,
Oct. 1994.
Appendix E
PROGRAMS AND CODES
MATHCADTM PROGRAM USED FOR THE

SIMULATIONS OF ALL THE MATHCAD
FIGURES
Mathcad program used for the simulation of all Mathcad figures

presented in the book.
Defining the Units:f { 10
15
M { 10
p { 10
G { 10
12
n { 10
T { 10
12
9
P { 10
R 10
6
m { 10
Set Resolution:-
3
Hz
Defining the Loop Parameters:K vco 100 M
MHz/V
VCXO_Ref_Freq 40 MHz
KI 2.0 m
mA
Fsamp 40 M Hz
Samples per decade
Start_Freq 10
The Log sweep...
Stop_Freq 10 M
Duty Cycle 2 S
Fmax
Hz
XScale (F ) 10
Duty Cycle
1725 M Hz
Fmin 1725 M Hz
187
10
k { 10
188
Appendix E
The Linear Sweep...

F 10log ( Start_Freq ) 10log ( Start_Freq )
If FM modulation is applied at the VCO
then this value must be entered .
10
R
10log( Stop_Freq )
K fm K vco
K fm 200k
Enter values for calculating the loop filter components:-
LBW 100k Hz
Ip 56 Degrees
ATTEN 15 dB
(Make this value0to remove the
additional R3 C3 low pass filter)
RF Noise Source Values:VCO Noise
VCO_9dB 1.3k VCONoise_Plateau 159

VCO_3dB 8 M VCO_6dB 8 M
dBc/Hz
189
Programs and Codes

Noise Sources
Reference Oscillator Noise
VCO Divider Noise
Ref Noise_Plateau 143 dBc/Hz
VCODiv_Plateau 173
Ref_3dB 10k Ref_6dB 1 k
RF Amplifier Noise
Ref_9dB 100
Amp_NF 8
Ref_12dB 10
dBc/Hz
VCODiv_Noise_3dB 0.3
dBm
Power_in 15
dB
Hz
Reference Divider Noise
Ref Div_Plateau 173 dBc/Hz R_Div_3dB 0.3 k

Amp_Gain 25 dB
R_Div_6dB 10
RFAmp_noise_3dB 100
)n_Plateau 216 dBc/Hz

)n 3dB 8 M
)_3dB 1 k
)_6dB 50
)_9dB 20 )_12dB 5
Loop Filter Value CALCULATIONS

Type 2 Second-Order Filter
K v K vco
Kv
Zp 2 S LBW
8
sec Ip
T1
Zp
rad
LBW
1 u 10
1 u 10
C1T22O
C1T22O
Fsamp
tan Ip S
180
180
43.125
T2
Zp
FmaxFmin
N
Z p T1
2
1 2 S LBW T2
1 2 S LBW T1
K
KI
T1 vco
Z p rad
N
T2 2 S LBW
9
3.591536 u 10
7
T1
4.866 u 10
T2
5.206 u 10
6
T2
C2T22O C1T22O
T1
C2T22O
8
3.483242 u 10
ATTEN
Type 2 Third-Order Filter
T3
10
20
1
2 S Fsamp 2
1
R2T22O
R2T22O
T2
C2T22O
149.451
190
Appendix E
1
T2
( T1 T3) tan Ip
180
( T1 T3)
( T1 T3) 2 T1 T3
C1T23O
( T1 T3) T1 T3
2
S
2
( T1 T3) tan Ip
180
T1
T2

S
( T1 T3) tan Ip 180
( T1 T3) 2 T1 T3
1 1
1
2
( T1 T3) T1 T3
2
S
2
( T1 T3) tan Ip
180
1 1
K vco KI
N
( T1 T3) tan Ip S
2
180
T2
2
( T1 T3) T1 T3
( T1 T3) T1 T3
11 1
2
S
2
( T1 T3) tan Ip
180
( T1 T3) 2 T1 T3
2
1 1 T1
S
2
( T1 T3) tan Ip
180

( T1 T3) tan Ip S
180
1
( T1 T3) 2 T1 T3

1
2
( T1 T3) 2 T1 T3
2
1 1 T3
S
2
( T1 T3) tan Ip
180

( T1 T3) tan Ip S
180
1
( T1 T3) 2 T1 T3

C2T23O C1T23O
T2
1
T1
C1T 23O
9
3.665 u 10
C3 T23O
T2
R2 T23O
C2T23O
10
3.665 u 10
C1 if ATTEN 0 C1T22O C1T23O
C2 T23O
C3 T23O
C1T23O
8
3.635 u 10
R3 T23O
10
R2 T23O
C2 if ATTEN 0 C2T22O C2T23O
146.14
T3
C3 T23O
R3 T23O
23.342
C3 if ATTEN 0 0 C3 T23O
191
Programs and Codes

R2 if ATTEN 0 R2 T22O R2 T23O
R3 if ATTEN 0 0 R3T23O
Giving the following values:NOISE CALCULATIONS

Reference Noise Calculation
R
VCXO_Ref_Freq
Fsamp
This line calculates the R divider logic noise floor including the 1/f corners for this R divider.
R_Div_Noise ( FrqPoint) Ref Div_Plateau 10log 1 j
R_Div_3dB
FrqPoint
10log 1 j R_Div_6dB
FrqPoint
This line calculates the ideal divided down (due to the R term) of the incoming reference VCXO source.
Note that this is a direct curve fit on the specification and makes no attempt to correct for the usual oscillator
.
1/f corners, giving 10Log breakpoints.
Ref_3dB
Ref_6dB
Ref_Div ( FrqPoint) Ref Noise_Plateau 10log 1 j

10log 1 j
FrqPoint
FrqPoint
10log 1 j
Ref_9dB
FrqPoint
10log 1 j Ref_12dB 20log(R)
FrqPoint
This VXCO SSB Phase Noise Plot represents the free running VCXO which is considerably
cleaner than the 16 MHz clean upused. This is because the 16 MHz cleanup loop has
a loop bandwidth of the order of 40 Hz, there after the phase noise follows the logic noise and
Op-Amp noise profile of the other components in that loop. These values are not modeled here,
giving an optimistic account of this loops output. This will reflect in a better than measured value in
the main synthesizer output for this part of the phase noise profile.
Hence, the actual phase noise profile of the signal at the sampling frequency is:-
Samp_Freq_Noise( FrqPoint) 10log 10
Ref_Div ( FrqPoint)
10
R_Div_Noise ( FrqPoint)
10
Reference VCXO SSB Phase Noise
80
SSB Phase Noise, L( f ) (dBc/Hz)
10
90
100
110
120
130
140
150
160
170
180
190
200
210
10
100
1 10
1 10
1 10
Frequency, f(Hz)
Sampling Frequency Phase Noise

Theoretical Divided Down Reference Noise
R Divider Noise
Reference Frequency Noise
1 10
1 10
192
Appendix E
The effect of the R divider logic noise plateau becomes particuraly important when considering low
sampling frequencies and very large VCO frequencies and hence multiplication of this reference noise.
The clear distinction has to be made between the sampling frequency phase noise and the phase frequency
logic noise.
VCO Noise Calculation
VCONoise ( FrqPoint) VCONoise_Plateau 10log 1 j
10 log 1 j
VCO_9dB
FrqPoint
VCO_3dB
FrqPoint
10 log 1 j VCO_6dB
FrqPoint
Phase Noise at different offsets:-
40
50
10
10
VCONoise 10 120.937 VCONoise 10 100.902
30
10
VCONoise 10 78.789
L(800 kHz)=
SSB Phase Noise, L( f )(dBc/Hz)
10 log( 800 k)
10
VCONoise 10
138.957
Free Running VCO SSB Phase Noise
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
10
100
1 10
1 10
1 10
Frequency, f(Hz)
1 10
1 10
Phase Detector Noise Calculations

This first line calculates the frequency profile of the normalized phase detector noise.
PD_Noise_Norm( FrqPoint) )n_Plateau 10log 1
)_9dB
10log 1
FrqPoint
)_3dB
FrqPoint
10log 1 )_6dB
FrqPoint
10log 1 )_12dB
rqPoint
This line denormalizes this normalized phase detector noise profile.
10log 1
PD_Noise ( FrqPoint) PD_Noise_Norm( FrqPoint) 10log( Fsamp) 20log FmaxFmin
Phase Noise at 1 MHz offset:-
PD_Noise 10
60
10
99.499
Fsamp
)n3dB
193
1/f Corners Effect on Normalized Noise
180
188
196
204
212
220
10
3
4
5
6
7
100 1 10 1 10 1 10 1 10 1 10
Frequency, (Hz)
SSB Phase Noise, L ( f ) (dBc/Hz)
Normalised Noise, (dBc/Hz)
Programs and Codes
Phase Detector Denormalized SSB Noise
60
68
76
84
92
100
3
4
5
6
7
100 1 10 1 10 1 10 1 10 1 10
Frequency, f(Hz)
10
VCO Divider Noise Calculation

VCODiv_Noise ( FrqPoint ) VCODiv_Plateau 10 log 1 j
VCODiv_Noise_3dB
FrqPoint
RF Amplifier Noise Calculation

Some constants...
23 J/K
K { 1.38066210
T { 273.14
B{1
Hz
Calculation of Amplifier Noise

RFAmp_Plateau Amp_NF 10 log( K T B) 30 3 Power_in
RFAmp_Plateau
giving...
dBc/Hz
154.235
Hence TOTAL RF Noise of the VCO and the RF Amplifier is calculated...

RFAmp_noise_3dB
RFAmp_noise ( FrqPoint ) RFAmp_Plateau 10log 1 j
FrqPoint
RFAmp_noise ( FrqPoint )
VCONoise ( FrqPoint )
10
10
VCOEffective_Noise( FrqPoint ) 10log 10
10
Effective VCO SSB Phase Noise
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
10
100
1 10
1 10
1 10
Frequency, f(Hz)
1 10
1 10
194
Appendix E
LOOP GAIN PARAMETER CALCULATIONS
Nm
K pd
Fmin Fmax
Fsamp Fsamp
N m 43.125
Fvco
KI
K pd
DutyCycle
K v Kvco 2 S
Kv
Fmax Fmin
4 A/Rad
3.183 u 10
8
6.283 u 10
R2
Rad/V
146.14
Filter Transfer Calculation
Fs ( FrqPoint) if ATTEN
1 j 2 S FrqPoint R2 C2
0
j 2 S FrqPoint ( C1 C2) 1 j 2 S FrqPoint R2
C1 C2
C1 C2
j 2 S FrqPoint C3
Filter Gain, (dB)
1
C1 C2
1 j 2 S FrqPoint R2 C2 1 j 2 S FrqPoint R3 C3 ( C1 C2) 1 j 2 S FrqPoint R2

C1 C2
C3

Loop Filter Frequency Gain Response
200
180
160
140
120
100
80
60
40
20
0
20
40
60
80
100
Filter Phase, (Deg)
10
100
3
4
5
1 10
1 10
1 10
Frequency, f(Hz)
1 10
1 10
Loop Filter Phase Response
180
160
140
120
100
80
60
40
20
0
20
40
60
80
100
120
140
160
180
10
100
3
4
5
1 10
1 10
1 10
Frequency, f(Hz)
1 10
1 10
195
Programs and Codes

Calculating the Loop Gain Terms
Aol ( FrqPoint ) Fs ( FrqPoint )
Kv
j 2 S FrqPoint
K pd
FB
4
K pd
Nm
3.183 u 10
10
5
F
10 180
d
arg Fs 10
5
10
Magnitude, (dB)
10
Magnitude, (dB)
100
1 10
1 10
1 10
XScale( F)
1 10
1 10
1 10
1 10
1 10
Closed Loop Frequency Response
20
0
20
40
60
80
100
120
140
160
180
200
10
100
3
4
5
1 10
1 10
1 10
Frequency, f(Hz)
1 10
Closed Loop FM Response
20
10
0
10
20
30
40
50
60
70
80
90
100
10
Phase, (Deg)
dF
100
3
4
5
1 10
1 10
1 10
Frequency, f(Hz)
1 10
Closed Loop Phase Response
180
150
120
90
60
30
0
30
60
90
120
150
180
10
100
3
4
5
1 10
1 10
1 10
Frequency, f(Hz)
1 10
196
Appendix E
Final Noise Summation Calculation

1
VCO_LoopGain_dB (FrqPoint) 20log
1 Aol( FrqPoint) FB
Aol( FrqPoint)
1 Aol(FrqPoint) FB
Ref_in_LoopGain_dB ( FrqPoint) 20log
Aol( FrqPoint) FB
1 Aol(FrqPoint) FB
Aol( FrqPoint)
VCODiv_LoopGain_dB ( FrqPoint) 20log
1 Aol(FrqPoint) FB
PD_LoopGain_dB ( FrqPoint) 20log
VCO_Loop_Noise_dB ( FrqPoint) VCO_LoopGain_dB ( FrqPoint) VCOEffective_Noise ( FrqPoint)

Samp_Freq_Loop_Noise_dB ( FrqPoint) Ref_in_LoopGain_dB( FrqPoint) Samp_Freq_Noise(FrqPoint)
VCODiv_Loop_Noise_dB( FrqPoint) VCODiv_LoopGain_dB( FrqPoint) VCODiv_Noise (FrqPoint)
PD_Loop_Noise_dB( FrqPoint) PD_Noise ( FrqPoint) PD_LoopGain_dB(FrqPoint)
Samp_Freq_Loop_Noise_dB ( FrqPoint)
VCO_Loop_Noise_dB ( FrqPoint)
10
10

10
Total_Noise( FrqPoint) 10log 10
VCODiv_Loop_Noise_dB( FrqPoint)
PD_Loop_Noise_dB( FrqPoint)
10
10
10log 10
10
10 log ( 1.7 k)
10
Total_Noise 10
96
Small_Angle ( FrqPoint) 10log( FrqPoint) 30
Marker1
log( Marker1)
Marker1 10
577 P
L(1.5 kHz)=
Phase Noise at:-
10
Filter Values:-
Marker2 10
L(800 kHz)=
Phase Noise at:-
10log (800k)
10 log(1.5 k)
Total_Noise 10
log( Marker2)
Marker2 135k
dBc/Hz

95.647
Total_Noise
10
125.955
10
dBc/Hz
Loop Gain Values:-
9
C1 3.665 u 10
8
C2 3.635 u 10
K vco
1 u 10
Hz/V
KI 0.002
Amps
7 Hz
Fsamp 4 u 10
Fvco
1.725 u 10
R2 146.14
Ohms
R3 23.342
Ohms
Phase Margin:-
LBW 1 u 10
Ip 56
10
Hz
Loop Filter Dynamic Values:-
C3 3.665 u 10
Hz
Degrees
197
Programs and Codes

Total SSB Phase Noise Of Synthesizer
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
10
100
1 10
1 10
Frequency, f(Hz)
1 10
1 10
1 10
VCO Noise Contribution

Sampling Frequency Noise Contribution
Digital Phase Detector Noise Contribution
VCO Divider Noise
Total Synthesizer Noise
Total SSB Phase Noise Of Synthesizer
0
10
20
SSB Phase Noise, L( f) (dBc/Hz)
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
10
100
1 10
VCO Noise Contribution

Phase Detector Noise
Reference Signal Noise
Total Synthesizer Noise
Small Angle Line
1 10
Frequency, f(Hz)
1 10
1 10
1 10
198
Appendix E
MATLABTM PROGRAM USED FOR THE

SIMULATIONS OF THE FRACTIONAL-N
PLL NOISE SPECTRUM
% Definition of the PLL elements
f_max=1898.208/90;
f_min=1880.928/92;
f_s=20e06;
N=91;
V_max=5;
V_min=0;
% Wanted T_L approx 2*pi/Wn <= 30 us
% <=> Wn >= 2*pi/ 30 us ~ 209.439 krads
T_L=30e-06;
Wn=2*pi/T_L;
xi=0.7;
K_pfd=(V_max-V_min)/(4*pi);
% gain for classic PFD with CP
K_vco=2*pi*20e06/(V_max-V_min);
K_filt=1;
K_t=K_vco*K_pfd*K_filt;
K=K_t/N;
K_gain=1000;
% K> 1.3614 = Wn*N/(2*xi*K_t) insure that Wz >=0
K=K*K_gain;
Wp= (Wn^2)/K;
% Wp/(Wn)^2 =1/K;
% xi = 0.5* (Wp/Wn + Wn/Wz)
% 1/Wz= 2 *xi/Wn 1/ K
if (1/K +2 *xi/Wn) >=0
Wz= 1/(1/K + 2 *xi/Wn);
else
Wz=0;
sprintf('Increase the loop gain or the lock in time')
end
Programs and Codes

dsm_order=5;
f_ref=20e06;
% Noise contribution in the PLL
f_min=1; % 10^fmin=10 Hz
f_max=7; % 10^fmax=10 MHz
N_f=100;
% Number of points
f=logspace(f_min,f_max,N_f);
s=j*2*pi*f;
% Definition of the close-loop transfer function H and 1-H
Hcl_2nd_order=Wn^2*[s/Wz + 1]./[(s.^2) + 2*xi*Wn*s+ Wn^2];
% Closed-Loop Gain of 2nd order
Gol_2nd_order=Hcl_2nd_order./(1-Hcl_2nd_order);
% Open-Loop Gain of 2nd order
Wp2=10*Wp;
% Further suppression at 10 times the frequency
Gol_3rd_order=Gol_2nd_order./(1+s/Wp2);
% Open-Loop Gain of Loop Filter + Suppression Filter
Hcl_3rd_order=Gol_3rd_order./(1+Gol_3rd_order);
% Closed-Loop Gain of 3rd Order
Hcl=Hcl_3rd_order;
% Closed-Loop Gain of 3rd Order
one_min_H_cl=1-Hcl;
% Complement of Closed-Loop Gain of 3rd order
%semilogx(f,10*log10(abs(Hcl)))
% contribution from the VCO
f_p1=50;
f_z1=10^(6.5);
s_phi_vco1_f=100./((f/f_p1).^3).*((f/f_z1).^3+1);
% article micro and RF nov 1994
% does not qualify as the phase noise is too high at high frequency
% ... and S_phi_out = S_phi_vco at high frequency !!
s_phi_vco2_f= 10^-14.5+10^-1.5 ./f.^3+10^-1.5 ./f.^2;
% formula p 171 poly goldberg 1998
s_phi_vco_f=s_phi_vco2_f;
figure(1)
199
200
Appendix E
subplot(2,1,1),semilogx(f,10*log10(s_phi_vco1_f),'b',f,10*
log10(s_phi_vco2_f),'r')
title('different Phase noise characteristic for the crystal oscillator')
% contribution from the crystal frequency reference
% p 93 poly Goldberg, state of the art Xtal
s_phi_state1(1)=10^(10);
s_phi_state1(2)=10^(13);
s_phi_state1(3)=10^(14.3);
s_phi_state1(4)=10^(15.8);
s_phi_state1(5)=10^(16.4);
s_phi_state1(6)=10^(17);
s_phi_state1(7)=10^(17);
f1=logspace(0,7,8);
s_phi_in1_f=s_phi_state1(1)./(f.^3).*((f/10) + 1).*
((f/100) + 1).*((f/5e03) + 1);
% s_phi_in1_f is the linear approximation from the vco p93
% Microwave and RF 1994
s_phi_in2_f=1e-04./((f).^3).*((f/10^3).^2+1).*((f/(4*10^4))+1);
% (Pretty noise at low frequencies !!)
% too ideal xtal below !! (from example)
s_phi_in3_f=1e-011./((f).^3).*((f/10).^2 + 1).*((f/100) + 1) ;
% phase noise of Hy-Q oscillator
s_phi_in4_f=10^(-5.3)./(f.^4).*((f.^3/5e04) + 1).*((f/8e03) + 1);
figure(1)
subplot(2,1,2),semilogx(f,10*log10(s_phi_in1_f),'b',...
f,10*log10(s_phi_in2_f),'r',f,10*log10(s_phi_in3_f),'g',f,10*
log10(s_phi_in4_f),'m')
title('different Phase noise characteristic for the crystal oscillator')
s_phi_in_f=s_phi_in1_f;
% s_phi_in3 is too ideal and s_phi_in2 is too bad (too much noise
% with in the loop bandwidth, one should achieve 80 dBc for DECT
% contribution from the loop filter
s_phi_loop=10^(-11)./((f).^3).*((f/(30)).^2+1).*((f/1e02)+1);
% contribution from the frequency detector
Programs and Codes

% sphi= 10^{10.6 +/0.3}/f 22 dB
s_phi_pd_f=10^(2.2)*10^(10.6)./f;
%s_phi_pd=10^(22/10)* tf([10^(10.6)],[1 0]);
% contribution from the frequency divider
% Integer-N case
s_phidn=(10^(14.7)./f + 10^(16.5));
s_phi_dn_int=s_phidn;
%s_phi_dn_int=s_phidn + s_phidn.*abs(Hcl).^2;
% plot of the phase noise source before filtering, N integer
figure(2)
subplot(2,1,1),semilogx(f,10*log10(s_phi_dn_int),'b',f,10*
log10(s_phi_pd_f),'r',...
f,10*log10(s_phi_loop),'g',...
f,10*log10(s_phi_in_f),'m',f,10*log10(s_phi_vco_f),'c');
grid on
set(gcf,'DefaultTextColor','k')
xlabel('frequency (Hz)')
ylabel('S_\Phi (dB)')
title('Phase noise source before filtering N integer')
set(gcf,'DefaultTextColor','c')
text(1e03,-70,'S_\Phi_{ vco}')
set(gcf,'DefaultTextColor','m')
text(1e01,-120,'S_\Phi_{ ref}')
set(gcf,'DefaultTextColor','b')
text(1e06,-170,'S_\Phi_{ dn}')
set(gcf,'DefaultTextColor','r')
text(1e03,-150,'S_\Phi_{ pfd}')
set(gcf,'DefaultTextColor','g')
text(1e06,-154,'S_\Phi_{ loop filter}')
% Fractional-N case
% depends on the variable dsm_order
s_phi_switch=(2*pi)^2/(12*f_ref).*abs(2*sin(f*pi/f_ref)).^(2*
(dsm_order-1));
s_phi_dn_frac=s_phidn+s_phi_switch;
201
202
Appendix E
% plot of the phase noise source before filtering , N Fractional

figure(2)
subplot(2,1,2),semilogx(f,10*log10(s_phi_dn_frac),'b',f,
10*log10(s_phi_pd_f),'r',...
f,10*log10(s_phi_loop),'g',...
f,10*log10(s_phi_in_f),'m',f,10*log10(s_phi_vco_f),'c');
grid on
title('Phase noise source before filtering, N frac')
text(1e03,-70,'S_\Phi_{ vco}')
text(1e01,-120,'S_\Phi_{ ref}')
text(1e06,-170,'S_\Phi_{ dn}')
text(1e03,-150,'S_\Phi_{ pfd}')
text(1e06,-154,'S_\Phi_{ loop filter}')
% Summation of all the contribution
S_phi_inband_int=(s_phi_in_f+s_phi_dn_int+s_phi_pd_f)*N^2.*
(abs(Hcl)).^2;
% multiply by |H|^2
S_phi_out=(s_phi_vco_f+s_phi_loop./f.^2).*(abs(one_min_H_cl)).^2;
% multiply by |1-H|^2
S_phi_tot=S_phi_inband_int+S_phi_out;
figure(3)
subplot(2,1,1),semilogx(f,10*log10(s_phi_dn_int*N^2.
*(abs(Hcl)).^2),'b',...
f,10*log10(s_phi_pd_f*N^2.*(abs(Hcl)).^2),'r',...
f,10*log10(s_phi_loop./f.^2 .*(abs(one_min_H_cl)).^2),'g',...
f,10*log10(s_phi_in_f*N^2.*(abs(Hcl)).^2),'m',...
f,10*log10(s_phi_vco_f.*(abs(one_min_H_cl)).^2),'c',
f,10*log10(S_phi_tot),'b-.');
grid on
Programs and Codes

title('Phase noise source after filtering')
text(1e06,-130,'(1-H)^2 S_\Phi_{ vco}')
text(1e01,-70,'N^2 H^2 S_\Phi_{ ref}')
text(1e07,-165,'N^2 H^2 S_\Phi_{ dn}')
text(1e05,-200,'N^2 H^2 S_\Phi_{ pfd}')
text(1e02,-250,'(1-H)^2 f^{-2} S_\Phi_{ loop filter}')
% DECT phase noise mask
N_l=4*N_f;
f_l=logspace(log10(1.2e06),f_max,N_l);
dect_mask(1:2)=10^-(8);
dect_mask(3:4)=10^-(8.5);
% -85 dBc @ 100 kHz
decal=4;
dect_mask(decal+1:decal+174)=10^(9.5);
f_l(1) =1.2 MHz
dect_mask(decal+175:decal+257)=10^(11.7);
% f_l(174) ~3 MHz
dect_mask(decal+258:decal+N_l)=10^(13.5);
% f_l(257) 4.67 MH < 4.7 MHz
figure(4)
subplot(2,1,1),semilogx(f,10*log10(S_phi_tot),'b',f,10*
log10(s_phi_vco_f),'c',...
[10,1e05-1,1e05,1.2000e+06,f_l],10*log10(dect_mask),'k')
title('Overall phase noise and phase mask');
grid
% fractional case
S_phi_inband_frac=(s_phi_in_f+s_phi_dn_frac+s_phi_pd_f)*N^2.*
(abs(Hcl)).^2;
S_phi_tot_frac=S_phi_inband_frac+S_phi_out;
203
204
Appendix E
figure(3)
subplot(2,1,2),semilogx(f,10*log10(s_phi_dn_frac*N^2.
*(abs(Hcl)).^2),'b',...
f,10*log10(s_phi_pd_f*N^2.*(abs(Hcl)).^2),'r',...
f,10*log10(s_phi_loop./f.^2 .*(abs(one_min_H_cl)).^2),'g',...
f,10*log10(s_phi_in_f*N^2.*(abs(Hcl)).^2),'m',...
f,10*log10(s_phi_vco_f.*(abs(one_min_H_cl)).^2),'c',
f,10*log10(S_phi_tot_frac),'b-.');
grid on
title('Phase noise source after filtering')
text(1e06,-130,'(1-H)^2 S_\Phi_{ vco}')
text(1e01,-70,'N^2 H^2 S_\Phi_{ ref}')
text(1e07,-165,'N^2 H^2 S_\Phi_{ dn}')
text(1e05,-200,'N^2 H^2 S_\Phi_{ pfd}')
text(1e02,-250,'(1-H)^2 f^{-2} S_\Phi_{ loop filter}')
figure(4)
subplot(2,1,2),semilogx(f,10*log10(S_phi_tot_frac),'b',f,10*
log10(s_phi_vco_f),'c',...
[10,1e05-1,1e05,1.2000e+06,f_l],10*log10(dect_mask),'k')
title('Overall phase noise and phase mask');
grid
The following M-file reads in the captured output of the simulated HDL
of the delta sigma block as applied to the MMD.
clear all;
Ts=25; %sampling period is 24nS
fid=fopen('HDL_deltasigma_out_data70p5.dat','r');
out=fscanf(fid,'%i %i %i\n',[3 inf]);
fclose(fid);
Programs and Codes
205
%M=1000044;
%M=length(out(1,:));
frac=out(2,:);
int=out(1,:);
inst_div=out(3,:);
%M=length(frac);
M=2^19;
y2=inst_div;
y2=y2(20001:M);
mean(y2)
M=length(y2);
fs=1/(Ts*1e-9);
f=(1:M)*fs/M/1e3;
win=hanning(M);
win=win';
a2=abs(fft(y2.*win));
a2=(a2.*a2)/M;
a2=a2(1:M/2);
f=f(1:M/2);
a2=10*log10(a2/max(a2));
figure(1),plot(f,a2);
xlabel('FREQUENCY (KHz)');
ylabel('MAGNITUDE (dB)');
axis([min(f) max(f) -350 0]),grid;
title('Output spectrum of Nemo Delta Sigma Modulator (VHDL)');
delta_f=fs/M;
place=floor(1000e3/delta_f);
a3=a2(1:place);
f3=f(1:place);
figure(2),plot(f3,a3);
ylabel('POWER SPECTRUM (dB)');
axis([min(f3) max(f3) -350 0]),grid;
title('Baseband output spectrum of Nemo Delta Sigma Modulator (VHDL)');
fB=200e03;
% The cutoff frequency = fpass
fstop=2000e03;
% The stop frequency
rp=3;
% pass band attenuation in dB
rs=30;
% stop band attenuation in dB
wp=fB*2/fs;
% pass normalized frequency
ws=fstop*2/fs; % stop normalized freuqnecy
[filt_order,wn]=buttord(wp,ws,rp,rs);
[b1,a1]=butter(filt_order,wn); % calculate coefficents of butterworth filter
filtered=filter(b1,a1,y2);
206
Appendix E
a4=abs(fft(filtered.*win));
a4=(a4.*a4)/M;
a4=a4(1:M/2);
a4=10*log10(a4/max(a4));
figure(3),plot(f,a4);
axis([min(f) max(f) -350 0]),grid;
title('Filtered spectrum of MASH output');
% to be able to print the results you have to decimate the results before
presenting
a5=a2(1:64:length(a2));
f5=f(1:64:length(f));
title('Decimated output spectrum of MASH');
a6=a3(1:64:length(a3));
f6=f3(1:64:length(f3));
title('Decimated baseband output spectrum of MASH');
a7=a4(1:64:length(a4));
title('Decimated filtered spectrum of MASH output');
Index
DC offset compensation 13
dead zone 48, 71, 76, 77, 132, 138
deltasigma modulators ix, 2, 67
deltasigma noise 50, 58, 98
design methodology ix, x, 155
differential to single-ended conversion 12
differentiators 95
digital accumulator 34, 35, 36, 90
digital domain 13, 133
digital-to-analog converters 12, 116
direct frequency synthesis 1, 131
direct modulation 133
direct-sequence spread spectrum 8
direct conversion 107, 109
dithering 57, 98, 132
divide-by-2 13, 107, 170
dividers 19, 36, 62, 89, 131, 143, 165
feedback 19
reference 19
dual-type flip-flop 71
dual-modulus prescaler 19, 35
duty cycle 30, 47, 52, 108
2s complement 96
802.11 a, b and g 3, 10
accumulator-based implementation 95
adaptive band switching 2, 111, 132
adaptive charge pump 2, 111, 113, 116,
117, 128, 132
adjacent channel rejection 13
attenuation 12, 205
automatically calibrated 12
average divide ratio 2, 45
balanced to unbalanced transformer 12
band switching 103, 126, 127, 128
bandgap reference 119
bandwidth 8, 32, 47, 105, 117, 133, 147,
158, 202
base band 10, 38
behavioral modelling 2, 45, 47
Bluetooth 7, 14
calibration 117, 122, 125, 128
calibration algorithm 125
carrier frequency 149, 153, 163
carry look ahead 93
channel selection 12
charge pump 17, 71, 113, 138
closed loop 1
CML see current mode logic
CMOS process 2, 67, 73, 102, 113, 131
complementary code keying 7
CP linearization 127
current mismatches 73
current-mode logic 89
cutoff frequency 12
error cancellation algorithm 95

error vector magnitude 42
extra filtering 13
feed-through 18, 73, 139
flicker noise 13, 29, 42, 86
FM demodulated 105
frequency bands 13, 131, 169
frequency domain 47, 55
frequency pulling 1
frequency synthesizers
207
208
fractional-N 1, 34
integer-N 1
front-end signal paths 12
GSM system 159
guard rings 108
impulse sensitivity functions 30
in-band phase noise 38, 72, 170
indirect frequency synthesis 3
integer multiples 60, 99
inter-subcarrier interferences 107
IQ filters 12
IQ image rejection mixer 86
limit cycles 57, 59, 60, 97, 99
linear time invariant xi
local oscillator 11, 53, 105, 131
local oscillators 1, 11, 131
locking time 26, 107, 128
lookup table 13
loop filter 20
loop filter design 15, 42, 131
low-noise amplifier 10
MASH-1-1-1 36, 67, 90, 131
mismatch cancellation 75, 76
mixers 5, 13, 107, 133
mobile phones 7
motional capacitance 143
motional inductance 143
negative-edge triggered 108
NMOS 74, 79, 86
noise contributions 1, 15, 27, 40, 131, 147
noise shaping 90, 93, 108, 113
noise spectrum 29, 57, 97, 161, 162, 198
nonoverlapping 10
normal distribution 50
OFDM 7, 9, 10
offset current 62, 78, 79, 81
offset frequency 50, 153, 158, 160, 161
open loop 1, 42, 45, 53
PFD/CP linearity 2, 45, 47, 49, 52
phase-domain model 2, 45, 46, 47, 50,
53
phase error 16, 35, 78, 105, 157
phase margin 21
phase noise 15, 27, 41
phase-frequency detector 16, 28, 71, 135, 65
phase-locked loop 15, 27, 67, 131
pipelined adder 93
PMOS 74, 75, 79, 82, 86
Index
power amplifier 10, 133
power spectral density 29, 38, 50, 55, 149
process tolerances 117
pseudorandom binary sequence 165
QPSK system 42
quadrature-phase signals 86
quantization noise 50, 51, 55, 64, 65,
132, 133, 172
rms phase error 41
range coverage 7
receiver ix, 1, 10, 11, 12, 13, 42, 70, 102,
105, 107, 131
reference frequency 50, 53, 60, 71, 77,
78, 99, 107, 140, 165, 176
rejection ratio 13
RF front-end circuits 13
RFIC transceivers 7
sampling frequency 31, 34, 35, 39, 40,
71, 125, 165
short-channel transistors 154
single-sideband phase noise 158, 163
single subcarrier 10
slew rate 118
spectral densities 52, 99
spurious performance x, 3
spurious signals 35, 57, 163
substrate noise rejection 18
superimposed noise vectors 162
tank amplitude 149, 150, 152, 153
time to digital converter xii, 134
time domain 26, 36, 55, 90
transceiver 1, 7, 69, 102, 109, 131
transfer functions 1
transmitter ix, 1, 5, 12, 13, 14, 70, 102,
105, 107, 131, 133, 176
tunable varactors 86
tuning curves 51, 88
tuning voltage 18, 49, 122, 140
unlicensed band 10
upconverted differential signal 12
variable-gain amplifiers 10
VCO 18, 40, 86, 132, 162, 201
wireless cellular devices 7
wireless LAN 7, 8, 10, 11, 13, 39, 45, 69,
70, 88, 107, 111, 127, 131, 132
wireless local area networks 1, 7
'6 36, 51, 69, 90, 113, 128, 169
'6:modulators 50

CMOS Single Chip Fast Frequency Hopping Synthesizers For Wireless Multi-Gigahertz Applications

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CMOS SINGLE CHIP FAST FREQUENCY

HOPPING SYNTHESIZERS FOR WIRELESS

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES

CMOS Single Chip Fast Frequency

Printed on acid-free paper

All Rights Reserved

4 SYSTEM SIMULATION OF '6-BASED FRACTIONAL-N

5 MULTIMODE '6-BASED FRACTIONAL-N FREQUENCY

5.4.2.3 DC Offset Current

7 CONCLUSION AND FURTHER WORK

Calculation of Global Phase Error From L(f)

Frequency synthesizers are at the heart of the each transmitter/receiver

excellent phase noise and spurious performance can be achieved while

Absolute Tolerance (CadenceTM specific)

Single-Sideband Phase Noise

Relative Tolerance (Cadence specific)

Frequency synthesizers are used as local oscillators in all transceiver

frequency synthesizers. Both synthesizers are incorporated in a

5. T. Bourdi, A. Borjak, and I. Kale, A Novel DeltaSigma Based RF

Figure 2-1. WLAN Usage

THE WLAN STANDARDS

As mentioned above the WLAN standards fall in two frequency

Wireless Communication Systems

Figure 2-2. Nonoverlapping and Overlapping US Channel Selection

WLAN TRANSCEIVER SYSTEMS

A basic diagram of a transceiver system used in the WLAN standards

Wireless Communication Systems

Figure 2-4. Transceiver System

Figure 2-5. WLAN Transceiver Architecture

(PA), and frequency synthesizers acting as local oscillators (LO). In

A detailed transmitter chain block diagram is shown in Figure 2-6.

Figure 2-6. Transmitter Signal Path for the WLAN Transceiver

Wireless Communication Systems

more severe adjacent channel rejection requirement, higher rejection

Figure 2-7. Receiver Chain for WLAN Transceiver

Included in the receiver is a low-flicker noise mixer [3], active-LC

The Frequency Synthesizer (Local Oscillator)

In a direct conversion transceiver, the required local oscillation (LO)

Figure 2-8. Local Oscillator Frequency Synthesizer For WLAN Transceiver

The quadrature LO signals for 2 GHz band are then generated by

In this chapter, detailed analyses of PLL frequency synthesizers are

PHASE-LOCKED LOOP FREQUENCY

A PLL frequency synthesizer is a circuit that faithfully follows and

Figure 3-1. Phase-Locked Loop Frequency Synthesizer

Phase-Locked Loop Main Blocks

Phase-Locked Loop Frequency Synthesizers

Figure 3-2. Conventional Dual-Type DFF Phase-Frequency Detector

Figure 3-3. Phase-Frequency Detector Timing Diagram

The CP is used to convert the PFD output signal voltage to a current

capacitive elements. The loop filter is usually of second order.

Figure 3-4. Illustration of Sourcing and Sinking in Charge Pump

The VCO converts a continuous input voltage to a high-frequency

Phase-Locked Loop Frequency Synthesizers

Voltage-Controlled Crystal Oscillator

The crystal oscillator is used to generate the reference signal. Crystal

PHASE-LOCKED LOOP PARAMETERS

PLLs are of nonlinear nature. To simplify their analyses, a linear

Kd is equal to 1. The CP current ICP is in amps. The VCO gain KVCO is

A typical passive loop filter is a second-order filter that yields a

The loop bandwidth (LBW) frequency fp (radial frequency is Zp) is

The phase margin is defined in the following equation:

I 180  phase( AOpenLoop ( s ))

Loop Filter Design

4 SYSTEM SIMULATION OF '6-BASED FRACTIONAL-N

I 180 phase( AOpenLoop ( s ))

Figure 3-15. Typical DeltaSigma ('6-Based Fractional-N Frequency Synthesizer

'6 Modulators in Frequency Synthesizers

Figure 3-16. A Third- Order MASH1-1-1 '6 Modulator Block Diagram

)]2( Norder 1)

Figure 3-17. Time-Domain Output of MASH1-1-1 '6 Modulator

In this section, a case study is presented for a '6-based frequency

Table 3-5. '6 PLL Parameters Used

Figure 3-19. Phase Noise Contributions of SubBlocks in '6-Based Fractional-N Synthesizer