Name:

Student ID Number:
Section: 01/02/03/04/05 A/B
Lecturer: Dr Jamaludin / Dr Azni Wati
/ Dr Fazrena Azlee

College of Engineering

Department of Electronics and Communication Engineering

Test 2
SEMESTER 1, ACADEMIC YEAR 2012/2013

Subject Code
Course Title
Date
Time Allowed

:
:
:
:

EEEB273
Electronics Analysis & Design II
3 August 2012
1.5 hours

Instructions to the candidates:

1.
2.
3.
4.
5.
6.

Write your Name and Student ID number. Circle your section number.
Write all your answers using pen. DO NOT USE PENCIL except for the diagram.
ANSWER ALL QUESTIONS.
WRITE YOUR ANSWER ON THIS QUESTION PAPER.
For BJT, use VT = 26 mV where appropriate.
Use at least 4 significant numbers in all calculations.

NOTE: DO NOT OPEN THE QUESTION PAPER UNTIL INSTRUCTED TO DO SO.

GOOD LUCK!
Question No.
Marks

Total

EEEB273

Question 1

Semester 1, 2012/2013

Test 2

[40 marks]

The circuit parameters for the differential amplifier shown in Figure 1 are V+ = 5 V, V = 5 V, Acm
= 0.28, and IQ = 240 A. The NMOS transistor parameters are VTN = 0.4 V, kn = 100 A/V2,
(W/L)n = 8, and n = 0.018 V-1. The PMOS transistor parameters are VTP = 0.4 V, kp = 40 A/V2,
(W/L)p = 10, and p = 0.02 V-1.
a)

Determine the maximum common-mode voltage input, vcm(max), that can be applied
such that the transistors are still biased in saturation region.
[6 marks]

b)

Draw the ac equivalent circuit for the differential-mode input (v1 = +vd/2 and v2 = vd/2).
Indicate the resultant ac currents in all transistors.
[6 marks]

c)

Determine the output resistance Ro of the differential amplifier.

[5 marks]

d)

Calculate the small-signal differential-mode voltage gain Ad = vo/vd.

[5 marks]

e)

Suggest one way to increase the differential-mode voltage gain and show your new circuit
and justify the change(s).
[6 marks]

f)

Find the one-sided output voltage (vo) taken at vD2 of the differential amplifier when v1 =
(0.10 + 0.05 sin t) mV and v2 = (
0.10 + 0.05 sin t) mV.
[12 marks]

Figure 1

EEEB273

Semester 1, 2012/2013

Test 2

Answers for Question 1

(a)

VSG3

= [
(ID3/Kn)] - VTP
= [
(IQ/2)/[( kp /2)(W/L)p]] - VTP

= [
(120
)/[(40
/2)(10)]] + 0.4
= 1.175 V
vcm(max) = V+ - VSG3 - VDS1(sat) + VGS1
= V+ - VSG3 - (VGS1 - VTN) + VGS1 = V+-VSG3 + VTN

= 5 - 1.175 + 0.4
= 4.225 V

(b)

1/2

1/2

1
1/2

1/2

1/2

1/2

EEEB273

Semester 1, 2012/2013

Test 2

Answers for Question 1 (Cont.)

(c)

(d)

ro2

= 1/(nID) = [(0.018)(120
)]-1 = 463 k

ro4

=1/(pID) = [(0.02)(120
)]-1 = 416.7 k

Ro

= ro2||ro4 = 219.3 k

Ro

= ro2||ro4 = 219.3 k

gm

= 2
[KnID] = 2 [( kn /2)(W/L)n(IQ/2)]

(e)

=2 [( 100
/2)(8)(120
)] = 0.4382 mA/V
Ad

2
2

= gmRo = (0.4382m)(219.3k) = 96.09

Increase voltage gain by using cascode active load.

A d = gm R o
Previous Ro = ro2||ro4

New circuit Ro = ro2||Ro(active load) = ro2||gmro4 ro6

The new Ro is larger than the previous one.

ro2

2
-transistor type PMOS
-within cascode connections
-connection with diff-amp

EEEB273

Semester 1, 2012/2013

Test 2

Answers for Question 1 (Cont.)

(f)

vd

= v 1 - v2

= (0.10 +0.05 sin t) - (

0.10 +0.05 sin t)
= 0.20 mV
vcm

= (v1 + v2)/2

1
1

= [(0.10 +0.05 sin t) + (

0.10 +0.05 sin t)]/2
= 0.05 sin t mV
vO

= Advd + Acmvcm

= (96.09)(0.2mV) + (-0.28)(0.05 sin t mV)

= (19.22 0.014 sin t) mV

EEEB273

Question 2

Semester 1, 2012/2013

Test 2

[30 marks]

Figure 3
For a simplified class-AB output stage with BJTs in Figure 3, given that VCC = 5 V and RL = 1 k .
For each transistor, the reverse-bias saturation current is IS = 2 x 10-15 A.
a)

What are two disadvantages of class-AB output stage compared to the class-B output
stage?
[4 marks]

b)

What is the advantage of class-AB output stage compared to the class-B output stage?
[2 marks]

c)

Determine the value of VBB that produces iCn = iCp = 1.1 mA when vI = 0 V. What is the
power dissipated in each transistor?
[6 marks]

d)

For vO = -3.6 V, determine iL, iCn, iCp, and vI. Reiterate your calculation twice for iCn and
iCp. What is the power dissipated in Qn, Qp, and RL?
[18 marks]

Answers for Question 2

a) i) Required power handling capability of Qs in class-AB will be slightly larger than class-B.
ii) Power Conversion Efficiency ( ) will be less than class-B.
[2 marks for each answer]
b) Eliminating crossover distortion in the class-B.

[2 marks]

EEEB273

Semester 1, 2012/2013

Test 2

Answers for Question 2 (Cont.)

c)

iCn
VBEn
VBB
PQ

d)

= IS exp(VBEn / VT )
= VT ln(iCn / IS)
= (0.026) ln (1.1x10-3 / 2x10-15) = 0.70286 V
= 2 VBE
= 2 x 0.70286 = 1.40572 V

[1]
[0.5, 0.5]
[1]
[0.5, 0.5]

= iCn vCE
= (1.1m)(5V 0V) = 5.5 mW

[1]
[0.5, 0.5]

For vO = -3.6 V,

iL

= vO / RL
= (-3.6V)/(1 k ) = -3.6 mA

[1]
[0.5, 0.5]

Approximation:

iCp
vEBp

| iL | = 3.6 mA
= VT ln(iCp / IS)
= (0.026) ln(3.6x10-3 / 2x10-15) = 0.73369 V
= VBB - vEBp
= 1.40572 0.73369 = 0.67203 V
= IS exp(VBEn / VT )
= (2x10-15) exp(0.67203 / 0.026) = 0.336026 mA

[1]
[0.5]
[0.5]
[1]
[0.5]
[1]
[0.5]

iCn - iL
= (0.336026m) - (-3.6m) = 3.936026 mA
= VT ln(iCp / IS)
= (0.026) ln(3.936026x10-3 / 2x10-15) = 0.73601 V
= VBB - vEBp
= 1.40572 0.73601 = 0.66971 V
= IS exp(VBEn / VT )
= (2x10-15) exp(0.66971 / 0.026) = 0.307341 mA
= iCn - iL
= (0.307341m) - (-3.6m) = 3.907341 mA

[1]
[0.5]

vBEn
iCn
Then, finally

iCp
vEBp
vBEn
iCn
iCp

[0.5]
[0.5]
[0.5]
[0.5]

vI

= vO - vEBp + VBB/2
= (-3.6) - 0.73601 + 1.40572/2 = -3.63315 V

[1]
[0.5]

Power:
For Qn:

PQn

= iCn vCEn
= (0.307341m)(5-(-3.6)) = 2.643 mW

[1]
[0.5, 0.5]

For Qp:

PQp

= iCp vECp
= (3.907341m)(-3.6-(-5)) = 5.470 mW

[1]
[0.5, 0.5]

For RL:

PRL

= i2L RL
= (-3.6 mA) 2(1 k ) = 12.96 mW

[1]
[0.5, 0.5]

EEEB273

Question 3

Semester 1, 2012/2013

Test 2

[30 marks]

Figure 3
Refer to Figure 3. It is given that IQ = IR4 = IR6 = 0.4 mA, and IR7 = 2 mA. Neglect base currents
and assume VBE(on) = 0.7 V for all transistors except Q8 and Q9 in the Widlar circuit.

a)

List all transistors and resistors forming the biasing stage of the circuit in the Figure 3?
[3 marks]

b)

Calculate the common-mode input range. State your assumptions.

c)

Calculate overall gain of the circuit. Assume

the Darlington Pair can be calculated using

= 100 and VA = . It is given that the gain of

[18 marks]

AV 2 =

d)

[7 marks]

I R4
2VT

(R5 || Ri 3 )

Comment on the loading effect of the output stage onto the gain stage.

[2 marks]

EEEB273

Semester 1, 2012/2013

Test 2

Answers for Question 3

a)

b)

Q7, R1, Q8, R2, Q9 and R3.

[0.5 mark each]

Vcm(max) = VC1, assume VCE(min) = VBE(on)

VC1 = V+ - IC1 RC = 10 - (0.2m)(20k) = 6 V

[1]
[2]

Vcm(min) = V- + VBE1 + VBE8

assume neglect VR2
Vcm(min) = -10 + 0.7 + 0.7 = -8.6 V

[2]
[0.5]
[1.5]

c)
Ad = Ad 1 . Av 2 . Av 3 =

vo 2
v
v
. o3 . o
v1 v 2 vo 2 vo 3

Vo 2
g
= m (RC Ri 2 )
vd
2

Ad 1 =

Ri 2 = r 3 + (1 + )r 4

r 4 = VT / I R 4 = (100)(0.026) / 0.4 m = 6.5k

r 3 2VT / I R 4 = (100) 2 (0.026) / 0.4 m = 650k
Ri 2 = 650k + (101)(6.5k ) = 1307 k
g m = I Q /(2VT ) = 0.4 m /( 2 0.026) = 7.70mA/V

[2]
[2]
[2]
[0.5]
[1.5]
[0.5]

Ad 1 = (7.70m/2)(20k || 1307k) = 75.8

[0.5]
[1]

Ri 3 = r 5 + (1 + )[R6 + r 6 + (1 + )R7 ]

[2]

r 5 = VT / I R 6 = (100)(0.026) / 0.4 m = 6.5k

[0.5]
[0.5]
Ri 3 = 6.5k + (1 + 100 )[16.5k + 1.3k + (1 + 100 )5k ] = 52.8M [1]

r 6 = VT / I R 7 = (100)(0.026) / 2 m = 1.3k
Av 2 =

d)

I R4
(R5 Ri 3 ) = 0.4m (5k 52.8M ) = 38.5
2VT
2(0.026)

[1]

Av 3 1

[1]

Ad = (75.8)(38.5)(1) = 2918

[2]

Since Ri3 >> R5, the output stage does not load down the gain stage

[2]

EEEB273

Semester 1, 2012/2013

Test 2

Appendix: BASIC FORMULA

BJT

MOSFET

iC = I S e v BE / VT ; npn

; N MOSFET
vDS (sat) = vGS VTN

iC = I S e v EB / VT ; pnp
iC = i E = i B

iD = K n [vGS VTN ]2

i E = i B + iC

k n' W
Kn =
2 L
; P MOSFET

+1

; Small signal
= g m r
r =

VT

gm =

I CQ
I CQ
VT

V
ro = A
I CQ

vSD (sat) = vSG + VTP

iD = K p [vSG + VTP ]2
k p' W
Kp =
2 L
; Small signal

g m = 2 K n (VGSQ VTN ) = 2 K n I DQ

ro

1
I DQ