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TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
TPS54560-Q1 4.5-V to 60-V Input, 5-A, Step-Down DC-DC Converter With Eco-Mode
1 Features
3 Description
PACKAGE
TPS54560-Q1
SO PowerPAD (8)
3.90 mm x 4.89 mm
2 Applications
VIN
BOOT
90
80
TPS54560-Q1
SW
COMP
70
VOUT
Efficiency (%)
EN
60
50
40
30
RT/CLK
FB
GND
20
VSeries1
IN = 12 V
VSeries2
IN = 36 V
VSeries4
IN = 60 V
10
0
0
0.5
1.5
2.5
3.5
4.5
5.5
C024
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
34
34
34
35
37
37
37
37
4 Revision History
Changes from Original (September 2013) to Revision A
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
TPS54560-Q1
www.ti.com
SW
GND
COMP
FB
BOOT
VIN
EN
RT/CLK
Thermal
Pad
9
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BOOT
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the output is switched off until the capacitor is
refreshed.
VIN
EN
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal
amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB
COMP
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
GND
Ground
SW
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal
Pad
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
0.3
65
EN
0.3
8.4
BOOT
Input voltage
73
FB
0.3
COMP
0.3
RT/CLK
0.3
3.6
BOOT-SW
Output voltage
UNIT
SW
0.6
65
65
40
150
65
150
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrostatic discharge
2000
500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
MAX
4.5
60
UNIT
V
40
150
DDA
UNIT
8 PINS
RJA
42.0
RJC(top)
45.8
RJB
23.4
JT
5.9
JB
23.4
RJC(bot)
3.6
(1)
(2)
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13mil) located under the device package
TPS54560-Q1
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6.5
Electrical Characteristics
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
4.3
4.48
4.5
Rising
4.1
325
mV
2.25
4.5
FB = 0.9 V, TA = 25C
146
175
1.2
1.3
4.6
Enable threshold 50 mV
Hysteresis current
Enable to COMP active
1.1
1.2
-1.8
2.2
3.4
-4.5
VIN = 12 V, TA = 25C
V
A
A
540
2.1
ms
Soft-Start Time
0.42
ms
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
92
190
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gM)
VFB = 0.8 V
50
nA
350
Mhos
77
Mhos
10,000
V/V
2500
kHz
30
17
A/V
CURRENT LIMIT
6.3
7.5
8.8
6.3
7.5
8.3
7.1
7.5
7.9
(1)
60
ns
176
12
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
fSW
Switching frequency
100
RT = 200 k
450
160
kHz
550
kHz
2300
kHz
15
1.55
(1)
2500
500
0.5
ns
2
1.2
55
ns
78
Open-loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
0.25
0.2
0.15
0.1
0.05
BOOT-SW = 3 V
0.809
0.804
0.799
0.794
0.789
BOOT-SW = 6 V
0
0.784
50
25
25
50
75
100
125
8.5
8.5
7.5
7
6.5
50
75
100
125
150
C026
40
C
Series1
25
C
Series2
150
C
Series4
8
7.5
7
6.5
6
50
25
25
50
75
100
125
150
10
20
540
450
500
520
510
500
490
480
470
460
450
40
50
60
C028
550
530
30
C027
25
400
350
300
250
200
150
100
50
0
50
25
25
50
75
100
125
150
200
300
400
500
600
700
RT/CLK - Resistance (k )
C029
25
C025
50
150
800
900
1000
C030
TPS54560-Q1
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2300
450
2100
1900
400
gm (A/V)
2500
1700
1500
1300
300
1100
900
250
700
500
200
0
50
100
150
50
200
RT/CLK - Resistance (k )
EN - Threshold (V)
100
gm (A/V)
80
70
60
50
40
30
20
25
25
50
75
100
125
25
50
75
100
125
150
C032
110
90
120
50
25
C031
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
50
150
25
25
50
75
100
125
C033
150
C034
3.5
0.5
3.7
0.7
3.9
0.9
4.1
1.1
4.3
1.3
IEN (A)
IEN (uA)
350
4.5
4.7
1.5
1.7
4.9
1.9
5.1
2.1
5.3
2.3
5.5
2.5
50
25
25
50
75
100
125
150
50
25
25
50
75
100
C035
125
150
C036
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
2.5
2.7
IEN - Hysteresis (A)
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
VSENSE
Rising
Series4
75
50
25
4.5
50
25
25
50
75
100
125
0.0
150
0.3
2.5
2.5
1.5
0.4
0.5
0.6
0.7
0.8
C038
IVIN (A)
IVIN (A)
0.2
VSENSE (V)
1.5
0.5
0.5
0
50
25
25
50
75
100
125
150
10
190
190
170
170
IVIN (A)
210
130
40
50
60
C040
150
130
110
110
90
90
70
30
210
150
20
C039
IVIN (A)
0.1
C037
70
50
25
25
50
75
100
125
150
10
20
30
40
C041
Series2
VSENSE
Falling
50
60
C042
TPS54560-Q1
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4.3
2.3
4.2
2.2
4.1
2.1
4.0
2.0
3.9
1.9
3.8
3.7
1.8
50
25
25
50
75
100
125
50
150
5.5
5.4
5.3
5.2
VIN (V)
5.6
75
100
125
150
C044
Start
Stop
5.1
4.9
4.8
4.7
4.6
Dropout
Voltage
Dropout
Voltage
2500
2300
2100
1900
1700
1500
1300
1100
900
700
500
300
100
0.05
0.1
0.15
0.2
0.25
0.3
C045
50
25
10
25
C043
4.4
VIN (V)
VI - BOOT-PH (V)
4.5
0.35
0.4
0.45
0.5
C046
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
7 Detailed Description
7.1 Overview
The TPS54560-Q1 is a 60-V, 5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop
(PLL) connected to the RT/CLK pin that will synchronize the power switch turn on to a falling edge of an external
clock signal.
The TPS54560-Q1 has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to adjust
the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current
source enables operation when the EN pin is floating. The operating current is 146 A under no load condition
(not switching). When the device is disabled, the supply current is 2 A.
The integrated 92-m, high-side MOSFET supports high efficiency power supply designs capable of delivering 5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54560-Q1 reduces the external
component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a
UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54560-Q1 to operate at high duty cycles
approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the
application. The minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The TPS54560-Q1 includes an internal soft-start circuit that slows the output rise time during start-up to reduce
in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
10
TPS54560-Q1
www.ti.com
VIN
Shutdown
OV
Thermal
Shutdown
UVLO
Enable
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Current
Sense
PWM
Comparator
FB
BOOT
Logic
Shutdown
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
GND
Oscillator
with PLL
POWERPAD
RT/ CLK
11
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
TPS54560-Q1
www.ti.com
0.8 V
(2)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54560-Q1 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54560-Q1 is disabled when the VIN pin voltage falls below 4 V or when the
EN pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 A that enables
operation of the TPS54560-Q1 when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 A of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4
A Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute
maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using
the EN resistors, the EN pin is clamped internally with a 5.8 V zener diode that will sink up to 150 A.
13
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
TPS54560-Q1
i1
VIN
ihys
RUVLO1
RUVLO1
EN
EN
10 kW
Node
VEN
RUVLO2
RUVLO2
5.8 V
- VSTOP
V
RUVLO1 = START
IHYS
(3)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1
(4)
14
101756
RT (kW)1.008
(7)
TPS54560-Q1
www.ti.com
CLPeak
tON
Figure 25. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54560-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB
pin voltage falls from 0.8 V to 0 V. The TPS54560-Q1 uses a digital frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the
inductor current can exceed the peak current limit because of the high input voltage and the minimum
controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases
slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the
period of the switching cycle providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 9 calculates the maximum switching frequency at which
the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency
should not exceed the calculated value.
Equation 8 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
15
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
(8)
(9)
fSW(shift) =
1
tON
IO
Output current
ICL
Current limit
Rdc
inductor resistance
VIN
VOUT
output voltage
VOUTSC
Vd
RDS(on)
switch on resistance
tON
controllable on time
DIV
16
TPS54560-Q1
www.ti.com
TPS54560-Q1
RT/CLK
RT/CLK
PLL
PLL
RT
Hi-Z
Clock
Source
Clock
Source
RT
SW
SW
EXT
EXT
IL
IL
SW
EXT
IL
17
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
VO
Power Stage
gmps 17 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
C2
RO
FB
COUT
gmea
350 mA/V
R2
C1
18
TPS54560-Q1
www.ti.com
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 31. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
s
1 +
2p fZ
VOUT
= Adc
VC
s
1 +
2p fP
(10)
Adc = gmps RL
(11)
1
fP =
COUT RL 2p
(12)
1
fZ =
COUT RESR 2p
(13)
19
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Aol
A0
P1
Z1
P2
A1
BW
Figure 33. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
gmea
=
2p BW (Hz)
Ro =
CO
(14)
(15)
s
1 +
2
p
f
Z1
EA = A0
s
s
1 +
1 +
2p fP1
2p fP2
A0 = gmea
A1 = gmea
20
R2
Ro
R1 + R2
R2
Ro| | R3
R1 + R2
(16)
(17)
(18)
TPS54560-Q1
www.ti.com
Z1 =
P2 =
1
2p Ro C1
(19)
1
2p R3 C1
(20)
1
2p R3 | | RO (C2 + CO )
type 2a
(21)
1
P2 =
type 2b
2p R3 | | RO CO
P2 =
2p R O
(22)
1
type 1
(C2 + C O )
(23)
21
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
VIN
+
Cin
Cboot
Lo
BOOT
VIN
Cd
GND
SW
R1
+
GND
TPS54560-Q1
Co
R2
FB
VOUT
EN
COMP
Rcomp
RT/CLK
Czero
RT
Cpole
Figure 34. TPS54560-Q1 Inverting Power Supply from SLVA317 Application Note
7.4.3.2 Split-Rail Power Supply
Another use of the TPS54561-Q1 device is to convert a positive input voltage to a split-rail positive- and
negative-output voltage by using a coupled inductor. Ideal applications are amplifiers requiring a split-rail
positive- and negative-voltage power supply. For a more-detailed example, see Creating a Split-Rail Power
Supply With a Wide Input Voltage Buck Regulator, application report SLVA369.
VOPOS
+
VIN
Copos
+
Cin
Cboot
BOOT
VIN
GND
SW
Lo
Cd
R1
GND
Coneg
R2
TPS54560-Q1
VONEG
FB
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Figure 35. TPS54560-Q1 Split Rail Power Supply based on the SLVA369 Application Note
22
TPS54560-Q1
www.ti.com
5V, 5A VOUT
C4 0.1uF
U1
TPS54560-Q1 (DDA)
7V to 60V
2
3
C10
2.2uF
C3
2.2uF
C1
2.2uF
C2
2.2uF
R1
442k
SW
BOOT
VIN
GND
EN
COMP
RT/CLK
PWRPD
VIN
FB
C6
C7
C9
47uF
47uF
47uF
R5
53.6k
7
6
5
FB
FB
R4
16.9k
R2
90.9k
D1
B560C
R3
243k
C8
R6
10.2k
47pF
C5
4700pF
UNIT
Output Voltage
5V
VOUT = 4 %
5A
Input Voltage
12 V nom. 7 V to 60 V
0.5% of VOUT
6.5 V
5V
23
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
(25)
(26)
TPS54560-Q1
www.ti.com
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54560-Q1 which is nominally 7.5 A.
VIN(max ) - VOUT
VOUT
60 V - 5 V
5V
= 7.6 mH
LO(min ) =
IOUT KIND
VIN(max ) fSW
5 A x 0.3
60 V 400 kHz
(27)
spacer
IRIPPLE =
5 V x (60 V - 5 V)
= 1.591 A
60 V x 7.2 mH x 400 kHz
(28)
spacer
12
VIN(max ) LO fSW
(5 A )
5 V (60 V - 5 V )
1
+
=5A
60 V 7.2 mH 400 kHz
12
(29)
spacer
IL(peak ) = IOUT +
IRIPPLE
1.591 A
= 5A +
= 5.797 A
2
2
(30)
25
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
Equation 33 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where sw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 33 yields 19.9 F.
Equation 34 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 34 indicates the ESR should be less than 15.7 m.
The most stringent criteria for the output capacitor is 62.5 F required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 3 x
47 F, 10 V ceramic capacitors with 5 m of ESR will be used. The derated capacitance is 87.4 F, well above
the minimum required capacitance of 62.5 F.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 35 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 35 yields 459 mA.
2 DIOUT
2 2.5 A
COUT >
=
= 62.5 mF
fSW DVOUT 400 kHz x 0.2 V
(31)
OH
COUT > LO
OL
1
1
1
1
=
= 19.9 mF
x
8 fSW VORIPPLE 8 x 400 kHz
25 mV
1.591 A
IRIPPLE
V
25 mV
RESR < ORIPPLE =
= 15.7 mW
IRIPPLE
1.591 A
(32)
COUT >
ICOUT(rms) =
)=
12 VIN(max ) LO fSW
5V
(60 V
- 5 V)
(33)
(34)
= 459 mA
(35)
TPS54560-Q1
www.ti.com
PD =
(V
IN(max ) - VOUT
) I
OUT
VIN(max )
(60 V
Vf d
- 5 V ) 5 A x 0.7 V
60 V
C j fSW (VIN + Vf d)
=
2
(36)
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 5A
5V
7V
(7 V
- 5 V)
7V
= 2.26 A
(37)
I
0.25
5 A 0.25
DVIN = OUT
=
= 355 mV
CIN fSW
8.8 mF 400 kHz
(38)
VALUE (F)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
100 V
Submit Documentation Feedback
27
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
VENA
1.2 V
=
= 90.9 kW
RUVLO2 =
VSTART - VENA
6.5 V - 1.2 V
+
m
1.2
A
+ I1
442 kW
RUVLO1
(40)
(41)
8.2.2.9 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, p(mod), and the ESR zero, z1 must be calculated using Equation 42 and
Equation 43. For COUT, use a derated value of 87.4 F. Use equations Equation 44 and Equation 45 to estimate
a starting point for the crossover frequency, co. For the example design, p(mod) is 1821 Hz and z(mod) is 1100
kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of
modulator pole and half of the switching frequency. Equation 44 yields 44.6 kHz and Equation 45 gives 19.1 kHz.
Use the geometric mean value of Equation 44 and Equation 45 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
5A
fP(mod) =
=
= 1821 Hz
2 p VOUT COUT 2 p 5 V 87.4 mF
(42)
f Z(mod) =
28
1
1
=
= 1100 kHz
2 p RESR COUT
2 p 1.67 mW 87.4 mF
(43)
TPS54560-Q1
www.ti.com
fco1 =
fp(mod) x f z(mod) =
fco2 =
fp(mod) x
fSW
2
1821 Hz x
400 kHz
2
= 44.6 kHz
(44)
= 19.1 kHz
(45)
To determine the compensation resistor, R4, use Equation 46. Assume the power stage transconductance,
gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 A/V, respectively. R4 is calculated to be 16.8 k and a standard value of 16.9 k is selected.
Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 5172 pF for
compensating capacitor C5. 4700 pF is used for this design.
VOUT
2 p fco COUT
5V
2 p 29.2 kHz 87.4 mF
R4 =
x
=
x
= 16.8 kW
gmps
17 A / V
0.8 V x 350 mA / V
VREF x gmea
(46)
C5 =
1
1
=
= 5172 pF
2 p R4 x fp(mod)
2 p 16.9 kW x 1821 Hz
(47)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 48 and Equation 49 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
87.4 mF x 1.67 mW
=
= 8.64 pF
C8 = OUT
R4
16.9 kW
(48)
1
1
C8 =
=
= 47.1 pF
R4 x f sw x p
16.9 kW x 400 kHz x p
(49)
8.2.2.10 Discontinuous Conduction Mode and Eco-Mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 408 mA. The power supply enters Eco-Mode when the output current is lower than 25.3 mA. The
input current draw is 257 A with no load.
8.2.3 Application Curves
1 A/div
10 V/div
Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
VIN
10 mV/div
200 mV/div
IOUT
VOUT 5V offset
VOUT 5V offset
Time = 4 ms/div
29
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
2 V/div
EN
4 V/div
4 V/div
VIN
VIN
1 V/div
5 V/div
5 V/div
Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
VOUT
EN
VOUT
Time = 2 ms/div
Time = 2 ms/div
10 V/div
500 mA/div
IL
SW
IL
10 mV/div
10 mV/div
1 A/div
10 V/div
SW
VOUT AC Coupled
VOUT AC Coupled
Time = 4 Ps/div
Time = 4 Ps/div
10 V/div
1 m\A/div
IL
200 mV/div
10 V/div
IL
10 mV/div
200 mA/div
SW
SW
VOUT AC Coupled
VIN AC Coupled
Time = 1 ms/div
Time = 4 Ps/div
30
TPS54560-Q1
www.ti.com
Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
10 V/div
2 V/div
SW
SW
IL
VOUT
20 mV/div
10 mV/div
200 mA/div
500 mA/div
IL
VIN AC Coupled
Time = 4 Ps/div
Time = 40 Ps/div
IOUT = 1 A
EN Floating
2 V/div
2 V/div
IOUT = 100 mA
EN Floating
VIN
VIN
VOUT
VOUT
Time = 40 ms/div
Figure 48. Low Dropout Operation
Time = 40 ms/div
Figure 47. Low Dropout Operation
100
100
90
95
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
60
50
40
30
70
20
VIN =Series4
7V
VIN =36V
36 V
65
60
0
0.5
1.5
VIN =12V
12 V
VIN =24V
24 V
VIN =48V
48 V
VIN =60V
60 V
2.5
3.5
4.5
10
5
0
0.001
0.00
C024
VIN =7V
7V
VIN =36V
36 V
0.01
VIN =12V
12 V
VIN = 48V
48 V
24VV
VIN = 24
VIN = 60
60VV
0.10
C024
1.00
31
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
Measurements are taken with standard EVM using a 12V input, 5V output, and 5A load unless otherwise noted.
100
100
95
90
80
70
Efficiency (%)
85
80
75
60
50
VIN = 6V
6V
VIN =12V
12 V
VIN =24v
24 V
VIN =36v
36 V
VIN =48V
48 V
VIN =60V
60 V
40
30
70
20
VIN =6V
6V
VIN =36V
36 V
65
60
0
0.5
1.5
2.5
VIN =12V
12 V
VIN =24V
24 V
VIN =48V
48 V
VIN =60V
60 V
3.5
4.5
10
0
0.001
0.00
0.01
1.00
C024
100
Gain (dB)
85
80
75
VIN 18in
= 18 V
VINSeries1
= 24 V
VINSeries3
= 36 V
VINSeries6
= 48 V
VINSeries8
= 60 V
70
65
60
0.5
1.5
2.5
3.5
4.5
120
30
90
20
60
10
30
10
30
20
60
30
90
VIN = 12 V
VOUT = 5 V
IOUT = 5 A
40
50
120
150
60
180
10
150
Phase
40
90
180
Gain
50
95
Efficiency (%)
0.10
C024
Phase ()
Efficiency (%)
90
100
1k
10k
100k
1M
Frequency (Hz)
C024
C001
0.3
Output Voltage Normalized (%)
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.2
0.1
0.0
0.1
0.2
0.5
0.6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
5.0
0.3
5
10
15
20
25
30
35
40
45
50
C024
32
4.5
55
60
C024
TPS54560-Q1
www.ti.com
33
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the VIN pin, and the A node of the catch diode. See Figure 57 for a PCB
layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.
The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The
SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection
is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area
of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top
side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT
resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional
external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Output
Inductor
BOOT
Catch
Diode
SW
VIN
GND
EN
COMP
RT / CLK
FB
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
34
TPS54560-Q1
www.ti.com
5V
2
PCOND = (IOUT ) RDS(on ) OUT = 5 A 2 92 mW
= 0.958 W
12 V
VIN
(50)
spacer
PSW = VIN fSW IOUT trise = 12 V 400 kHz 5 A 4.9 ns = 0.118 W
(51)
spacer
PGD = VIN QG fSW = 12 V 3nC 400 kHz = 0.014 W
(52)
spacer
PQ = VIN IQ = 12 V 146 mA = 0.0018 W
(53)
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET ().
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W
(54)
(55)
(56)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (C).
TJ is the junction temperature (C).
RTH is the thermal resistance of the package (C/W).
TJMAX is maximum junction temperature (C).
TAMAX is maximum ambient temperature (C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
35
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
90
90
80
80
70
70
60
60
TA (C)
TA (C)
50
6V
12 V
24 V
36 V
48 V
60 V
40
30
20
0.0
0.5
50
8V
12 V
24 V
36 V
48 V
60 V
40
30
20
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
IOUT (Amps)
5.0
0.0
0.5
1.0
80
80
70
70
60
60
TA (C)
TA (C)
90
50
18 V
24 V
36 V
48 V
60 V
20
0.0
0.5
1.0
3.0
3.5
4.0
4.5
5.0
C048
50
400 LFM
40
200 LFM
100 LFM
30
Nat Conv
20
1.5
2.0
2.5
3.0
3.5
IOUT (Amps)
4.0
4.5
5.0
0.0
0.5
C048
36
2.5
90
30
2.0
IOUT (Amps)
40
1.5
C047
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT (Amps)
4.5
5.0
C048
TPS54560-Q1
www.ti.com
11.2 Trademarks
Eco-Mode, PowerPAD are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
37
TPS54560-Q1
SLVSBZ0A SEPTEMBER 2013 REVISED DECEMBER 2014
www.ti.com
38
www.ti.com
4-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TPS54560QDDAQ1
ACTIVE SO PowerPAD
DDA
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54560Q
TPS54560QDDARQ1
ACTIVE SO PowerPAD
DDA
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54560Q
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
4-Nov-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54560-Q1 :
Catalog: TPS54560
NOTE: Qualified Version Definitions:
Addendum-Page 2
4-Nov-2014
Device
TPS54560QDDARQ1
DDA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
4-Nov-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54560QDDARQ1
SO PowerPAD
DDA
2500
366.0
364.0
50.0
Pack Materials-Page 2
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