ALU tutorial using XILINX

1.0 Introduction
This is a step-by-step tutorial for building a full adder in Xilinx Vivado
By the end of this tutorial, you should be able to:
Create a new design using Verilog.
Verify the function of a design by behavioral simulation.
Objectives After completing this tutorial, you will be able to:
Create a Vivado project sourcing HDL model(s) But we are not targeting a specific FPGA
device
Simulate the design using the XSim simulator
This steps are not mandatory for the project but if you are interested I can provide
information for the next steps that can also be done on XILINX
Synthesize and implement the design
Generate the bitstream
Configure the FPGA using the generated bitstream and verify the functionality

2.0 ALU

The objective of this tutorial is to create an ALU that can add, substract, and set on less than two 32 bits
inputs (a and b).
Inputs:
a, b will be two numbers of 32 bits
ALUOperation is a 5 bit input value that determines the function the ALU will perform
Outputs:
Result is a 32 bit number the result of the operation on a, b
Zero is a one bit value that is 1 when Result is 0
(Forget by now about the CarryOut and Overflow)

3.0 Create a new design

If you are at the design center Xilinx is in the All Programs-> under the Electrical
Engineering Folder
1. Launch Vivado and create a project targeting a device (leave the default one) and select
using Verilog HDL.
Open Vivado : Start > All Programs > Xilinx Design Tools > Vivado 2013.3
Click Create New Project to start the wizard.
You will see Create A New Vivado Project dialog box. Click Next.
Click the Browse button of the Project location field of the New Project form (give a
name for your project and click select)
Select RTL Project option in the Project Type form, and click Next.
Select Verilog as the Target language and Simulator language in the Add Sources form.

You have no files to add so just ignore the file options you are going to create your
own not import them
2.

3. Leave the default options for next dialog box.

Make sure Leave the ISE simulator (VHDL/Verilog) option selected). Click Next to continue. Click Finish
to create the Vivado project

4.0 Create the ALU

1. Go to Project->New Source

3
31

The ALU.v file will be created

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:06:46 01/07/2010
// Design Name:
// Module Name: ALU
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//

// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU(
input [31:0] a;
input [31:0] b;
input [3:0] ALUop;
output [31:0] result;
output zero;
)
endmodule
now add the code to add, etc
module alu(
input [31:0] a,
input [31:0] b,
output reg [31:0] result,
output zero,
input [3:0] ALUop
);

assign zero = (result==0); //Zero is true if ALUOut is 0

always @(ALUop, a, b) begin //reevaluate if these change
case (ALUop)
0: result <= a & b;
1: result <= a | b;
2: result <= a + b;
6: result <= a - b;
7: result <= a < b ? b : 0;
12: result <= ~(a | b); // result is nor
default: result <= 0;
endcase
end
endmodule

5.0 Behavior Simulation

In this section, we will introduce the concept of test bench and show how to verify the function of our full
adder by behavioral simulation.

5.1 Build the test bench by specifying waveforms

1. Click Project->Add Sources; in the pop-up window, select Verilog Test Feature

2. Select the Add or Create Simulation Sources option and click Next.
In the Add Sources Files form, click the Create Files... button.
The tutorial_tb.v file is added under the Simulation Sources group

By defaults it does create the following file

module ALU_tb2_v;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg [3:0] ALUop;
// Outputs
wire [31:0] result;
wire zero;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.a(a),
.b(b),
.ALUop(ALUop),
.result(result),
.zero(zero)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
ALUop = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule

change the stimulus to some values for example:

module ALU_tb_v;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg [3:0] ALUop;
// Outputs
wire [31:0] result;
wire zero;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.a(a),
.b(b),
.ALUop(ALUop),
.result(result),
.zero(zero)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
ALUop = 0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

a = 0;
b = 1;
ALUop = 1;
#100;
a = 0;
b = 1;
ALUop = 2;
#100;
end
endmodule
Now you can simulate your ALU:
1.
Select behavioral simulation (instead of implementation)

Simulate the design for 200 ns using the XSim simulator.

Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane.
A Project Settings form will appear showing the Simulation properties form.
Select the Simulation tab, and set the Simulation Run Time value to 200 ns and click OK.
Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow
Navigator pane.
The testbench and source files will be compiled and the XSim simulator will be run (assuming no errors).
You will see a simulator output similar to the one shown below.

You will get a waveform similar to this one, check that the output is correct
some hints about the simulation screen to view results nicer: