Proceedings of the 5th European Microwave Integrated Circuits Conference

A Low-Power Analog-to-Digital Converter for

Multi-Gigabit Wireless Receiver in 90nm CMOS
Kevin Chuang 1 , David Yeh 2 , Stephane Pinel, and Joy Laskar
Georgia Electronic Design Center, School of Electrical and Computer Engineering,
Georgia Institute of Technology
85 Fifth Street NW, Atlanta, GA 30308, USA
1

kchuang3@ece.gatech.edu
2
david.yeh@gatech.edu

I. INTRODUCTION
The rapid development of modern communication systems
such as the 60GHz wireless devices and other wireless
products [1] with ultra-high data transmission rates drive the
demand of data converters with ever increasing sampling rates.
In order to simultaneously meet the ultra-low power
requirement for portable electronic devices [2] and extremely
high sampling rate, it is absolutely necessary to simplify the
architecture of such ADCs as much as possible by excluding
all non-essential blocks that increase power consumption and
limit the sampling speed.
ADCs range from the oversampling delta-sigma, to
medium-speed successive approximation and to the highest
sampling speed, flash. Among all of the aforementioned types
of converters, flash converters are the most suitable based on
the requirement for 60GHz wireless applications. Moreover,
flash ADCs guarantee the smallest number of clock cycles per
conversion; and thus minimum latency. This is especially
critical for mixed-signal single carrier phase recovery systems.
The performance of ADCs can be improved by means of
either analog or digital calibrations. Calibration techniques
improve the overall performance at the expense of increased
circuitry complexity, but often degrade the inter-stage
bandwidth, linearity and gain due to the presence of switches
or series-input capacitors [3]. One offline calibration scheme
proposed in [4] requires more than twice the area occupied by
the ADC core. In a highly integrated wireless radio for mobile
applications, the power consumption and area available for

978-2-87487-017-0 2010 EuMA

Digital Signal
Processor

Abstract This paper presents a very low-power (3mW, 3.9mW)

and high-speed (3GS/s, 5GS/s) flash ADC in a deep sub-micron
CMOS technology. To save power and area, unnecessary
building blocks of ADC are excluded. Optimization of
comparator has been fully analyzed to reduce random offsets due
to process scaling. Fabricated in 90nm CMOS, the experimental
results demonstrate that the ADC occupying 0.0108mm2 active
area achieves an effective resolution bandwidth (ERBW) of
1.25GHz and figure-of-merit (FOM) of 0.35pJ/conversion-step.
The peak differential non-linearity (DNL) and integral nonlinearity (INL) are 0.4LSB. The results obtained in this work is
used to satisfy the stringent power requirement of a wireless
mixed-signal receiver, specifically suitable for multi-gigabit
amplitude shift keying (ASK) and binary phase shift keying
(BPSK) demodulations.

Fig. 1 An example of wireless 60GHz radio.

Fig. 2 An example of portable UWB receiver.

data converters are extremely limited. Fig. 1 shows the mixedsignal demodulator integrated for 60GHz applications
requiring low-power, high-speed compact ADCs for digital
signal processing [5]. Fig. 2 shows the potential application
for portable UWB receiver.
The architecture of the ADC is discussed in section II. High
speed optimizations are explained in section III. The
experimental results are demonstrated in section IV followed
by a conclusion in section V.
II. ARCHITECTURE
Typically in the design of ADC, track-and-hold (T/H)
circuit is the first component that provides instantaneous
sampling of the input signal and holds its output at the
sampled level for the rest of the clock period. Charge
redistribution from the nonlinear parasitic capacitance and the
sampling capacitor indicate distortion while this output slowly
settles to its final state. In order to avoid this distortion, T/H
circuit must provide high bandwidth, which requires higher
power consumption. However, mobile applications targeted in
this work require extremely low power consumption; hence in
the proposed ADC, T/H circuit is excluded. Consequently, the
design of high speed comparator becomes critical and requires
optimization. By placing two converters in parallel and

218

27-28 September 2010, Paris, France

Fig. 3 Time-interleaved architecture.

Digital back-end

6th

5th

0th

Za[2:0]

Zb[2:0]

2:1 MUX

3-bit Flash ADC Architecture

Z[2:0]

Fig. 5 Schematic of the high speed comparator.

Vin
CLK

phase (clk is high), the gain and the total input noise without
considering flicker noise are derived in (1) and (2)
respectively, where coefficient  is a constant depending on
the technologies.

clk
clkb

Fig. 4 Block diagram of a 3-bit flash A/D converter

W5
Ron ,9
W3
Av v
4  2 g m 7 Ron ,9
g m1

interleaving them (in Fig. 3), the clock frequency for each
converter can be reduced while maintaining the same system
throughput.
III. HIGH SPEED OPTIMIZATIONS
Unlike the conventional architecture, track-and-hold circuit
and difference amplifiers are removed to enable ultra lowpower processing [6]-[8]. The block diagram in Fig. 4 consists
of 2N-1 taps of reference voltages, high speed latched
comparators, buffers and digital back-end.
A. Optimization of Comparator
Two practical issues in high-speed comparator design are:
technology dependent gain-bandwidth product (GBW)
constant of an amplifier and the poor isolation between the
latch output and the input of the difference amplifier through
the drain-gate capacitances of input transistors, inducing
strong kick-back noise to the preceding stages. Unlike the
switched-cascode comparator in [8], Fig. 5 shows the currentmode latched comparator implemented for the low-power
ADC operation that can solve these two problems. First, the
bandwidth requirement for high speed operation during
comparator
amplification
phase
is
defined
as
BW INTER ! (n  1) ln(2) f s / 2S assuming half of the sample
period is used for settling with n-bit resolution [9]. With n = 3,
the minimum bandwidth for settling is: BW > 0.88fNyquist for
time interleaving.
Secondly, the input differential pairs before the latch has
the advantage of reducing the input offset voltage of the latch
and the gain is also enhanced from the current mirroring. The
overload recovery time is determined by M9, the output
parasitic capacitance and the transconductance of M7-M8. The
comparator is optimized based on the trade-offs of gain and
total input-referred thermal noise. During the amplification

Vn2,in
'f

v 16kT (

J
g m1

(1)

g m3J
g

2
m1

2  g m7 Ron,9
g m5J
)

W
W
g m21 ( 5 ) 2 g m21 ( 5 ) 2 Ron,9
W3
W3

(2)

As seen from the equations, to minimize thermal noise and

resolve higher resolution, the transconductance of M1-2 and the
width of M5-6 must increase.
B. Optimization of Data Path
In Fig. 6, the output of the comparator interfaces with a
buffer consisting of two inverters. The trip point of the first
inverter is resized low to avoid unnecessary switching power
during the amplification phase when clk is high.

219

Fig. 6 Schematic of high speed data path.

The timing constraint for the highest achievable speed is

governed by the setup time (tsu) of the DFF. Since the
propagation delays due to the comparator (tlatch) and buffer
(tbuf) constitute enough margin for hold time, the only possible
error is caused by the inadequate margin of setup time.
Therefore, the maximum clock frequency is derived 2.7GHz.

1
t CLK

2 (t latch

1
 t buf  t su )

(3)

IV. EXPERIMENTAL RESULTS

The proposed ADC chip occupies 120m x 90m
(0.0108mm) active area. It is fabricated in a 90nm 7-metal
single-poly CMOS process. The microphotograph is shown in
Fig. 7. Fig. 8 shows the test setup for both static and dynamic
performance in a standard ADC-DAC test. A 1.8V power
supply is only used for the output 50 buffer to facilitate
spectrum analyzer measurement. The digital interface captures
the static response of the ADC directly from a DC input.

Fig. 10 Measured spectrum of 346MHz input at 3GS/s.

Fig. 7 Microphotograph of the ADC test chip.

2:1 MUX <2:0>

Fig. 11 Measured spectrum of 834MHz input at 5GS/s.

25

SFDR (dB)

20

0.50

0.25

0.25

INL (LSB)

DNL (LSB)

Fig. 8 ADC test setup.

0.50

0.00
-0.25
-0.50
2

Output Code

15

10

0.00
-0.25

5
0.1

-0.50
0

5GS/s
3GS/s

1
Input Frequency (GHz)

10

Output Code

Fig. 12 Measured SFDR vs Fin.

Fig. 9. Measured DNL/INL at 3GS/s.

The measured static performance of the ADC is shown in

Fig. 9. At 3GS/s operation, the peak DNL and INL are both
0.4LSB. Fig. 10 captures the output spectrum with a 346MHz
input at 3GS/s. The same output is further observed at 5GS/s
when input frequency is increased to 834MHz (shown in Fig.

11). From both plots, the error due to the INL is estimated to
be less than 1-b LSB since the fundamental tone is at least 6ndB (in our case 18dB) above all the individual harmonics and
distortions, where n is the theoretical number of bits [10].
The dynamic performance is characterized in Fig. 12 and
13. This ADC achieves spurious free dynamic range (SFDR)

220

16

SNDR (dB)

The performance of the measured ADC is summarized in

Table I and compared with the current state-of-the-art ADCs
in Table II indicating one of the most power-efficient highspeed converters and the highest power efficiency for an ADC
operating at both 3GS/s and 5GS/s. Degradations of the actual
ADC performance include but are not limited to power and
ground bounce, comparator mismatch, INL/DNL of the DAC,
output buffer nonlinearities, signal source distortion and
output harmonic distortions with no filtering.

3GS/s
5GS/s

12

4
0.1

V. CONCLUSION
A time-interleaved high-speed 3-bit flash ADC in 90nm
CMOS is presented. In order to achieve excellent power
efficiency, T/H and difference amplifiers are removed and
only the very essential blocks are retained. Thorough
optimizations are analyzed and the results demonstrate an
ultra low-power (3mW, 3.9mW) and high-speed (3GS/s,
5GS/s) performance. This represents an opportunity for a
multi-gigabit real-time digital processing for portable UWB
systems and 60GHz radio applications, satisfying the stringent
power budget for portable consumer electronic devices.

10

Input Frequency (GHz)

Fig. 13 Measured SNDR vs Fin.
TABLE I
PERFORMANCE SUMMARY

Resolution
Supply Voltage
Input Range
Sample Rate
Power
SFDR (dB)
SNDR (dB)
ENOB (bit)
ERBW
FOM
DNL / INL
Active Area
Technology

This work
3 bit
1V
200 mVpp

REFERENCES
[1]

3 GS/s
5 GS/s
3 mW
3.9 mW
23.2 @fin=346MHz
19.84 @fin=834MHz
16 @fin=346MHz
14.73 @fin=834MHz
2.37 @fin=346MHz
2.15 @fin=834MHz
1.25 GHz
1.15 GHz
0.35 pJ
0.465 pJ
< 0.4 LSB
0.0108 mm2
90 nm

[2]

[3]

[4]

TABLE II
COMPARISON WITH STATE-OF-THE-ART

Resolution
Sample Rate
(GS/s)
Power (mW)
Area (mm2)
Technology
(m)
FOM (pJ)

[5]

[4]
4

[6]
4

[7]
4

[11]
3

THIS
3

1.25

20

10.6
0.021
0.18
CMOS
0.81

2.5
0.033
0.09
CMOS
0.16

43
0.06
0.18
CMOS
2.14

2360
2.55
0.12
SiGe
109

3
0.0128
0.09
CMOS
0.35

[6]

[7]

[8]

of 23.2dB at 3GS/s and 19.84dB at 5GS/s with 346MHz and

834MHz input, respectively. With the same input frequencies,
its measured signal-to-noise and distortion ratio (SNDR) are
16dB at 3GS/s and 14.73dB at 5GS/s. The curve in Fig. 13
indicates an ERBW of 1.25GHz at 3GS/s and 1.15GHz at
5GS/s, respectively. At 3GS/s operation, the measured SNDR
is above 15dB for input frequencies up to 1000MHz and the
SFDR is above 20dB for input frequencies up to 850MHz.
The total power consumption is 3mW at 3GS/s and 3.9mW at
5GS/s. Its effective number of bit (ENOB) is 2.37 up to a
conversion rate of 3GHz.

[9]

[10]

[11]

221

D. Yeh, S. Sarkar, S. Pinel, P. Sen, and J. Laskar, An Integrated IQ

Demodulator with Integrated Low-Power BPSK/ASK Analog Signal
Processor in 90nm CMOS, in IEEE European Microwave Integrated
Circuit Conf., October 2008, pp. 139-142.
S. Sarkar, P. Sen, B. Perumana, D. Yeh, D. Dawn, S. Pinel, and J.
Laskar, 60 GHz single-chip 90nm CMOS radio with Integrated Signal
Processor, in IEEE MTT-S International Microwave Symposium
Digest, June 2008, pp. 1167-1170.
M. Choi, and A. A. Abidi, A 6-b 1.3-Gsample/s A/D Converter in
0.35-m CMOS, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp.
1847-1858, December 2001.
P. Nuzzo, G. Van der Plas, R. De Bernardinis, L. Van der Perre, B.
Gyselinckx, and P. Terreni, A 10.6mW/0.8pJ Power-Scalable 1GS/s
4b ADC in 0.18m CMOS with 5.8GHz ERBW, in Design
Automation Conf., July 2006 , pp. 873-878.
K. Chuang, D. Yeh, F. Barale, B. Perumana, S. Sarkar, P. Sen, S. Pinel,
and J. Laskar, A 17pJ/bit Broadband Mixed-Signal Demodulator in
90nm CMOS, in IEEE MTT-S International Microwave Symposium
Digest, May 2010, to be published.
G. Van der Plas, S. Decoutere, and S. Donnay, A 0.16pJ/ConversionStep 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process, in
IEEE Solid-State Circuits Conf., February 2006, pp. 566-567.
S. Sheikhaei, S. Mirabbasi, and A. Ivanov, A 43mW Single-Channel
4GS/s 4-Bit Flash ADC in 0.18m CMOS, in IEEE Custom
Integrated Circuits Conf., September 2007, pp. 333-336.
S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, A 3.5
GS/s 5-b Flash ADC in 90 nm CMOS, in IEEE Custom Integrated
Circuits Conf., September 2006, pp. 489-492.
S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, A 1.35
GS/s, 10b, 175mW Time-Interleaved AD Converter in 0.13 m
CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778-786,
April 2008.
J. Doernberg, H. Lee, and D. A. Hodges, Full-speed Testing of A/D
Converters, IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 820-827,
December 1984.
Y. Yao, X. Yu, D. Yang, F. Dai, J. D. Irwin, and R. C. Jaeger, A 3-bit
20GS/s interleaved flash analog-to-digital converter in SiGe
technology, in IEEE Asian Solid-State Circuits Conf., November 2007,
pp. 420-423.