50 Part I Semiconductor Devices and Basic Applications

Power
transformer
+
,-­ -
f-­ ~

AC
Diode Filter Voltage
voltage
rectifier regulator
LOAD
source

~
-
f-­ c---"

Figure 2.1 Block diagram of an electronic power supply

power source. We will use the piecewise linear approach to analyze this circuit,
assuming that the diode forward resistance rf = 0 when the diode is "on."
Figure 2.2(b) shows the voltage transfer characteristics, Vo versus v I, for
the circuit. For VI < 0, the diode is reverse biased, which means that the
current is zero and the output voltage is zero. As long as VI < V y , the diode
will be nonconducting, so the output voltage will remain zero. When VI > Vr
the diode becomes forward biased and a current is induced in the circuit. In
this case, we can write
. VI - Vy
tv = R (2.1(a) )

and
Vo = ivR = VI - Vy (2.1(b»
For VI > V y , the slope of the transfer curve is 1.

1'0

+ "v -
+

(a) (b)
Figure 2.2 Diode in series with ac power source: (a) circuit and (b) voltage transfer
characteristics

If VI is a sinusoidal signal, as shown in Figure 2.3(a), the output voltage

can be found using the voltage transfer curve in Figure 2.2(b). For VI :::; V.
the output voltage is zero; for VI > V y , the output is given by Equation
(2.1(b)), or
Vo = VI - Vy
and is shown in Figure 2.3(b). We can see that while the input signal ('I
alternates polarity and has a time-average value of zero, the output voltage
Vo is unidirectional and has an average value that is not zero. The input signal
is therefore rectified. Also, since the output voltage appears only during the
positive cycle of the input signal, the circuit is called a half-wave rectifier.
 Chapter 2 Diode Circuits 55

N I :N z 3
5
+ • • +

vI Vs 2
I vsl

0 +
4
(a) (b)

2T t

(c)
Figure 2.7 A full-wave bridge rectifier (a) circuit showing the current direction for a positive
inputcycle, (b) current direction for a negative input cycle, and (c) input and output voltage
waveforms

\'0 is as shown in Figure 2.7(a). During the negative half-cycle of the input

voltage. Vs is negative, and D 3 and D 4 are forward biased. The direction of

the current, shown in Figure 2.7(b), produces the same output voltage polarity
as before.
Figure 2.7(c) shows the sinusoidal voltage Vs and the rectified output
voltage \'0' Because two diodes are in series in the conduction path, the
magnitude of Vo is two diode drops less than the magnitude of vs.

Example 2.2 Objective: Compare voltages and the transformer turns ratio in two
full-wave rectifier circuits.
Consider the rectifier circuits shown in Figures 2.6(a) and 2.7(a). Assume the
input voltage is from a 120 V (rms), 60 Hz ac source. The desired peak output voltage
II) is 9 V. and the diode cut-in voltage is assumed to be V, = 0.7 V.

Solution: For the center-tapped transformer circuit shown in Figure 2.6(a), a peak
voltage of I'ot max) = 9 V means that the peak value of vs is

Is(max) = va(max) + V, = 9 + 0.7 = 9.7 V

For a sinusoidal signal, this produces a rms value of

9.7
I'S.frm = ----;= = 6,86 V

\/2

The: t urn, ratio of the primary to each secondary winding must then be
\ 1"')()
:"""':'=---=17')
.\"~ 6,86 ..

For the bridge circuit shown in Figure 2.7(a), a peak voltage of va (max) = 9V
means that the peak value of vs is

vs(max) = va(max) + 2V, = 9 + 2(0.7) = 10.4 V

 Chapter 2 Diode Circu its 55

N] N2 3
+ • • +

v/ Vs 2
I Vs I

0 +
4
(a) (b)

2T I

(c)
Figure 2.7 A full-wave bridge rectifier (a) circuit s howing the current dire ction for a positive
input cycle , (b) curre nt direction for a negative input cycle, and (c) input and outp ut voltag e
waveforms

\' 0is as shown in Figure 2.7(a) . During th e negative half-cycle o f th e input

volt age. Vs is negative, and D 3 and D 4 a re forward biased. The direction o f
the current, sh own in Figure 2.7(b) , produces the same output volt age polarity
as before .
Figure 2.7(c) shows the sinuso ida l voltage Vs and the rect ified output
vol tage \ ' 0' Be cause tw o diodes ar e in se ries in th e condu cti on path . th e
magnitude of Vo is two di od e drops less than the ma gnitude o f vs.

Example 2.2 Objective: Co m p a re vo ltages and th e t ran sformer turn s ratio in two
full-wave recti fier c ircu its.
Consider th e re ctifier circ u its shown in Figures 2.6(a) and 2.7(a ). Assume th e
in put voltage is fro m a 120 V ( rms), 60 H z ac so u rce . T he d esired peak o u tp u t vo ltage
I ' f) is 9 V. an d t he di od e cut -in vo ltage is ass um ed to b e V, = 0.7 V.

Solution: For th e ce n te r-ta p pe d transformer circuit sho wn in Figure 2.6(a ), a pe ak

voltage of ,'o ( ma x) = 9 V me an s that the pe ak value o f vs is
I's( ma x) = vo( max) + V, = 9 + 0 .7 = 9.7 V

Fo r a sinuso id a l sig na l. this pr oduces a rm s value of

I Sf ", ' = 9; =
\' 2
6 .86 V

T he tu rn s ra tio o f th e prim ary to each seco nda ry windin g mu st th en be

<
\ 1::'0
== 6.86 = 17.5

For th e brid ge circuit sho w n in Fi gure 2 .7( a) , a pe ak vo ltage o f vo( max) = 9 V

me an s that th e pe ak value of vs is

vs(max) = vo( max) + 2V, = 9 + 2(0 .7) = lOA V

 Chapter 2 Diode Circuits 57

v,
Vo
-, -,
\ I \ I \
\ I \ I \
\ I \ I \

T'

Figure 2.9 Output voltage of a full-wave rectifier with an RC filter

Th e sm a llest output voltage is

V L = VM e-TIR C (2.3)

where T' is the discharge time , as indicated in the figure .

Th e ripple voltage V, is defined as the difference between V~l and V L .
and is determined by
Vr = V M - V L = V <\.f(J - e- T ' IRC) (2.4)

Normally, we will want the di scharge time T' to be sm all compared to

the time constant, or T' ~ RC. Expanding the exponential in a se ries and
keeping only the linear terms of th at expansion, we hav e th e approximation

e- r 'IRC == 1 - ­T' (2.5)

RC

Th e ripple volt age can now be written as

V-V (T)
r =RC ,l/
(2.6)

Sin ce the discharge time T' dep end s on the RC time con stant, Equat ion
(2,6) is difficult to solve . However , if the ripple e ffe ct is sm all. then as an
approxim ation. we ca n let T' = T", so that

v,==\ 1
II. (!'L)
RC (2.7)

where T; is the tim e between peak valu es of the o u tp ut voltage . For a full­
wave rectifier, T; is one-half the sig na l period . Therefore. we can relate T
to the signal frequency , "

1
f =2 T
p

The rippl e voltage is then

V =~ (2.8)
r 2f Re

For a half-wave rectifier, the time Tp corresponds to a full period (not a

half period) of the sig na l, so the fa ctor 2 doe s not appear in Equ ation (2.8).
Equ ation (2.8) can be used to determine the ca pacito r value required for
a particular ripple voltage .
 Chapter 2 Diode Circuits 69

D2.7 Design a parallel-b ased clipp er th at will yield the volt age transfer fun ct ion
shown in Figure 2.25 . Assume diode cut-in voltages o f V r = 0.7 V. (A ns. Using Figure
2.20(a) , V 2 = 4.3 V, V I = 1.8 V, and R 1 = 2 R 2 )
2.8 Repeat Example 2.6 if the dir ection of the di ode is reversed . (Ans. Output is a
sq uare wave between - 2 V a nd +6 V )
2.9 Determine the ste ady-sta te output volt age Vo for the circu it shown in Figure
2.26(a ), if the input is as sho wn in Figure 2.26(b). A ssum e the di od e cut- in voltage is
V y = O. (A ns. Output is a sq ua re wave between + 5 V a nd +35 V )

T= I ms-j
+ 10

C= I/lF Of--+--+----i­- -+----+-­ -+­- - -­

+-----1[--;----------0
+

+
VB =5 v czz:
- 20

(a) (b)
Figure 2.26 Figure for Exercise 2.9

2.3 ZENER DIODE CIRCUITS

In Ch apt er 1, we saw that th e br eakdow n volt age of a Ze ne r d io de was nearl y
co nsta nt over a wide ran ge of rev erse-bias curre nts. T his mak es th e Z en er
diod e useful in a voltage regulator, or a constant-voltage reference circuit. In
this ch apt er, we will look a t a n ideal vo ltage reference circ ui t, and the e ffects
of including a non ideal Zener resistance.

2.3.1 Ideal Voltage Reference Circuit

Figure 2.27 sho ws a Zener vo ltag e regul at or circ uit. Fo r thi s circ uit, the o utp ut
voltage should remain constant, eve n when th e output load resistance varies
ove r a fairl y wide ran ge , and wh en the input vo ltage va ries over a specific range .

R,
+

Figure 2.27 A Zener diode voltag e regulator circuit

We determin e , initially, the proper input resistan ce Ri . T he resistance R,

limit s the current through the Ze ne r d iode and drops the "excess" voltage
 Chapter 2 Diode Circuits 71

Design Example 2.7 Objective: D esign a volt age reg ula tor, usin g th e ci rc uit
show n in Figure 2.27 .
Ass ume th at th e Z en e r d io de has a break down vo ltage of V z = 10 Y, th e pow er
supply is in th e ran ge 20 :S V ps :S 24 Y, a nd the load res ista nce va ries fro m 100 to
500 n. D e te rm ine R, a nd the re qu ire d pow e r ra ting of the Z en e r diode .

Solution : T he maximum a nd m in imum lo ad c ur ren ts are

Vz 10

Idm ax ) = R d mi n ) = Q.1 = 100 rnA

and

. Vz 10
Idm tn ) = = -=20mA
R d m ax ) 0.5

Usi ng E qu at ion (2 .27) , th e ma ximum Zene r diode curre nt is

1_( .) = (100) ' [24 - 10] - (20)' [20 -10] = 140 A

z ma x 20 _ 0.9(10) _ 0. 1(24) m

T he maximum pow er d issipa tio n in the Z en er diode is

P z (m a x) = Iz ( m ax ) V z = (0 .14)(10) = 1.4 W

Fro m E q ua tion (2 25( b)), the va lue o f th e inp ut re sist a nce R, is

R, = Vps( m ax) - V z = 24 - 10 =) 87 .5 n
Iz (m ax ) + Id mtn ) 140 + 20

Comment: By co nsideri ng variou s co m bina tio ns of V ps a nd R L , we ca n det erm ine that

the dio de cu rre nt r em a ins wi thi n the ran ge of 14 :S l z :S 140 m A , o r O.lI z ( ma x) :S
Iz :S Iz (m ax ). as th e des ign specified .

2.3.2 Zener Resistance and Percent Regulation

In the ide al Ze ne r diode, the Z e ner resist ance is zero. In actu al Zen er d iodes,
however. this is not th e case. The result is that th e o utp ut vo ltage is a func tio n
of the Z en er d iod e cu rre nt or the load cu rre nt.
Figure 2.28 sh ows th e equ ivalent circ ui t of th e vol tage regulator in Figur e
2.27. Becau se of th e Ze ne r res ista nce, th e output vo ltage will not remain
co nsta nt. We ca n de term ine the m inim um a nd maximum va lues of o utp ut
voltage . A figure of me rit fo r a vol tage reg ula to r is called the percent regula-

R,
+
I,
t Id +

\ PS -=- Iz ~ rz
Vz RL vL
~

Figure 2.28 A Zene r diode voltage regulator circuit with a nonze ro Zener resistance
84 Pa rt I Semico nd uctor Devices and Basic Appl icati on s

2.2 For th e circu it sho wn in Figure P2.2, sho w that for 1', :2: O. th e output vo ltage
+ D
+
is a pproxi ma te ly give n by
R Vo

Va = v i : V Tln (~~ )
2.3 A ssume th e input to th e circuit shown in Figure P2.2 is a triangular wave of
Figure P2.2
20 V peak-t o-p ea k a mplitude with a zer o tim e-av er age valu e. Le t R = 1 kfl a nd ass ume
piecew ise linear diode param et er s of Vy = 0.6 V and r f = 20 fl . Sketch th e output
voltage ver sus tim e ove r on e cycle and label all appro pr iate voltages.
02.4 Th e input signa l voltage to th e full-wa ve rectifier circ uit show n in Figure 2.7(a)
in th e tex t is 1', = 160 sin[2rr(60)1] V. A ssume Vy = 0.7 V for each d iod e. Det erm ine
th e required turns ratio of th e transformer to produce a peak output volt age of (a)
25 V. and (b) 100 v.
02.5 T he o utp ut res ista nce o f th e full-wave rec t ifier sho wn in Figur e 2.7(a) in th e
text is R = 150 fl. A filter ca pacitor is connect ed in par allel with R. As sume Vy =
0.7 V. Th e pe ak out put volt age is to be 24 V a nd the rip ple volt age is to be no mor e
th an 0.5 V. T he input frequ en cy is 60 H z. (a) Det ermine the required rm s va lue o f
I's . (b) D e termin e th e re q uire d filte r capacitance va lue . (c) Determ ine the pe a k current
th rough each diod e.
02.6 Rep eat Pr o blem 2.5 fo r a half- wave rectifi er ; th at is D 3 and D 4 a re e lim ina ted
fro m th e circ uit show n in Figure 2.7(a)
2.7 Th e circuit show n in Fig ure P2.7 is a co mp leme nta ry output recti fie r. If I' s =
26 sin[2rr(60)1] V, ske tch th e o utp ut wavef orms v; a nd v; vers us time , ass umi ng Vy =
0.6 V for each di od e .

..
I/ o

• +
,.s

J
R

~
• +
I' , R

,.­
0

Figure P2.7

02.8 A ss ume th at eq ua l filter ca pac ito rs are co nnec ted in para lle l with each load
resis to r R in the circuit described in Problem 2.7. If R = 100 fl and the ripp le vo ltage
is to be no more th an V, = ] V, determine th e value of C required .
*02.9 A full-w av e rectifie r a nd a n input volt age are sho wn in F igure P2.9. T he cut­
in voltage of ea ch d iode is Vy = 0.6 V. (a) Sketch th e o utput volt age vers us time. (b)
T he ave rage pow er d issipa te d in R L is to be P L = ]0 0 rnW. Det ermin e the correct
valu e of R L .

+;~h
:rv
r.I
»--~- " o

Figure P2 .9
 Cha pter 2 Diode Circuits 85

*2.10 Sk et ch Va ve rs us tim e fo r th e ci rc ui t give n In Fig ure n. lO wit h the inp ut

show n. A ssume V y = O.

~
' +
+40
Vi

-40

Figure P2 .10 Figure P2.11

*2.11 (a) Ske tch Va ve rs us tim e fo r th e circ ui t show n in Figu re P2.l l. The in put is
a sine wave give n by Vi = 10 si nwt V. Ass ume V y = O. (b) D et e rm ine th e rms val ue
of th e o utp ut vo ltage.

Section 2.2 Clipper and Clam per Circuits

2.12 (a) Co nsi der th e circ ui t s how n in Figu re P2.12 a nd ass ume V y = O. Ske tc h the
ou tput vo ltage ve rs us tim e if th e in p ut is a sine wave wi th a pea k valu e of 10 V. (b)
Re peat part (a) if V y = 0.7 V .

I H2

R = I kO

I kO 2kn
,.-'l/v'Vlr--4--'WV\r-- + 15 V
+SV
+ I 'U - R = 2.2 U2
Figure P2 .12 Figure P2 .13 "/~
;: 1
---l +
0 -==-- :2 V
2.13
VI S
Fo r th e ci rc ui t shown in Figure P2 .13, p lo t
I S V. Ass ume V, = 0.7 V. Ind icat e a ll b rea kpo ints .
Va ve rs us VI for 0 s
I
2.14 A ssume V y = 0.6 V for the di ode in th e circ uit giv e n in Fig ur e P2.l 4. Ske tch Figure P2.14
Vo a nd i o versu s time if VI = 5 s i n w l V.

*2.15 The d iode s ho wn in the circ uit o f Figure P2 .15( a) has piecew ise line a r pa rame ­
ters v, = 0.7 V a nd Tf = 10 D . (a) Plo t Va versus VI for -30 .s VI S 30 V . (b) If th e
trian gul a r wave . s how n in Figu re P2. 15( b) , is applied, plot th e o ut put vers us t ime .

R = 100 n

" ~"
30 V

\ I
-=- 10 V \

I ­
(a) (b)
Figure P2.15