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I.
INTRODUCTION
Over the past years, many researches on successiveapproximation-register analog-to-digital converters (SAR
ADC) have been published [1]-[3] for applications which
require low-power dissipation. The SAR ADC
architecture is well suitable for large-scale wireless sensor
networks and bio-medical applications due to its
moderate speed, moderate resolution and very low-power
consumption characteristics. The primary sources of
power consumption in a SAR ADC are the comparator
and charge/discharge of the capacitor array. The energy
dissipation required to charge/discharge the capacitor
array is dominated by the switching sequence. The
conventional switching sequence is an inefficient
procedure and much of energy is wasted on charging and
discharging the capacitor array.
This paper proposes an energy-saving switching
sequence technique to minimize the power consumption
of the capacitor array and the details about circuit design
are organized as followings: the ADC architecture and
energy-saving switching sequence technique is discussed
in Section 2 and the building block circuit designs are
presented in Section 3. The measurement results are
summarized in Section 4. Finally, summary of this design
is offer in Section 5.
II.
ADC ARCHITECTURES
1-4244-1360-5/07/$25.00
2007 IEEE
2n-3C
2C C
2n-1C
2n-3C
2C C
2n-1C
2n-3C
2C C
Gnd
Vdd
Vin
Vdd
Vdd
SAR
Control Unit
D1
D2
Dn
Vip
Vdd
Gnd
2n-3C
2C C
(1)
i =1
228
Switching Phase 3
Switching Phase 2
Vref
4CVref2
Vref
4C 2C
5CVref2
Switching Phase 1
Vref
Vref
4C 2C
C
Vip-Vin > 0 ?
4C 2C C C
Vip Vip Vip Vip
4C 2C C C
Vref Vref Vref
Vref Vref
4C 2C
2
ref
CV
4C 2C C C
Vref Vref
C
Vip-Vin > 3Vref/4 ?
Vref
4C 2C C
9
CVref2
4
5
CVref2
4
4C 2C C C
Vref Vref
Vref
Vref Vref
4C 2C C C
Vip-Vin > Vref/4 ?
4C 2C C C
Vref
Vref
Vref
Vref
4C 2C C C
13
CVref2
4
4C 2C C C
Vref
Vref
Vip-Vin > -Vref/2 ?
Vref Vref Vref
4C 2C C C
1
CVref2
4
Vref
(a)
C
Vref
C
4C
4C
Switching Phase 3
Vref Vref
C C
Switching Phase 2
1
CV ref2
4
4C
C
C
Vref
Vref Vref
C
C
Vin Vin
C
C
Vin
4C
Vin Vin
C C
Vref
Switching Phase 1
5
CV ref2
4
4C
Vref
C
4C
4C
C
C
Vref
Vip-Vin > 0 ?
4C
C C
Vip Vip
C
C C
Vref Vref
C
Vref
4C
Vip
4C
Vref
3CVref2
Vref Vref
C
C
C
Vip Vip
3CV ref2
Vref
4C
Vref
4C
5
CVref2
4
Vref Vref
C C
Vref Vref
1
CV ref2
4
(b)
Vref
C
C
Vref Vref
Vref
C
C
Vref
C
C
Vref
4C
Vref Vref
C
C
Vip-Vin > -3Vref/4 ?
4C
C
Vref
Fig. 2. (a) Conventional Switching Sequence. (b) Proposed energy-saving switching sequence.
(2)
i =3
III.
CIRCUIT DESIGN
A. Capacitor Array
The linearity of the SAR ADC is dependent upon the
229
10
10
10
10
Conventional
Energy-Saving
5
10
n-bit Capacitor Array
15
Fig. 3. The average switching energy of two sequences for an n-bit SAR
ADC.
B. Comparator
The comparator circuit is shown in Fig. 6.The operation
principle is described below. When Vclk is low, the
comparator is in precharge phase. Nodes Vout+ and Voutare precharged to Vdd by transistors M5 and M6. Because
M9 is off at this time, no dc current flows from Vdd to
ground. When Vclk is high, the comparator is in
comparison phase. At this time, Vout+ and Vout slew
towards ground at unequal rates according to the
differential input voltage Vin+ and Vin-. Once the voltages
of Vout+ and Vout- are low enough, the PMOS positive
feedback load formed by M7 and M8 latches the
comparator. When the comparator is in steady-state, there
is also no dc current flowing from Vdd to ground.
Therefore, it is suitable for low power application due to
no static current consumption.
500
Vdd
Conventional
Energy-Saving
400
Vclk
M5
300
M7
M8
Vout-
200
Vout+
M3
100
0
50
100
150
Output Code
200
M4
Vclk
Vin+
M1
250
Vclk
M6
M2
Vclk
Vin-
M9
Fig. 4. The energy versus output code required for the switching of the
capacitor array.
Fig. 6. Comparator circuit.
Set
Q
QB
32
32
128
16
4
4
8
8
Reset
QB
Reset
Reset
Set
Switch
Control
Reset
Set
D
QB
Reset
32
Reset
Set
Logic
Switch
Control
Q
QB
Reset
Set
Logic
QB
S2
Logic
Q
QB
Reset
Reset
S1
Set
Switch
Control
Q
QB
QB
16
128
32
QB
QB
DUMMY
DUMMY
16
16
Set
32
128
2 1 1 2
2 1 1 2
128
S7
Set
Comp
128
4
4
S6
Set
CLK
32
8
8
S1
Set
QB
Reset
DUMMY
128
Bit cycling
Sample
Set
Reset
S7
128
32
32
128
DUMMY
230
IV.
MEASUREMENT RESULTS
Amplitude [dB]
-20
-40
Fin @ 231KHz
SNDR = 46.92 dB
ENOB = 7.5 bits
SFDR = 62.69 dB
-60
-80
-100
0
6
5
ENOB
DNL (LSB)
250
4
3
2
100
150
200
250
DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
1
INL(LSB)
200
50
1
0
0
0
-1
0
100
150
Frequency [kHz]
-1
0
50
50
100
150
Input Frequency [KHz]
200
250
100
150
200
DIGITAL OUTPUT CODE
250
ACKNOWLEDGMENT
FOM =
Power
2 ENOB f s
(3)
The FOM of this work corresponds to 86fJ/conversionstep and is better than previous publications [2][3].
REFERENCES
[1]
[2]
[3]
[4]
V.
CONCLUSIONS
J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, A 0.5-V 1W Successive Approximation ADC, IEEE J. Solid-State
Circuits, vol. 38, no. 7, pp. 1261-1265, July 2003.
M. Scott, B. Boser, and K. Pister, An Ultra Low-Energy ADC for
Smart Dust, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 11231129, July 2003.
N. Verma and A. Chandrakasan, A 25W 100kS/s 12b ADC for
Wireless Micro-Sensor Applications, ISSCC Dig. Tech. Papers,
pp. 222-223, Feb. 2006.
B. P. Ginsburg and A. P. Chandrakasan, An energy-efficient
charge recycling approach for a SAR converter with capacitive
DAC, in Proc. IEEE Int. Symp. Circuits and Systems,2005, vol. 1,
pp. 184-187.
231