Term End Examination - September 2013

Class NBR
Course Code
Course Title
Time : Three Hours

: 1022
Slot : A2+TA2
: EEE575
: Scripting Languages and
Verification
Max.Marks:100

Answer ALL Questions

(10 X 10 = 100 Marks)
1.

[5]

a) Describe the operation and the result in PERL

i) /^\s*$/;
ii) /^\s*\S+\s+\S+\s+\S+\s*$/;
iii) $_=Dar21 presents;
iv) /^\s*([a-zA-Z]+)/; print $1;
v) /^\s*(\W+)/; print $1;
b) Write a Perl script to create an array that contains the names of 10 students of a class.

[5]

Print the array. Add that names at the end and beginning of array. Print the array. Ask
user to input a number. Print the name that has that number as index. Remove last
and starting element of array. Print the array in alphabetical and in reverse order.
2.

Write a Perl script which will read a mathematical sentence from the user, evaluate the

[10]

result, and print the result to the screen. For example, if the user types
2 + 4 = the program will output 6. The result should be written in output file. All
formulas will be given in the format Operand_1 Operator Operand_2 =
The characters in the formulas may or may not be separated by white space. The
operators that must be supported are: +, - , / , * , % .
3.

[5]

a) I) Create regular expressions that:

i) match any floating point number.
ii) match the following tree words a507, b702, c334.
iii) swap the two words of the following string 45 67.
II) Give the string example which satisfies the following perl regular expressions
i) /(\w+\s+)(\w+)(\s+\w+)/

ii) s/[ \t]+\n$/\n/.

b) Write a perl program that reads a number and then a list of strings (all on separate
lines), and then prints one of the lines from the list as selected by the number.

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[5]

4.

a) Write a TCL Script to Reverse the elements of a List using a While and a FOR loop.

[5]

b) Create a new TCL command called ldelete which deletes a particular element in a

[5]

list, It takes two arguments a list and a value , it deletes the element specified by the
value.
5.(a)

Create a new TCL command called Fibonacci which generates Fibonacci series but

[10]

the no. of elements generated is limited by an integer value specified as argument to the
command.
OR
5.(b)

Write a perl script that prints those mosfets that act as moscaps. The drain, source and

[10]

bulk of mosfet are connected to the same net and the gate is connected to the other net.
6.(a)

Consider the following state transition diagram of the lift controller of block, which has

[10]

three floors. The states are encoded using a 2 bit bus, whereas the inputs are denoted by
2 bits. There are 3 states, one corresponding to each floor, denoted by L0, L1 and L2.
The state 0, denoted by L0 is the initial state. The labels on the arrows represent the valid
inputs received by the controller, which can be 0, 1 or 2. Using the state space approach
derive test scenarios to detect bugs in the state transition diagram. Based on it redraw a
more correct state transition diagram which takes care of the corner cases.
i) Which verification topology and test cases are used to verify the above controller?
ii) Write the verification scenarios to verify the lift controller

State transition diagram of Lift controller

OR
6.(b)

There are two bus masters linked to a central arbiter by individual request (REQ#) and
grant (GNT#) signals. Each master has its own REQ# and GNT# lines. Apart from this
the arbiter also receives an input reset (RST#) signal. Consider the following timing
specification: Whenever the signal RST# is deasserted and in the next clock cycle REQ#
is asserted, the GNT# signal is asserted after 3 clock cycles after the REQ# assertion and
remains high for 7 clock cycles.
Write verilog BFM code to model the above specification with timing diagram.

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[10]

7.

Dual port RAM (DPRAM) provides a common memory accessible to 2 processors that
can be used to share and transmit data and system status between two processors.
Consider a DPRAM wrapper in verilog:
dram(addr0, data0, addr1, data1)
The dimension of the data bus is 1 bit and that of the address bus is 4 bits. The wrappers,
written in verilog has tasks read_memory and write_memory which you can invoke
from a top level testbench.We also have suitable wrappers for the verilog codes for a
processor:
cpu(busy,addr,data,control)
The control and busy bits are 1 bit each and the data and address are as that of the
DPRAM.

A block named TestnSet probes two processors P0 and P1 which share a DPRAM. The
processors are connected to port0 and port1 of a shared DPRAM (refer Fig). The block
named TestnSet maintains two special 1 bit registers sreg0 and sreg1 and two 1 bit flag
registers, flag0 and flag1. If the control bit of P0 goes high with the address value as say
A, then the content of the memory is brought to the sreg0 and flag0 is set high. If P1s
control bit also goes high and address value is also A, then P1 busy should be high.
Otherwise there is an error. Irrespective of what happens to P1, the sreg0 register will be
checked and if the value is 0, the content of data0 bus will be written to the address A. If
the sreg0 register is 1, no write takes place.
a) Write the BFM tasks for read memory and write memory.
b) Write a testcase using BFM tasks to do write and read operation of both processors.

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[10]

8.

Communications (on both sides) takes place by means of a 4-phase handshaking as

[10]

follows:
When the sender has data to send to the receiver, it initiates a transfer by putting the data
on the data bus and asserting StoB_REQ (Server to Buffer REQuest). If BUF is free, it
reads the data and asserts BtoS_ACK (Buffer to Server ACKnowledge). Otherwise the
sender waits. After seeing BtoS_ACK, the sender may release the data bus and deassert
StoB_REQ. To conclude the transaction, BUF deasserts BtoS_ACK.
When BUF has data, it initiates a transfer to the receiver by putting the data on the data
bus and asserting BtoR_REQ (Buffer to Receiver REQuest). If the receiver is ready, it
reads the data and asserts RtoB_ACK (Receiver to Buffer ACKnowledge). Otherwise,
BUF waits. After seeing RtoB_ACK, BUF may release the data bus and deassert
BtoR_REQ. To conclude the transaction, the receiver deasserts RtoB_ACK.

a) Develop the BFM Tasks for buffer module.

b) Develop suitable verification methodology and test scenarios.
9.

a) A communication device receives a clock upto M MHz. Write a verilog code snippet

[5]

to verify that the clock meets this timing requirement.

b) What is the significance of seed in randomization and draw the random verification
methodology?

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[5]

10.

[10]

Define the code coverage metrics and write the different coverage metrics in the
following code
module

s1: begin

else begin

sequence_detector( clk,rst,

if (x==1'b1) begin

ns = s0;

x, y);

ns = s1;

y = 1'b0;

input x,clk,rst;

y = 1'b0;

end

output y;

end

end

reg y;

else begin

endcase

reg [1:0] ns, ps;

ns = s2;

end

parameter s0 = 2'b00;

y = 1'b0;

always @( posedge

parameter s1 = 2'b01;

end

clk or posedge rst)

parameter s2 = 2'b10;

end

begin

always @ ( x or ps)
begin

s2: begin

if ( rst)

if (x==1'b1) begin

ps <= s0;

case( ps)

ns = s1;

else

s0: begin

y=1'b1;

ps <= ns;

if (x==1'b1) begin

end

ns = s1;

end
endmodule

y = 1'b0;
end
else begin
ns = s0;
y = 1'b0;
end
end

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