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Introduction
Relay coordination
Electromechanical
Solid State
Hybrid
Numerical (Microprocessor)
Time-Overcurrent Relays
Time-Overcurrent Relays
BREAKER OPERATING
TIME
B1
5 Cycles
CT
RATIO
400:5
RELAY
TYPE
CO-8
B2
5 Cycles
200:5
CO-8
B3
5 Cycles
200:5
CO-8
11.0
0.95
4.0
0.95
6.0
0.95
3000
2200
2000
1500
1000
700
I load =
I CT
6 *10 6
3
= 100.4 A
3 * 34.5 * 10
100.4
=
= 2.51A
(200 / 5)
I load =
I CT
(6 + 4) * 10 6
3
= 167.35 A
3 * 34.5 * 10
167.35
=
= 4.18 A
(200 / 5)
I load =
I CT
(6 + 4 + 11) * 10 6
3
3 * 34.5 * 10
351.43
=
= 4.39 A
(400 / 5)
= 351.43 A
Polar unit
mho
Offset mho
Simple blinder
reactance
Z load =
120
3 *5
= 13.86
where
ZR
2
Z R Z R
Z=
2
2
Z R
is the radius from the offset point
2
(Typo in the book)
of
Z X = Z R cos( R X )
where
ZX is the impedance from the origin to any point on the
circle at angle X.
Vzy
nZ 1L ( I 1 + I 2 ) + nZ 0 L I 0
I1 + I 2 + I 0
(typo)
For voltage compensation, subtract out nZ1L(I1+I2) and use I0 (not Ia),
then:
Vag nZ 1L ( I 1 + I 2 ) nZ 0 L I 0
ZR =
=
= nZ 0 L
I0
I0
Vag
Ia
Vag
I a + mI 0
where m =
= nZ1L
Z 0 L Z 1L
Z 1L
I relay
3I
= nZ 1L + R fault 0
I
I relay
relay
( Z Z 1L )
I a + I 0 0L
Z 1L
=
I Z
1 + 0E 0M
I 0 Z 1L
Vag
(typo)
where I0E is the zero sequence current in the parallel line and Z0M is the
mutual coupling impedance between two lines.
Introduction
In
Introduction
Each
Surge
Supressor
Signal
Conditioning
Sample/Hold
A/D Conversion
& Multiplexer
Contacts O/P
Surge
Supressor
Output
Driver
Signal
Conditioning
Central
Processor
Unit
Communication
Module
Memory Sub-System
RAM, EPROM, EEPROM
Surge
Supressor
Q=1
Q=5
-50
Q=10
-100
Frequency (rad/sec)
Q=10
Q=1
0
Q=5
-90
Frequency (rad/sec)
1st Order
2nd Order
3rd Order
-50
-100
Frequency (rad/sec)
-90
1st Order
-180
2nd Order
270-
3rd Order
Frequency (rad/sec)
M
A/D
U
X
(a)
S/H
S/H
U
X
(c)
A/D
(b)
M
S/H
S/H
A/D
S/H
S/H
A/D
A/D
S/H
A/D
(d)
B
U
F
F
E
R
Conversion Techniques
Conversion Techniques
Conversion Techniques
Word Length
Quantization Error of a N-bit A/D Converter is Equal to
2-N
Gain, and Offset Errors
Actual
Output
Quantization
Error
x
Offset
Error
10%
50%
90%
Input
Filtering
Non-Recursive Filter
Ym = X m + X m2
Ym = X m X m2
Ym = X m + 3 X m1 + X m2
3, 9,
DC, 6, 12,
5, 7, ...
Filtering
Recursive Filter
Kalman Filter
Fast Fourier Transform
Curve Fitting
Walsh Filter
|V |2 = vm2 + vm2 3
|V |2 = ( vm2 + vm2 1 2vm vm1 cos T ) / sin 2 T
W2
W1
Algorithms
Making Process
Protocol
Checking
2t + s + 1 < dmin
Checking
I=01101100
J=11000100
d(I, J) = 3
Checking
dmin=4
Detection Algorithms
Parity Check
Even parity
Odd parity
Check Sum
CRC
LRC
CX-ORC
Correction Algorithm
Hamming code
i3 i2 i1 i0 c2c1c0
1000111
G= 0 1 0 0 1 1 0
0010101
0001011
1110100
H= 1 1 0 1 0 1 0
101100 1
Correction Algorithm
Hamming code
c2: even parity check of i3, i2, i1
c1: even parity check of i3, i2, i0
c0: even parity check of i3, i1, i0
Transmit code word, c = iG
HcT = 0
If the receiving code, d, with error
d=c+e
Syndrome, s = HdT = HeT
Correction Algorithm
Syndrome table
Syndrome
000
001
010
100
011
101
110
111
Meaning
No error
Error in c0
Error in c1
Error in c2
Error in i0
Error in 11
Error in i2
Error in i3
Correction Algorithm
Code length: n = 2m - l -1
Number of information bits: k = 2 m - m - l -1
Number of check bits m = n - k
100001111
010001110
G= 001001101
000101011
000010111
Intelligence
Multiple Function Relays
Common Hardware Configuration
Software (Firmware) Driven Protective
Function(s)
Stronger Communication Capability
Serve as Pre-/Post-Fault Recorder