Ne 58633 NXP Head Amplifier Data Sheet

NE58633
Noise reduction class-D headphone driver amplifier

Rev. 03 19 January 2010
Product data sheet
1. General description
The NE58633 is a stereo, noise reduction, class-D, Bridge-Tied Load (BTL) headphone
driver amplifier. Each channel comprises a class-D BTL headphone driver amplifier, an
electret microphone low noise preamplifier, feedback noise reduction circuit and a music
amplifier input.
The NE58633 operates with a battery voltage of 0.9 V to 1.7 V. The chip employs an
on-chip DC-to-DC boost converter and internal Vref voltage reference which is filtered and
output to ground for noise decoupling. It features mute control and plop and click
reduction circuitry. The gain of the microphone amplifier and filter amplifier is set using
external resistors. Differential architecture provides increased immunity to noise.
The NE58633 is capable of driving 800 mVrms across a 16 or 32 load and provides
ElectroStatic Discharge (ESD) and short-circuit protection.
It is available in the 32-pin HVQFN32 (5 mm 5 mm 0.85 mm) package suitable for
high density small-scale layouts and is an ideal choice for noise reduction headphones
and educational audio aids.
2. Features
Low current consumption of 4.4 mA

0.9 V to 1.7 V battery operating voltage range
1 % THD+N at VO = 1 VM driving 16 with a battery voltage of 1.5 V
10 % THD+N at 800 mVrms output voltage driving 16 and 32 loads with a battery
voltage of 1.5 V
Output noise voltage with noise reduction circuit typically 31 mVrms for Gv(cl) = 25 dB
On-chip mute function
Plop and click reduction circuitry
Class-D BTL differential output configuration
Electret microphone noise reduction polarization amplifier with external gain
adjustment using resistors
Music and filter amplifier with external gain adjustment using resistors
DC-to-DC converter circuitry (3 V output) with 2.5 mA (typical) load current
Internal voltage reference pinned out for noise decoupling
Available in HVQFN32 package
NE58633
NXP Semiconductors
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
NE58633BS
Description
Version
HVQFN32 plastic thermal enhanced very thin quad flat package; SOT617-1
no leads; 32 terminals; body 5 5 0.85 mm
4. Block diagram
MA_OUTR
21
internal
oscillator
14, 19
PGNDR
AVDD
MA_INRN
MA_INRP
NMIC_OUTR
18
22
PWM
23
24
1 k
NMIC_INRP
OUTRN
MUTE
10 k
Vref
NMIC_INRN
15
H-BRIDGE
OUTRP
17
Vref
16
PVDDR
PVDDR
AVDD
25
NE58633
26
20
5 k
VREF
MUTE
AGND
B_IN
BS
VBAT
27
Vref
28
DC-to-DC
BOOST
CONVERTER
29
AVDD
31
MA_INLP
MA_INLN
MA_OUTL
AGND
internal
oscillator
Vref
AVDD
10 k
MUTE
8
10
7
H-BRIDGE
32
AGND
1
PVDDL
PVDDL
AVDD
PWM
1 k
NMIC_OUTL
12
Vref
Vref
Vref
NMIC_INLN
MUTE
CONTROL
30
5 k
NMIC_INLP
Vref
BUFFER
OUTLN
OUTLP
MUTE
6, 11
PGNDL
2
3
4
5
001aaj506
Fig 1.
Block diagram
NE58633_3
Product data sheet
NXP B.V. 2010. All rights reserved.
2 of 27
NE58633
NXP Semiconductors
5. Pinning information
25 NMIC_INRN
26 NMIC_INRP
27 AGND
28 B_IN
29 BS
30 VBAT
terminal 1
index area
31 NMIC_INLP
32 NMIC_INLN
5.1 Pinning
NMIC_OUTL
24 NMIC_OUTR
MA_INLP
23 MA_INRP
MA_INLN
22 MA_INRN
MA_OUTL
AGND
PGNDL
19 PGNDR
OUTLP
18 OUTRP
PVDDL
17 PVDDR
21 MA_OUTR
PVDDR 16
20 VREF
OUTRN 15
PGNDR 14
n.c. 13
MUTE 12
PGNDL 11
9
PVDDL
OUTLN 10
NE58633BS
002aad751
Transparent top view
Fig 2.
Pin configuration for HVQFN32
5.2 Pin description

Table 2.
Pin description
Symbol
Pin
Description
NMIC_OUTL
noise reduction microphone preamplifier output, left channel
MA_INLP
music amplifier positive input, left channel
MA_INLN
music amplifier negative input, left channel
MA_OUTL
music amplifier output, left channel
AGND
analog ground
PGNDL
power ground, headphone driver, left channel
OUTLP
headphone positive output, left channel
PVDDL
8, 9
battery supply voltage, headphone driver output, left channel
OUTLN
10
headphone negative output, left channel
PGNDL
11
power ground, headphone driver, left channel
MUTE
12
mute, headphone outputs (active LOW)
n.c.
13
not connected internally; connect pin to ground
PGNDR
14
power ground, headphone driver, right channel
OUTRN
15
headphone negative output, right channel
PVDDR
16, 17
battery supply voltage, headphone driver output, right channel
OUTRP
18
headphone positive output, right channel
PGNDR
19
power ground, headphone driver, right channel
VREF
20
internal voltage reference output
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
Table 2.
Pin description continued
Symbol
Pin
Description
MA_OUTR
21
music amplifier output, right channel
MA_INRN
22
music amplifier negative input, right channel
MA_INRP
23
music amplifier positive input, right channel
NMIC_OUTR
24
noise reduction microphone preamplifier output, right channel
NMIC_INRN
25
noise reduction microphone preamplifier negative input, right

channel
NMIC_INRP
26
noise reduction microphone preamplifier positive input, right

channel
AGND
27
ground, analog
B_IN
28
boost converter input
BS
29
boost converter switching transistor collector
VBAT
30
battery supply voltage
NMIC_INLP
31
Noise reduction microphone preamplifier positive input, left

channel
NMIC_INLN
32
Noise reduction microphone preamplifier negative input, left

channel
6. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb = 25 C, unless otherwise specified.
Symbol
Parameter
Conditions
VBAT
pins VBAT, PVDDL, PVDDR
VI
input voltage
Min
Max
Unit
in active mode
0.3
+1.7
in mute mode
0.3
+1.7
0.3
+2.0
Tamb
ambient temperature
operating
70
Tj
junction temperature
operating
150
Tstg
storage temperature
150
VESD
electrostatic discharge
voltage
human body model
2500
machine model
150
7. Recommended operating conditions

Table 4.
Operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VBAT
AVDD, PVDD
0.9
1.7
Vi(cm)
common-mode input
voltage
music and noise reduction

amplifier inputs
0.2
Vbst 1
VIH
HIGH-level input voltage
unmuted; MUTE
VBAT
VIL
LOW-level input voltage
muted; MUTE
0.8
Tamb
ambient temperature
operating
70
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
8. Characteristics
Table 5.
Electrical characteristics
Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
|VO(offset)|
output offset voltage
measured differentially; inputs AC

grounded; Gv(cl) = 25 dB;
VBAT = 0.9 V to 1.7 V
25
mV
|VI(offset)|
input offset voltage
music amplifier and noise reduction

microphone amplifier;
measured differentially
mV
Zi
input impedance
music amplifier, non-inverting terminal;

VBAT = 0.9 V to 1.7 V
10
inverting terminal noise reduction
non-inverting terminal noise reduction
microphone preamplifier;
VBAT = 0.9 V to 1.7 V
ILI
input leakage current
music amplifier; inverting terminal

VBAT = 0.9 V to 1.7 V
500
nA
VOH
HIGH-level output voltage

microphone preamplifier; IOH = 1 mA;
VBAT = 0.9 V to 1.7 V
2.6
VOL
LOW-level output voltage

microphone preamplifier; IOH = 1 mA;
VBAT = 0.9 V to 1.7 V
0.35
Vref
reference voltage
VBAT = 0.9 V to 1.7 V
0.5Vbst
VBAT = 1.7 V
5.0
6.0
mA
VBAT = 1.5 V
6.0
mA
VBAT = 1.3 V
7.0
mA
supply current
IDD
AC grounded; no load
[1]
VBAT = 1.05 V
8.0
mA
VBAT = 0.9 V
9.0
11
mA
2.8
RDSon
drain-source on-state
resistance
fsw
switching frequency
VBAT = 0.9 V to 1.7 V
250
300
350
kHz
Gv(cl)
closed-loop voltage gain
with noise reduction microphone circuit;

VBAT = 0.9 V to 1.7 V; RF = 18 k
25
dB
Vth(mute)
mute threshold voltage
VBAT = 0.9 V to 1.7 V

LOW-level; active LOW (muted)
0.8
HIGH-level; inactive HIGH (unmuted)
1.0
[1]
VBAT = 0.9 V to 1.7 V; no load
Music amplifier at unity gain; noise preamplifier at 25 dB gain; noise preamplifier output connected to corresponding inverting input of
music amplifier; non-inverting inputs.
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
Table 6.
Operating characteristics
Symbol
Parameter
Conditions
Vo
output voltage variation
per channel; RL = 16 ; f = 1 kHz;

THD+N = 10 %
VBAT = 1.7 V
Po
THD+N
output power
total harmonic
distortion-plus-noise
Min
Typ
Max
Unit
800
mVrms
VBAT = 1.5 V
800
mVrms
VBAT = 1.05 V
550
mVrms
RL = 16 ; VBAT = 1.5 V
40
mW
RL = 32 ; VBAT = 1.5 V
20
mW
RL = 16 ; VBAT = 1.05 V
19
mW
Vo = 1 Vpeak; f = 1 kHz;
VBAT = 1.5 V to 1.7 V
1.0
Vo = 620 mVpeak; f = 1 kHz;

VBAT = 1.05
1.0
per channel; f = 1 kHz;

THD+N = 10 %
Gv(ol)
open-loop voltage gain

VBAT = 1.5 V
100
dB
ct
crosstalk attenuation
f = 1 kHz; VBAT = 1.5 V; Rg = 1 k;

RL = 16 ; Vo = 800 mVrms
40
50
dB
SVRR
supply voltage ripple

rejection
Vbst(ripple) = 100 mVrms;

Gv(cl) = 25 dB; f = 1 kHz
VBAT = 0.9 V
30
40
dB
VBAT = 1.5 V
60
dB
Zi
input impedance
Gv(cl) = 25 dB (from noise reduction
microphone to class-D output)
S/N
signal-to-noise ratio
VBAT = 1.5 V; Vo = 800 mVrms;

RL = 16 ; f = 1 kHz
70
dB
Vn(i)
input noise voltage
spectral noise; VBAT = 1.5 V;

f = 20 Hz to 20 kHz; Gv(cl) = 25 dB;
Rg = 1 k
12
nV/Hz
Vn(o)
output noise voltage
VBAT = 1.5 V; f = 20 Hz to 20 kHz;

inputs AC grounded; Gv(cl) = 25 dB
no weighting
26
A weighting
20
DC-to-DC boost converter

VI
input voltage
1.05
1.7
VI(startup)min
minimum start-up input

voltage
0.9
1.05
Vbst
boost voltage
VBAT = 1.05 V to 1.7 V;

2.65 mA external load
2.75
3.1
3.45
Ibst(load)O
output load boost current
VBAT = 1.05 V to 1.7 V; Vbst > 2.8 V
2.65
mA
bst
boost efficiency
VBAT = 1.05 V to 1.7 V;

RL(tot) = 600
70
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
9. Typical performance curves

002aad921
12
IBAT
(mA)
002aad920
3.5
Vbst
(V)
3.3
8
3.1
2.9
4
2.7
0
0.8
1.1
1.4
2.5
0.8
1.7
1.1
1.4
VBAT (V)
1.7
VBAT (V)
Vbst = 3.14 V
Fig 3.
Battery supply current as a function of battery

supply voltage
Fig 4.
Boost voltage as a function of battery supply

voltage
3.3
Vbst (V)
3.1
2.9
2.7
2.5
1.50
VBAT (V)
1.25
1.15
2.3
2.45 2.55
2.65 2.75
2.85 2.95
3.05 3.15
3.25
Ibst(load)O
Fig 5.
1.05
0.9
002aad917
Boost voltage performance versus battery supply voltage and output load boost current
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
80
(2)
(%)
70
002aad922
80
(2)
(%)
70
(3)
(1)
60
60
50
50
40
40
30
002aad926
(3)
(1)
30
0
4
5
RL(ext) (k)
4
5
RL(ext) (k)
(1) VBAT = 0.9 V
(1) VBAT = 1.0 V
(2) VBAT = 1.2 V
(2) VBAT = 1.3 V
(3) VBAT = 1.5 V
(3) VBAT = 1.6 V
a. Battery supply voltage = 0.9 V, 1.2 V and 1.5 V
b. Battery supply voltage = 1.0 V, 1.3 V and 1.6 V

002aad925
80
(%)
70
(3)
(1)
(2)
60
50
40
30
0
4
5
RL(ext) (k)
(1) VBAT = 1.1 V

(2) VBAT = 1.4 V
(3) VBAT = 1.7 V
c. Battery supply voltage = 1.1 V, 1.4 V and 1.7 V

Fig 6.
Efficiency as a function of external load resistance; boost voltage = 3.14 V
NE58633_3
Product data sheet
8 of 27
NE58633
NXP Semiconductors
002aae671
102
THD+N ratio
(%)
002aae729
102
THD+N ratio
(%)
(2) (3)
(1)
10
(4)
10
(1)
(2)
(3)
101
101
(4)
102
10
101
101
102
10
Po (mW)
Po (mW)
a. Rs = 0
b. Rs = 18
RL = 16 speaker load + 2 ferrite bead +

2 0 resistor + 2 27 pF shunt capacitor;
measured across 16 speaker load; fi = 1 kHz;
A-weighting filter for THD+N.
RL = 16 speaker load + 2 15 H inductor +

measured across 16 speaker; fi = 1 kHz;
A-weighting filter for THD+N.
(1) VBAT = 1.05 V
(1) VBAT = 1.05 V
(2) VBAT = 1.3 V
(2) VBAT = 1.3 V
(3) VBAT = 1.5 V
(3) VBAT = 1.5 V
(4) VBAT = 1.7 V
(4) VBAT = 1.7 V
Total harmonic distortion-plus-noise as a function of output power; 16 load
Fig 7.
002aae672
102
THD+N ratio
(%)
002aae728
102
THD+N ratio
(%)
(2) (3)
(1)
10
(4)
10
1
(1)
(2)
(3)
(4)
101
101
102
10
101
101
Po (mW)
Po (mW)
a. Rs = 0
b. Rs = 18
RL = 32 speaker load + 2 ferrite bead +

measured across 32 speaker load; fi = 1 kHz;
A-weighting filter for THD+N
RL = 32 speaker load + 2 15 H inductor +

measured across 32 speaker; fi = 1 kHz;
A-weighting filter for THD+N
(1) VBAT = 1.05 V
(1) VBAT = 1.05 V
(2) VBAT = 1.3 V
(2) VBAT = 1.3 V
(3) VBAT = 1.5 V
(3) VBAT = 1.5 V
(4) VBAT = 1.7 V
(4) VBAT = 1.7 V
Fig 8.
102
10
Total harmonic distortion-plus-noise as a function of output power; 32 load
NE58633_3
Product data sheet
9 of 27
NE58633
NXP Semiconductors
002aad958
40
G
(dB)
002aae323
40
G
(dB)
20
20
20
10
102
103
104
105
20
10
f (Hz)
Gain as a function of frequency response of

feedforward noise reduction circuit;
NMIC_INx to MA_OUTx for feedforward
application circuit
104
105
VNMIC_IN = 10 mV to 50 mV; VBAT = 1.5 V; Vbst = 3.1 V
Fig 10. Gain as a function of frequency; NMIC_INx to

MA_OUTx for feedback application circuit
NE58633_3
Product data sheet
103
f (Hz)
VNMIC_IN = 6.3 mVrms; Vbst = 3 V; VBAT = 1.5 V
Fig 9.
102
10 of 27
NE58633
NXP Semiconductors
(1)
(2)
(3)
(4)
002aad930
At start-up, no signal on music input. No pop or click. The small glitches on trace (2) are just noise from the noise reduction
amplifier feed-through. Start-up delay approximately 135 ms.
(1) VBAT switch ON to 1.5 V (50 ms; 1.0 V)
(2) Difference between trace (3) and (4), which equates to the pop or click (0.5 ms; 0.54 V)
(3) OUTLP (50 ms; 1.0 V)
(4) OUTLN (50 ms; 1.0 V)
Fig 11. Power-on delay and pop-on noise performance

(1)
(2)
(3)
(4)
002aad929
(1) 50 ms; 1.0 V

(2) 1 ms; 0.5 V
(3) 50 ms; 1.0 V
(4) 50 ms; 1.0 V
Fig 12. Pop-off click performance
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
10. Application information

10.1 General application description
The NE58633 is a stereo noise reduction IC with a boost converter output at 3.2 V with
2.5 mA load current. Using the on-chip boost converter, it operates from a single cell
alkaline battery (0.9 V to 1.7 V). The NE58633 is optimized for low current consumption at
6 mA quiescent current for VBAT = 1.5 V.
Each channel is comprised of a low noise preamplifier which is driven by an electret
microphone, a music amplifier and class-D, BTL headphone driver amplifier (see Figure 1
Block diagram).
The NE58633 output drivers are capable of driving 800 mVrms across 16 and 32
loads. THD+N performance is 1 % at VO = 1 VM and 10 % THD+N at 800 mVrms output
voltage driving 16 at a battery voltage of 1.5 V.
The internal reference voltage is set for 12 Vbst and is pinned out so it can be externally
decoupled to enhance noise performance. The NE58633 differential architecture provides
immunity to noise. The output noise is typically 26 Vrms for Gv(cl) = 25 dB.
The NE58633 provides ESD and short-circuit protection. It features mute control and
plop and click reduction circuitry.
As shown in the application circuit schematics (Figure 13 and Figure 14), the NE58633
may be used for Active Noise Reduction (ANR) in either feedforward or feedback
noise-cancelling headphones and earphones in consumer and industrial applications. The
gain and filter characteristics of the ANR circuit are set using external resistors and
capacitors.
NE58633_3
Product data sheet
12 of 27
NE58633
NXP Semiconductors
10 nF
10 k
22 k
21 MA_OUTR
PGNDR 14
2.2 k
internal
oscillator
PGNDR 19
AVDD
27 pF
PWM
22 MA_INRN
FB
Rs(1)
OUTRP 18 FB
H-BRIDGE
MUTE
47 k
100 nF
Rs(1)
OUTRN 15
23 MA_INRP
24 NMIC_OUTR
right
speaker
27 pF
PVDDR 17
10 k
AVDD
22 k
10 nF
PVDDR 16
25 NMIC_INRN
1 F
10 k
26 NMIC_INRP
VBAT
1 F
4.7 k
switch shown
in OFF position
NE58633
27 AGND
28 B_IN
100 F
1 k
29 BS
OFF
DC-to-DC
BOOST
CONVERTER
10 F
4.7 k
20
1 F
MUTE
CONTROL
30 VBAT
VBAT
VREF
AVDD
MUTE
12
right audio
input
4.7 F
1 F
390
AVDD
560
PVDDL 9
31 NMIC_INLP
1 F
10 k
10 nF
PVDDL 8
32 NMIC_INLN
22 k
1 NMIC_OUTL
AGND
AVDD
OUTLN 10
10 k
100 nF
1 F
internal
oscillator
PWM
47 k
Rs(1)
MUTE
27 pF
PGNDL 6
Rs(1)
H-BRIDGE
OUTLP 7
10 k
2.2 k
22 k
390
560
1 F
27 pF
FB
FB
2 MA_INLP
3 MA_INLN
10 nF
power
switch
ON
left audio
input
left
speaker
4 MA_OUTL
PGNDL 11
5 AGND
002aae726
(1) Select Rs value for desired power output delivered to speaker load.
Fig 13. NE58633 feedback application schematic
NE58633_3
Product data sheet
13 of 27
NE58633
NXP Semiconductors
47 nF 1.8 k
21 MA_OUTR
PGNDR 14
3.3 k
internal
oscillator
PGNDR 19
AVDD
27 pF
PWM
22 MA_INRN
FB
MUTE
3.3 k
Rs(1)
OUTRP 18 FB
H-BRIDGE
3.3 k
330 nF
Rs(1)
OUTRN 15
23 MA_INRP
24 NMIC_OUTR
right
speaker
27 pF
PVDDR 17
10 nF
AVDD
22 k
PVDDR 16
25 NMIC_INRN
8.2 k
1 F
26 NMIC_INRP
VBAT
1 F
6.8 k
switch shown
in OFF position
NE58633
27 AGND
28 B_IN
1 k
100 F
29 BS
OFF
DC-to-DC
BOOST
CONVERTER
10 F
6.8 k
1 F
10 nF
330 nF
3.3 k
3.3 k
12
AVDD
PVDDL 9
32 NMIC_INLN
PVDDL 8
22 k
1 NMIC_OUTL
right audio
input
4.7 F
31 NMIC_INLP
1 F
560
1 F
internal
oscillator
AGND
power
switch
ON
AVDD
OUTLN 10
PWM
Rs(1)
MUTE
27 pF
PGNDL 6
Rs(1)
H-BRIDGE
OUTLP 7
4 MA_OUTL
390
560
1 F
27 pF
FB
FB
2 MA_INLP
3 MA_INLN
47 nF 1.8 k
MUTE
390
1 F
8.2 k
20
AVDD
MUTE
CONTROL
30 VBAT
VBAT
VREF
left audio
input
left
speaker
PGNDL 11
3.3 k
5 AGND
002aae727
(1) Select Rs value for desired power output delivered to speaker load.
Fig 14. NE58633 feedforward application schematic
NE58633_3
Product data sheet
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NE58633
NXP Semiconductors
10.2 Power supply decoupling

The power supply pins B_IN, PVDDL and PVDDR are decoupled with 1 F capacitors
directly from the pins to ground.
10.3 Speaker output filtering considerations

The ferrite beads form a low-pass filter with a shunt capacitor to reduce radio
frequency > 1 MHz. Choose a ferrite bead with high-impedance at high frequencies and
low-impedance at low frequencies. A typical ferrite bead is 600 at 100 MHz. A shunt
capacitor is added after the ferrite bead to complete the low-pass filter. The low frequency
impedance is not as important as in power amplifiers because headphone speakers are
stabilized with a series impedance of about 18 on each output. The series resistors, Rs,
may be decreased to increase the power delivered to the speaker load. Figure 7 and
Figure 8 show the THD+N versus Po performance for Rs = 0 and Rs = 18 .
10.4 Boost converter and layout considerations

10.4.1 Boost converter operation
The boost converter operates in asynchronous mode as shown in Figure 15. As VBAT
drops, the boost converter efficiency decreases (see Figure 3 and Figure 6). The boost
converter is capable of driving 2.65 mA external load (see Figure 5).
If the NE58633 is operated without the boost converter, pins B_IN, PVDDL and PVDDR
may be powered directly from a 3 V power supply source such as 2 AAA alkaline
batteries. The VBAT pin is not used.
(1)
(2)
(3)
2 Gs/s
002aad957
(1) Positive or negative output of the class-D driver with VBAT at 1.5 V.
(2) Pin BS (VBS = Vbst).
Remark: This is a normal pulse. It does not change with VBAT but remains at the level of the boosted voltage.
(3) Current at pin B_IN (Ibst(load)O) measures approximately 40 mA peak, but averaged DC current is a few milliamperes per the
specification.
Fig 15. Switching waveform at the BS pin
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Product data sheet
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NE58633
NXP Semiconductors
10.4.2 Critical layout consideration and component selection

The trace between pin BS and the switching inductor must be kept as short as possible.
The VBAT side of the boost switching inductor is decoupled by use of a low Equivalent
Series Resistance (ESR) 10 F, 6 V capacitor. A power inductor with low ESR (typically
50 m) should be used. The boost inductor must be 22 H to ensure proper operation
over VBAT voltage. Pin B_IN is decoupled by use of a 1 F capacitor directly at the pin with
33 F to 47 F at the Vbst output at the Schottky diode.
10.5 Mute
Mute may be invoked by directly grounding the pin with a momentary switch. The MUTE
pin is active LOW. The outputs are muted automatically when VBAT is less than or equal to
0.9 V. The MUTE pin is decoupled to ground with a 1 F capacitor. The value of the MUTE
decoupling capacitor may be increased to keep outputs muted longer.
10.6 Internal reference, VREF pin

The internal reference is pinned out so it can be filtered with a capacitor to ground. The
recommended value is 1 F to 10 F. Ensure that the biasing time constant at pin VREF
does not exceed the power-on delay time or a pop-on click will heard.
10.7 Power-on delay time and pop and click performance

Power-on delay time of typically 135 ms is imposed to allow the input biasing to power-up
and stabilize. This eliminates pop-on noise for most ANR filter networks. However,
specific ANR filter circuits have longer power-on delays. The MUTE decoupling may be
increased to keep outputs muted longer and eliminate pop-on noise.
10.8 Active Noise Reduction (ANR) concepts

10.8.1 Basic concept
Noise reduction headphones utilize Passive Noise Reduction (PNR) provided by the
passive noise reduction of the headphone acoustical plant alone. The amount of PNR is
greatest at the high frequencies and least at the low frequencies. The addition of Active
Noise Reduction (ANR) greatly increases the amount of noise reduction at low
frequencies. The combined effect of PNR and ANR provides noise reduction over an
appreciable hearing range. Figure 16 shows the combined effect of both PNR and ANR in
an over-the-ear noise-cancelling FB headphone.
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002aad911
10
(dB)
(dB)
10
10
20
20
30
30
40
102
002aad912
10
103
104
40
102
103
f (Hz)
a. Passive attenuation left
b. Passive attenuation right

002aad913
10
(dB)
002aad914
10
(dB)
10
10
20
20
30
30
40
102
103
104
40
102
103
f (Hz)
104
f (Hz)
c. Total attenuation left
d. Total attenuation right

002aad915
10
(dB)
002aad916
10
(dB)
10
10
20
20
30
30
40
102
104
f (Hz)
103
104
40
102
103
f (Hz)
e. Active attenuation left
104
f (Hz)
f. Active attenuation right
Fig 16. Combined noise reduction (PNR + ANR) of typical over-the-ear FB application
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10.8.2 Feedforward circuit

10.8.2.1
Conceptual diagram of feedforward application

Figure 17 shows the typical feedforward application diagram in which the noise cancelling
microphone samples the noise outside the acoustic plant of the headphone or earphone.
external noise
human head
E
electronic
compartment
ear
2
noise detection
microphone
FILTER
AMP
H.P. driver
NE58633
transducer
(speaker)
acoustic
compartment
or plant
headphone
shell or body
002aad927
Fig 17. Feedforward conceptual diagram
This method produces a noise-cancelling signal that tries to replicate the noise in the
acoustical plant at the loudspeaker and entrance to the ear. The replication is never exact
because the microphone is located outside the headphones; the noise sampled is not a
perfect replica of the noise inside the ear cup, which is altered by passing through the ear
cup as well as by the internal reflections. In fact, in some cases the anti-noise may
actually introduce noise inside the headphones.
The headphone loudspeaker or transducer is used to send the normal audio signal as well
as the feedforward signal providing noise cancellation. The microphone detects the
external noise and its output is amplified and filtered, and phase is inverted by the low
noise preamplifier and music amplifier in the NE58633.
10.8.2.2
Feedforward demo board schematic

The evaluation demo board uses a typical filter design and may not yield the optimal noise
cancelling performance for a given headphone mechanical-acoustical plant.
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10.8.3 Feedback circuit

10.8.3.1
Conceptual diagram of feedback application

Figure 18 shows the typical feedback application diagram in the which the noise
cancelling microphone samples the noise and music inside the acoustical plant.
acoustic
compartment
or plant
noise detection
microphone
human head
ear
2
electronic
compartment
FILTER
AMP
H.P. driver
NE58633
transducer
(speaker)
E
headphone
shell or body
external noise
002aad928
Fig 18. Feedback conceptual diagram
The feedback solution employs a low cost, battery operated analog Active Noise
Reduction (ANR) technique. The topology uses negative feedback circuitry in which the
noise reduction microphone is placed close to the ear and headphone loudspeaker. By
detecting the noise with the microphone in the position closer to the ear, a noise
cancelling effect with high accuracy is realized. This technique produces a noise
cancelling signal that always minimizes the noise in the ear canal or entrance to the ear
canal. The audio signal is analyzed with exact timing with the noise cancelling signal. The
noise cancelling signal increases with increasing noise level.
The headphone loudspeaker or transducer is used to send the normal audio signal as well
as the feedback signal providing noise cancellation. The microphone is placed near the
loudspeaker and its output is amplified, filtered, and phase inverted by the feedback
network and sent back to the loudspeaker.
The design of the feedback filter for a given headphone plant involves a trade-off between
performance on one hand and stability and robustness with respect to variations of the
headphone plant on the other. Traditional feedback design methods use filter elements
such as, lead, lag and notch filters which are appropriately tuned to shape the audio
response of the system to obtain good performance with sufficient stability margins.
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NXP Semiconductors
Since the attenuation performance of an analog ANR headphone is defined in the design
stage, it has limited applicability to work in different environments. Overall noise cancelling
performance is achieved by first characterizing the passive attenuation of headphone
plant and then designing the ANR circuitry to obtain the optimal overall noise reduction
performance and stability. Figure 16 shows combined noise reduction results of typical
over-the-ear feedback headphone. The combined noise reduction is the sum of the PNR
of the plant and the active noise reduction of the feedback filter circuit.
10.8.3.2
Feedback demo board schematic

The evaluation demo board embodies a typical filter design and may not yield the optimal
noise cancelling performance for a given headphone mechanical-acoustical plant.
11. Test information
15 H
AP585
AUDIO
ANALYZER
INxP
OUTxP
RL
DUT
INxN
OUTxN
15 H
AUX0025
30 kHz
LOW-PASS FILTER
POWER
SUPPLY
AP585
MEASUREMENT
INPUTS
002aad417
Fig 19. NE58633 test circuit
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12. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
SOT617-1
terminal 1
index area
A
A1
E
detail X
e1
e
1/2
e b
y1 C
v M C A B
w M C
16
L
17
e2
Eh
1/2
1
terminal 1
index area
24
32
25
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)

UNIT
A(1)
max.
A1
D (1)
Dh
E (1)
Eh
e1
e2
y1
mm
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Fig 20. Package outline SOT617-1 (HVQFN32)

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13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 Surface mount reflow
soldering description.
13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering

Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities

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13.4 Reflow soldering

Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)

Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 8.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)

Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 21.
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maximum peak temperature

= MSL limit, damage level
temperature
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

Surface mount reflow soldering description.
14. Abbreviations
Table 9.
Abbreviations
Acronym
Description
ANR
Active Noise Reduction
BTL
Bridge Tied Load
DUT
Device Under Test
ESD
ElectroStatic Discharge
ESR
Equivalent Series Resistance
FB
FeedBack
RMS
Root Mean Squared
PNR
Passive Noise Reduction
PWM
Pulse Width Modulation
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15. Revision history

Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NE58633_3
20100119
Product data sheet
NE58633_2
Modifications:
Table 3 Limiting values: added VESD (electrostatic discharge voltage) limits
Figure 5 updated
Table 6 Operating characteristics, bst (boost efficiency): Typical value changed from 80 % to
70 %
Figure 13 NE58633 feedback application schematic updated
Figure 14 NE58633 feedforward application schematic updated
Section 10.4.2 Critical layout consideration and component selection, 4th sentence changed from
The boost inductor must be 22 H minimum and 47 H maximum to ensure proper operation. to
The boost inductor must be 22 H to ensure proper operation over VBAT voltage.
Section 10.5 Mute: added 5th sentence.
Section 10.7 Power-on delay time and pop and click performance:
2nd sentence re-written
added new 3rd and 4th sentences
NE58633_2
20090525
Product data sheet
NE58633_1
NE58633_1
20090122
Product data sheet
NE58633_3
Product data sheet
25 of 27
NE58633
NXP Semiconductors
16. Legal information

16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term short data sheet is explained in section Definitions.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customers own risk.
Applications Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NE58633_3
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18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
10.1
10.2
10.3
10.4
10.4.1
10.4.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical performance curves . . . . . . . . . . . . . . . 7
Application information. . . . . . . . . . . . . . . . . . 12
General application description . . . . . . . . . . . 12
Power supply decoupling . . . . . . . . . . . . . . . . 15
Speaker output filtering considerations. . . . . . 15
Boost converter and layout considerations. . . 15
Boost converter operation . . . . . . . . . . . . . . . 15
Critical layout consideration and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.5
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.6
Internal reference, VREF pin . . . . . . . . . . . . . 16
10.7
Power-on delay time and pop and click
performance . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.8
Active Noise Reduction (ANR) concepts . . . . 16
10.8.1
Basic concept . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.8.2
Feedforward circuit . . . . . . . . . . . . . . . . . . . . . 18
10.8.2.1 Conceptual diagram of feedforward
application . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.8.2.2 Feedforward demo board schematic . . . . . . . 18
10.8.3
Feedback circuit . . . . . . . . . . . . . . . . . . . . . . . 19
10.8.3.1 Conceptual diagram of feedback application . 19
10.8.3.2 Feedback demo board schematic . . . . . . . . . 20
11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 20
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
13
Soldering of SMD packages . . . . . . . . . . . . . . 22
13.1
Introduction to soldering . . . . . . . . . . . . . . . . . 22
13.2
Wave and reflow soldering . . . . . . . . . . . . . . . 22
13.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22
13.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23
14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
16.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
16.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.4
17
18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contact information . . . . . . . . . . . . . . . . . . . . 26
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.
NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 January 2010
Document identifier: NE58633_3

Ne 58633 NXP Head Amplifier Data Sheet

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NE58633

Noise reduction class-D headphone driver amplifier

Product data sheet

Low current consumption of 4.4 mA

Noise reduction class-D headphone driver amplifier

Product data sheet

NXP B.V. 2010. All rights reserved.

Rev. 03 19 January 2010

Noise reduction class-D headphone driver amplifier

Transparent top view

Pin configuration for HVQFN32

5.2 Pin description

noise reduction microphone preamplifier output, left channel

music amplifier positive input, left channel

music amplifier negative input, left channel

music amplifier output, left channel

power ground, headphone driver, left channel

headphone positive output, left channel

battery supply voltage, headphone driver output, left channel

headphone negative output, left channel

power ground, headphone driver, left channel

mute, headphone outputs (active LOW)

not connected internally; connect pin to ground

power ground, headphone driver, right channel

headphone negative output, right channel

battery supply voltage, headphone driver output, right channel

headphone positive output, right channel

power ground, headphone driver, right channel

internal voltage reference output

Product data sheet

NXP B.V. 2010. All rights reserved.

Rev. 03 19 January 2010

Noise reduction class-D headphone driver amplifier

Pin description continued

music amplifier output, right channel

music amplifier negative input, right channel

music amplifier positive input, right channel

noise reduction microphone preamplifier output, right channel

noise reduction microphone preamplifier negative input, right

noise reduction microphone preamplifier positive input, right

boost converter input

boost converter switching transistor collector

battery supply voltage

Noise reduction microphone preamplifier positive input, left

Noise reduction microphone preamplifier negative input, left

battery supply voltage

pins VBAT, PVDDL, PVDDR

human body model

7. Recommended operating conditions

battery supply voltage

music and noise reduction

HIGH-level input voltage

LOW-level input voltage

Product data sheet

NXP B.V. 2010. All rights reserved.

Rev. 03 19 January 2010

Noise reduction class-D headphone driver amplifier

output offset voltage

measured differentially; inputs AC

input offset voltage

music amplifier and noise reduction

music amplifier, non-inverting terminal;

inverting terminal noise reduction