EXPERIMENT NO.

2
Aim: Short-circuit current variation with output load and input signal slope for a CMOS inverter driving a
capacitive load.
Theory:

When the input signal switches, there is a short duration in which the input level is between
and and both transistors are turned on. This causes a short-circuit current from to ground and
dissipates power. The time variation of the short-circuit current during signal transition is shown in Figure
2. The shape of the short-circuit current curve is dependent on several factors:
1. The duration and slope of the input signal.
2. The I-V curves of the P and N transistors, which depend on their sizes, process technology,
temperature, etc.
3. The output loading capacitance of the inverter.
1. Short-circuit Current Variation with Output Load
Theory:
Consider the case when the input voltage is falling and the output voltage is rising. If the output
capacitance is large, the output voltage barely rises above zero and the voltage across the source and drain
of the N transistor is only slightly above zero. The low source-drain potential difference results in small
short-circuit current. Conversely, if the output capacitance is small, the output voltage rises faster and the
source-drain voltage is much higher, causing a larger short-circuit current.
To see the effects of output capacitance on short-circuit current, we ran several SPICE
simulations with different capacitance values while keeping all conditions (signal slope, temperature, etc.)
constant. In this experiment, we again keep all conditions identical and vary only the output capacitance.
This time, we measure the total current, i.e., the sum of short-circuit current and the capacitance charging
or discharging current. The short-circuit and total currents are plotted in Figure 3. and Figure 4.
respectively.

We observe that the short-circuit current envelope is the largest when the output capacitance is
the smallest. As the output capacitance increases, the current envelope becomes smaller and eventually
approaches zero. However, the duration of the short-circuit current is independent of the output
capacitance because it depends on the input signal slope only. The results also show that when the output
capacitance is increased, the total current always increases in peak as well as duration. This means that
increasing the output capacitance decreases the short-circuit power dissipation but the sum of capacitive
and short-circuit power increases. Therefore, capacitance is always the enemy of power efficiency and a
low power digital design should always strive to reduce loading capacitance.
To understand the effects of increasing output capacitance on short-circuit current capacitor
current and total current + , we refer to the current envelopes of the SPICE simulations shown
in Figure 3. and Figure 4.. We note the width (the duration in which the current is non-zero), peak and the
integration of the current envelope over time, which corresponds to the energy dissipated per transition.
The observations are summarized in the following table: