A Low Power 4-bit Interleaved Burst Sampling ADC

for Sub-GHz Impulse UWB Radio

Xiaodong Zhang and Magdy Bayoumi
The Center for Advanced Computer Studies
University of Louisiana at Lafayette
Lafayette, Louisiana 70504
Email: {xxz0050, mab}@cacs.louisiana.edu
AbstractThis paper presents a low power 4-bit ADC for subGHz Ultra Wideband (UWB) receivers. The power efficiency is
achieved by taking advantage of the low duty cycle feature of
UWB impulse. After the synchronization is achieved, the burstmode sampling approach is employed to avoid unnecessary
operations. So, the ADC only samples at the time when a pulse
is expected and stays in standby during the rest of the time. The
proposed burst sampling ADC employs five interleaved pipeline
flash ADCs controlled by a low duty cycle 25 MHz sampling
clock with five different phases. The resistor ladder reference
circuit is eliminated by using a modified Quantum Voltage
comparator, which can generate the reference voltages
internally. The proposed ADC has been designed and simulated
by using TSMC 0.18m CMOS process. Simulation results
show that the proposed 4-bit ADC can operate at 1G sample/s
for UWB impulse with power consumption of 7.6 mW.

I.

INTRODUCTION

Impulse UWB (Ultra Wideband) technology has great

potential for low-power, low-cost radio as it transmits
information through short base band pulses without
employing a carrier. It can also provide a low probability of
detection, strong multi-path fading resistance, and accurate
location awareness, which make it a promising radio for
wireless communication. The FCC has defined UWB in three
bands: 0~960 MHz, 3.1~10.6 GHz and 24~29 GHz [1]. While
the majority of attention is focused on high-speed
communications in the 3.1 GHz to 10.6 GHz band over very
short distances, there is also interest in power efficient low
data rate applications. The work focuses on the low
frequency band as it has a longer transmit distance, lower
power
consumption,
and
lower
complexity
of
implementation, suitable for low data rate applications such as
wireless sensor networks, RFID, etc. [2].
One of the biggest challenges of the impulse UWB radio
architecture is the ADC design. The ADC for impulse UWB
has to sample into the Giga Samples Per Second (GSPS)
range in order to capture information carried by the nanosecond impulses, which in turn has the potential to consume
enormous amounts of power. Fortunately, the commonly used

1-4244-0921-7/07 $25.00 2007 IEEE.

modulation schemes such as PAM, PPM, BPSK, and OOK do

not need a high resolution ADC. According to [3] and [4] the
4-bit resolution is sufficient for impulse UWB. Even at low
resolution, a high speed ADC still consumes a lot of power
[5]-[9]. To ease the ADC requirement for UWB radio, the
frequency domain approach, which performs ADC in the
frequency domain instead of the time domain, was proposed
in [10] and [11]. However, it redirects the design challenge to
multiple LNAs and band-pass filters and is too complex to
implement for low cost, low power applications.
By taking the low duty cycle feature of impulse UWB
radio for low data rate applications, we propose a low power
4-bit ADC based on the burst-mode sampling approach. It
only samples the analog input signal at the time when a pulse
is expected; otherwise it stays in standby mode to save power.
This paper is organized as follows: Section II describes the
time-interleaved burst sampling pipelined ADC architecture.
Section III presents the CMOS circuit implementation of the
proposed architecture, Section IV reports the simulation
results, and finally, we conclude the paper in section V.
II.

TIME-INTERLEAVED BURST SAMPLING

PIPELINED ADC ARCHITECTURE

Impulse UWB radio transmits information through nanosecond order pulses. For low data rate applications, the duty
cycle of pulses is usually less than 10%. In other words, if the
ADC samples the input signal continuously, over 90% of the
sampled data is useless, which is a high waste of resource.
Therefore, as long as the timing pattern of the baseband
pulses is known, the burst-mode sampling can be employed to
reduce the power consumption [12]. As shown in Figure 1,
the power saving of burst sampling is obtained by keeping the
ADC in standby mode when there is no pulse expected. For a
sub-GHz impulse UWB radio with a pulse rate of 25 MHz,
the time between two consecutive pulses is 40 nanoseconds
and the width of each single pulse is only several
nanoseconds. Therefore over 75% of unnecessary operations
including sampling, comparing, and encoding will be saved if
the burst mode sampling is employed for power optimization.

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Consequently, digitizing valueless noise information is

avoided, which will also save the power consumption of the
digital back-end as the processor can run at the relatively low
frequency as long as the sampling window is synchronized
with the timing of the impulse signal.

impulse UWB signals. Fortunately, after the synchronization

is achieved, the timing pattern is fixed for some modulation
schemes such as BPSK and PAM. As shown in Figure 2, the
synchronization block is indispensable for almost every
impulse UWB receiver [3] [5] [13]. During initialization, the
correlation bank is responsible for establishing the
synchronization through the preamble of the UWB packet.
After the synchronization is achieved, it is maintained by the
timing-tracking loop. With correct timing, the ADC can work
in the burst-sampling mode without loss of information.
Please note that the burst sampling approach can only be used
for some modulation schemes where the timing information is
fixed such as PAM and BPSK, but it may not work well for
others modulation schemes like PPM and OOK.

Figure 1.
Figure 1. Burst sampling low duty cycle impulse UWB signals

Figure 2. The block diagram of an impulse UWB transceiver

Figure 4. Timing of pipelined interleaved ADC

Figure 3. Proposed burst sampling interleaved ADC architecture

As we can see, timing plays a critical role for burst

sampling ADC. Without correct timing, the data collected by
the burst sampling ADC is valueless. Therefore the timing
generation and tracking blocks are required for burst sampling

The architecture of proposed burst sampling ADC is

shown in Figure 3. It consists of five interleaved flash ADCs.
Each one only samples 1ns of a 4ns pulse at a different phase
of the sampling clock. The time difference between two
consecutive sampling clocks is also 1ns. Therefore, five such
burst-sampling clocks could cover a 4-ns pulse allowing the
sampling rate to reach to 1G sample/s during the time when
the pulse is expected. The evenly spaced sampling clock can
be further explored to build a pipelined ADC to increase the
data throughput. In addition to providing the sample clock for
track and hold, the sampling pulse (except for the first one)
can be used to control the comparison and encoding of the
previous sample. The five flash ADCs are pipelined at 4
stages: 1) The track and hold, 2) The comparator, 3) The
thermometer code to Gray code encoder, and 4) The Gray
code to binary code decoder. The timing of the timeinterleaving pipelined ADC is shown in Figure 4. We can see
that the digitized output is available 4ns after the analog input
is held by the track and hold circuit and the whole 4 ns UWB
impulse will be digitized in 9ns. The digitized outputs have to

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be resynchronized at the registers before sending to the backend. Note that the frequency of the sampling clock is the same
as the UWB pulse rate. Lets take 25MHz for example; the
ADC can stay in standby mode for 31ns, which leads to about
77% of power savings.
Another advantage of burst sample pipelined ADC is to
alleviate the interference between the analog front-end and
digital back-end. Before digitization is complete, the digital
back-end has no data to process and thus can be turned off to
save power and reduce interference to the front-end. It can be
turned back on when the data is available. At this time, the
front-end, including the ADC, can be turned off for the same
reason. With this interleaved operation, both power
consumption and interference will decrease.
III.

programmable sampling clock generator has proven helpful to

maintain the timing of the sampling.
B. Track and hold circuits
In order to reduce the error caused by the aperture
uncertainty, a track and hold circuit is widely employed in
flash ADC even though it is not required. Due to the low
precision requirement of the ADC for UWB signal, an open
loop CMOS track and hold is employed in our design for
simplicity [15]. It consists of a transmission gate controlled
by the clock and sampling capacitor. When the sampling
clock is high, the switch is on and the output tracks the input.
When clock is low, the input is held by the capacitor.

CIRCUIT IMPLEMENTATION

According to Figure 3, the ADC consists of five modules:

the track and hold circuit, the timing generator, the
comparator and two encoders. The details of these modules
are disclosed in this section.

Figure 6. Modified Quantum Voltage Comparator

1.0V

Figure 5.
Proposed programmable sampling generator
A. Timing
Circuits
Timing is the most important factor for the proposed
ADC. Generating the sampling clock with the precise pulse
width and phase is the key of the burst sampling ADC.
Usually it can be generated at every rising edge of the low
frequency global clock if the complement of the delayed
clock and the clock itself are fed into a NAND gate. However
the delay may vary at different processes, voltages, and
temperatures (PVT). To minimize the PVT variance, we
proposed a programmable sampling clock generator based on
a digital controlled delay element DCDE [14]. As shown in
Figure. 5, the drain current through the control transistor M7
is determined by a current mirror composed of transistors M5
and M7. An appropriate current through M7 can be adjusted
by turning-on transistor M1-M3. Therefore the overall pulse
width is digitally controlled by the vector (a, b, c). Depending
on the input vector, this circuit can generate a rectangle pulse
with eight different widths. The beauty of the programmable
sampling clock generator is that the pulse width of the
sampling clock can be adjusted by setting the control vector.
The delay/phase of the sampling clock can be adjusted by
using the DCDE as well. By sizing transistor M1, M2, M3,
and M4, a 100ps resolution can be achieved and the accuracy
can be further improved by adding more control vectors. This

0.6V

Figure 7. Voltage transfer curve of 16 modified QV comparators

C. Comparator
The Quantum Voltage (QV) comparator consists of two
cascaded differential pairs with current mirror load [16]. It
has good common mode noise rejection and no resistor ladder
circuits to create the reference voltage, which can be
generated internally by intentionally introducing mismatch in
the differential pairs. We propose a modified QV comparator
shown in Figure 6 by replacing the second differential pair as
well as the current mirror load of the QV comparator with a
CMOS inverter. This replacement can save the bias current of
the second differential pair while still keeping the common
mode nose rejection properties of the differential pair. The
Last two inverters work as gain boosters to improve the gain
of the comparator. As shown in Figure 7, the 16 internally
generated reference voltages are almost equally spaced
between the input range, 0.6V1.0V. Comparing to the

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original QV comparator, the modified one can save 56% of

the power consumption while still keeping the benefits of the
QV comparator, which is insensitive to PVT variation.
D. Encoders
Instead of converting the thermometer code generated by
the comparator to binary code directly, the intermediate Gray
code is employed in the pipelined encoder to mitigate the
impact of babble error.
IV.

0.18m CMOS process. Simulation results show that the

proposed 4-bit ADC can operate at 1G sample/s with low
power consumption and can be easily integrated into a single
chip UWB transceiver.
ACKNOWLEDGMENT
The authors acknowledge the support of the United States
Department of Energy EETAPP program (DE-97ER12220)
and the Governors Information Technology Initiative.

SIMULATION RESULTS

This proposed ADC has been implemented using TSMC

0.18m technology simulated using Cadence Spectre
simulator. The simulation result of the ADC with a 25 MHz
4-ns triangle pulse input with 0.4V input range is shown in
Figure 8. The performance and comparison of the proposed
ADC with related works are summarized in Table I.

REFERENCES
[1]
[2]

[3]

[4]

[5]

[6]

[7]
Figure 8. Output waveform of ADC simulation
[8]
TABLE I.

THE COMPARISON OF HIGH SPEED ADC

Design

[5]

[6]

[7]

[8]

[9]

This
work

Technology

0.18m
4-bit
1.2

0.13m
6-bit
1.2

0.25m
6-bit
1.3

0.13m
4-bit
1.4

0.18m
5/6 bit
1.056

0.18m
4-bit
1

0.5 V
86
N/A
N/A

1V
160
N/A
N/A

1V
600
0.4
0.8

1V
62
0.3
0.2

1V
36/98
0.3/0.5
0.5/0.6

0.4 V
7.6
0.3
0.3

Resolution
Sampling rate
(GSPS)
Input range
Power (mW)
DNL (LSB)
INL (LSB)

V.

CONCLUSION

[9]

[10]

[11]

[12]
[13]

This paper presented a low power 4-bit ADC for sub-GHz

Ultra wideband (UWB) receivers. The power efficiency is
achieved by taking advantages of the low duty cycle feature
of the baseband pulse. With the help of the interleaved burstmode sampling architecture, almost 80% of the unnecessary
operations including sampling, comparing, and encoding are
avoided. By using pipelining, the power consumption is
further reduced through keeping the digital baseband in a
slow clock domain of low duty cycle pulses. The proposed
ADC has been designed and simulated by using the TSMC

[14]

[15]
[16]

1168

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