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Data Sheet
FEATURES
GENERAL DESCRIPTION
The ADP5063 charger is fully compliant with USB 3.0 and the
USB Battery Charging 1.2 Compliance Plan Specification, and
enables charging via the mini USB VBUS pin from a wall charger,
car charger, or USB host port.
The ADP5063 operates from a 4 V to 6.7 V input voltage range but
is tolerant of voltages up to 20 V, thereby alleviating concerns about
USB bus spikes during disconnection or connection scenarios.
The ADP5063 features an internal field effect transistor (FET)
between the linear charger output and the battery. This permits
battery isolation and, therefore, system powering under a dead
battery or no battery scenario, which allows immediate system
function upon connection to a USB power supply.
Based on the type of USB source, which is detected by an external
USB detection chip, the ADP5063 can be set to apply the correct
current limit for optimal charging and USB compliance.
The ADP5063 has three factory-programmable digital input/output pins that provide maximum flexibility for different systems.
These digital input/output pins permit a combination of features,
such as input current limits, charging enable and disable, charging
current limits, and a dedicated interrupt output pin.
APPLICATIONS
Single cell lithium iron phosphate (LiFePO4) portable
equipment
Portable medical devices
Portable instrumentation devices
Portable consumer devices
PROGRAMMABLE
C4
10F
ISO_Sx
VINx
CBP
C1
100nF
C3
22F
SCL
SDA
DIG_IO1
DIG_IO2
DIG_IO3
SYSTEM
ISO_Bx
CHARGER
CONTROL
BLOCK
BAT_SNS
+
Li-Ion
C2
22F
THR
SYS_EN
ILED
AGND
VLED
11593-001
AC OR
USB
Figure 1.
Rev. 0
Document Feedback
ADP5063
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 3
Introduction ................................................................................ 16
Charger Modes............................................................................ 18
REVISION HISTORY
7/13Revision 0: Initial Version
Rev. 0 | Page 2 of 44
Data Sheet
ADP5063
SPECIFICATIONS
40C < TJ < +125C, VVINx = 5.0 V, RHOT_RISE < RTHR < RCOLD_FALL, VBAT_SNS = 3.6 V, VISO_Bx = VBAT_SNS, CVINx = 10 F, CISO_Sx = 22 F, CISO_Bx =
22 F, CCBP = 100 nF, all registers are at default values, unless otherwise noted.
Table 1.
Parameter
GENERAL PARAMETERS
Undervoltage Lockout
Hysteresis
Total Input Current
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VUVLO
2.25
50
74
114
2.35
100
92
2.5
150
100
150
300
V
mV
mA
mA
mA
425
470
500
900
1500
mA
mA
mA
mA
mA
A
A
0.9
mA
ILIM
IQVIN
IQVIN_SUSPEND
IQBATT
2
1.0
20
0.5
CHARGER
Fast Charge Current Constant
Current (CC) Mode
Fast Charge Current Accuracy
Trickle Charge Current2
Weak Charge Current2, 3
Trickle to Weak Charge Threshold
Dead Battery
Hysteresis
Weak Battery Threshold
Weak to Fast Charge Threshold
Battery Termination Voltage
Termination Voltage Accuracy
ICHG
1.8
750
9
mA
+9
ITRK_DEAD
ICHG_WEAK
16
20
ITRK_DEAD + ICHG
25
mA
mA
VTRK_DEAD
VTRK_DEAD
1.9
2.0
100
2.1
V
mV
VWEAK
VWEAK
VTRM
2.89
3.0
100
3.600
3.11
V
mV
V
%
%
%
V
mA
mA
On BAT_SNS2, 4
mA
mV
V
mA
V
mA
ms
0.6
1.55
1.7
VBATOV
IEND
VRCH
VBAT_SHR
ITRK_SHORT
VCHG_VLIM
ICHG_START
tCHG_START
15
17
59
160
2.2
3.1
185
+0.6
+1.45
+1.7
VIN 0.075
52.5
260
2.4
20
3.2
260
3
98
83
123
390
2.5
3.3
365
Rev. 0 | Page 3 of 44
ITRK_SHORT = ITRK_DEAD2
Voltage limit is not active by default
VBAT_SNS > VTRK_DEAD
ADP5063
Parameter
BATTERY ISOLATION FET
Pin to Pin Resistance Between
ISO_Sx and ISO_Bx
Regulated System Voltage: VBAT Low
Battery Supplementary Threshold
LDO AND HIGH VOLTAGE BLOCKING
Regulated System Voltage
Load Regulation
High Voltage Blocking FET (LDO FET)
On Resistance
Maximum Output Current
VINx Input Voltage, Good Threshold
Rising
VINx Falling
VINx Input Overvoltage Threshold
Hysteresis
VINx Transition Timing
THERMAL CONTROL
Isothermal Charging Temperature
Thermal Early Warning Temperature
Thermal Shutdown Temperature
THERMISTOR CONTROL
Thermistor Current
10,000 NTC (Negative Temperature
Coefficient) Resistor
100,000 NTC Resistor
Thermistor Capacitance
Cold Temperature Threshold
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
Hot Temperature Threshold
Resistance Thresholds
Hot to Typical Resistance
Typical to Hot Resistance
JEITA1 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS 5
JEITA Cold Temperature
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
JEITA Cool Temperature
Resistance Thresholds
Typical to Cool Resistance
Cool to Typical Resistance
JEITA Warm Temperature
Resistance Thresholds
Warm to Typical Resistance
Typical to Warm Resistance
Data Sheet
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
55
89
VTHISO
3.6
3.2
0
3.8
3.4
5
4.0
3.5
12
V
V
mV
VISO_STRK
4.214
4.3
4.386
0.56
330
485
%/A
m
2.1
3.9
4.0
A
V
RDSON_ISO
VISO_SFC
RDS(ON)HV
VVIN_OK_RISE
VVIN_OK_FALL
VVIN_OV
VVIN_OV
tVIN_RISE
tVIN_FALL
3.75
6.7
3.6
6.9
0.1
10
10
TLIM
TSDL
TSD
115
130
140
110
INTC_10k
INTC_100k
CNTC
TNTC_COLD
RCOLD_FALL
RCOLD_RISE
TNTC_HOT
RHOT_FALL
RHOT_RISE
20,500
2750
25,600
24,400
60
3700
3350
20,500
RTYP_FALL
RTYP_RISE
TJEITA_WARM
13,200
4260
C
C
C
C
TJ rising
TJ falling
40
A
pF
C
30,720
3950
25,600
24,400
10
30,720
16,500
15,900
45
19,800
5800
5200
V
V
V
s
s
RCOLD_FALL
RCOLD_RISE
TJEITA_COOL
400
100
0
TJEITA_COLD
RWARM_FALL
RWARM_RISE
3.7
7.2
6140
Rev. 0 | Page 4 of 44
Data Sheet
Parameter
JEITA Hot Temperature
Resistance Thresholds
Hot to Warm Resistance
Warm to Hot Resistance
JEITA2 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS
JEITA Cold Temperature
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
JEITA Cool Temperature
Resistance Thresholds
Typical to Cool Resistance
Cool to Typical Resistance
JEITA Warm Temperature
Resistance Thresholds
Warm to Typical Resistance
Typical to Warm Resistance
JEITA Hot Temperature
Resistance Thresholds
Hot to Warm Resistance
Warm to Hot Resistance
BATTERY DETECTION
Sink Current
Source Current
Battery Threshold
Low
High
Battery Detection Timer
TIMERS
Clock Oscillator Frequency
Start Charging Delay
Trickle Charge
Fast Charge
Charge Complete
Deglitch
Watchdog2
Safety
Battery Short2
ILED OUTPUT PINS
Voltage Drop over ILED
Maximum Operating Voltage over
ILED
SYS_EN OUTPUT Pin
SYS_EN FET On Resistance
ADP5063
Symbol
TJEITA_HOT
RHOT_FALL
RHOT_RISE
Min
2750
TJEITA_COLD
3700
3350
Max
3950
RCOLD_FALL
RCOLD_RISE
TJEITA_COOL
20,500
RTYP_FALL
RTYP_RISE
TJEITA_WARM
13,200
RWARM_FALL
RWARM_RISE
TJEITA_HOT
Typ
60
4260
30,720
16,500
15,900
45
19,800
6140
RHOT_FALL
RHOT_RISE
2750
3700
3350
3950
ISINK
ISOURCE
13
7
20
10
34
13
mA
mA
VBATL
VBATH
tBATOK
1.8
1.9
3.4
333
2.0
V
V
ms
fCLK
tSTART
tTRK
tCHG
tEND
tDG
2.7
3
1
60
600
7.5
31
3.3
MHz
sec
min
min
min
ms
tWD
tSAFE
tBAT_SHR
36
32
40
30
VILED
VMAXILED
200
RON_SYS_EN
10
44
5.5
Rev. 0 | Page 5 of 44
Test Conditions/Comments
No battery charging occurs
25,600
24,400
10
5800
5200
60
Unit
C
sec
min
sec
mV
V
IILED = 20 mA
ISYS_EN = 20 mA
ADP5063
Parameter
LOGIC INPUT PINS
Maximum Voltage on Digital Inputs
Maximum Logic Low Input Voltage
Minimum Logic High Input Voltage
Pull-Down Resistance
Data Sheet
Symbol
VDIN_MAX
VIL
VIH
Min
1.2
215
Typ
350
Max
Unit
Test Conditions/Comments
5.5
0.5
V
V
V
k
610
Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx.
These values are programmable via I2C. Values are given with default register values.
The output current during charging may be limited by the input current limit or by the isothermal charging mode.
4
During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled.
Any residual current that is not required by the system is also used to charge the battery.
5
Either JEITA1 (default) or JEITA2 can be selected in I2C, or both JEITA functions can be enabled or disabled in I2C.
1
2
3
Symbol
Min
Typ
CVINx
CCBP
CISO_Sx
CISO_Bx
4
60
10
10
100
22
22
Max
Unit
10
140
100
F
nF
F
F
Test Conditions/Comments
Effective capacitance
Symbol
CS
fSCL
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
tSP
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20
0
Typ
Max
Unit
400
400
pF
kHz
s
s
ns
s
s
s
s
s
ns
ns
ns
0.9
300
300
50
Guaranteed by design.
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
Rev. 0 | Page 6 of 44
Data Sheet
ADP5063
Timing Diagram
SDA
tLOW
tF
tSU, DAT
tR
tSP
tBUF
tR
tHD, STA
tF
SCL
tHD, DAT
tHIGH
tSU, STO
tSU, STA
Sr
S
11593-002
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Rev. 0 | Page 7 of 44
ADP5063
Data Sheet
Table 4.
Parameter
VIN1, VIN2, VIN3 to AGND
All Other Pins to AGND
Continuous Drain Current, Battery Supplementary Mode, from ISO_Bx to ISO_Sx
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
0.5 V to +20 V
0.3 V to +6 V
2.1 A
65C to +150C
40C to +125C
JEDEC J-STD-020
ESD CAUTION
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is
specified for a device soldered in a circuit board for surfacemount packages.
Table 5.
Package Type
20-Lead LFCSP
JA
35.6
JC
3.65
Unit
C/W
Rev. 0 | Page 8 of 44
Data Sheet
ADP5063
17 SDA
16 SYS_EN
18 THR
20 AGND
19 CBP
15 ILED
SCL 1
DIG_IO3 2
BAT_SNS 4
14 ISO_B3
ADP5063
13 ISO_B2
TOP VIEW
(Not to Scale)
12 ISO_B1
DIG_IO1 5
ISO_S2 10
8
VIN3
ISO_S1
VIN2 7
VIN1 6
11 ISO_S3
NOTES
1. CONNECTION OF THE EXPOSED PAD IS NOT REQUIRED. THE
EXPOSED PAD CAN BE CONNECTED TO ANALOG GROUND TO
IMPROVE HEAT DISSIPATION FROM THE PACKAGE TO BOARD.
11593-003
DIG_IO2 3
Name
SCL
DIG_IO3
Type 1
I
GPIO
DIG_IO2
GPIO
4
5
BAT_SNS
DIG_IO1
I
GPIO
6, 7, 8
9, 10, 11
I/O
I/O
I/O
15
16
17
18
SDA
THR
I/O
I
19
20
N/A 4
CBP
AGND
EP
I/O
G
N/A4
12, 13, 14
O
O
Description
I2C-Compatible Interface Serial Clock.
Charging Enable. When DIG_IO3 = low or high-Z, charging is disabled. When DIG_IO3 = high,
charging is enabled.2, 3
Set Input Current Limit. When DIG_IO2 = low or high-Z, the input limit is defined by DIG_IO1
setting. When DIG_IO2 = high, the input limit is 1500 mA.2, 3
Battery Voltage Sense Pin.
Set Input Current Limit. This pin sets the input current limit directly. When DIG_IO1 = low or
high-Z, the input limit is 100 mA. When DIG_IO1 = high, the input limit is 500 mA. 2, 3
Power Connections to USB VBUS. These pins are high current inputs when in charging mode.
Linear Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. High
current input/output.
Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.
Open-Drain Output to Indicator LED.
System Enable. This pin is the battery OK flag/open-drain pull-down FET to enable the system
when the battery reaches the VWEAK level.
I2C-Compatible Interface Serial Data.
Battery Pack Thermistor Connection. If this pin is not used, connect a dummy 10 k resistor from
THR to AGND.
Bypass Capacitor Input.
Analog Ground.
Exposed Pad. Connection of the exposed pad is not required. The exposed pad can be connected
to analog ground to improve heat dissipation from the package to the board.
I is input, O is output, I/O is input/output, G is ground, and GPIO is the factory programmable general-purpose input/output.
See the Digital Input and Output Options section for details.
3
The DIG_IOx setting defines the initial state of the ADP5063. If the parameter or the mode that is related to each DIG_IOx pin setting is changed (by programming an
equivalent I2C register bit or bits), the I2C register setting takes precedence over the DIG_IOx pin setting. VINx connection or disconnection resets control to the
DIG_IOx pin.
4
N/A = not applicable.
1
2
Rev. 0 | Page 9 of 44
ADP5063
Data Sheet
4.38
900
4.36
800
4.34
4.32
4.30
4.28
4.26
500
400
300
4.22
100
0.1
0
1.8
3.3
2.8
2.3
3.8
70
LOAD = 100mA
LOAD = 500mA
LOAD = 1000mA
ISOLATION FET RESISTANCE (m)
4.4
TRICKLE CHARGE
FAST CHARGE
600
200
4.3
SYSTEM VOLTAGE (V)
700
4.24
4.20
0.01
WEAK
CHARGE
11593-009
4.40
11593-004
VVINx = 5.0 V, CVINx = 10 F, CISO_Sx = 44 F, CISO_Bx = 22 F, CCBP = 100 nF, all registers are at default values, unless otherwise noted.
4.2
4.1
4.0
3.9
3.8
3.7
65
60
55
50
45
4.4
4.8
5.2
5.6
6.0
6.4
6.8
40
2.7
2.9
3.1
3.3
3.5
Figure 5. System Voltage vs. Input Voltage (in Dropout), LDO Mode,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V
Rev. 0 | Page 10 of 44
3.7
11593-010
3.5
4.0
11593-005
3.6
Data Sheet
ADP5063
3.5
3.8
DEFAULT STARTUP
DIS_LDO = HIGH
3.7
2.0
1.5
1.0
0.5
0.4
3.5
3.4
0.3
3.3
0.2
3.2
70
65
60
55
50
40
1.0
1.5
2.0
11593-012
45
0.5
20
40
60
CHARGE TIME (Minutes)
80
3.0
11593-011
0.1
VBAT_SNS
IISO_B
3.1
Rev. 0 | Page 11 of 44
11593-013
2.5
3.6
0.5
3.0
0.6
ADP5063
Data Sheet
TEMPERATURE CHARACTERISTICS
1.4
1.3
0.5
VISO_Bx = 3.6V
VISO_Bx = 4.2V
VISO_Bx = 5.5V
0.4
1.5
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
VISO_Sx = 4.3V
VISO_Sx = 5.0V
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
15
10
35
60
85
5.0
1.8
4.5
1.4
1.2
1.0
0.8
0.6
0.4
0.2
10
20
35
50
65
80
95
110
125
50
65
80
95
110
125
VIN = 4.0V
VIN = 5.0V
VIN = 6.7V
3.5
3.0
2.5
2.0
1.5
1.0
25
10
20
35
50
65
80
95
110
125
0.5
VISO_Sx = 4.3V
VISO_Sx = 5.0V
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
VTRM = 3.5V
VTRM = 3.8V
VTRM = 4.2V
0.3
0.2
0.1
0
0.1
0.2
0.3
25
10
20
35
50
65
80
95
110
125
0.5
40
25
10
20
35
50
65
80
95
110
125
11593-019
0.4
11593-016
35
4.0
0
40
0.5
40
20
11593-018
25
0.4
0.5
11593-015
0
40
10
Figure 14. System Voltage Accuracy vs. Ambient Temperature, Trickle Charge
Mode, VISO_Sx = 4.3 V and VVINx = 5.0 V, or VISO_Sx = 5.0 V and VVINx = 6.0 V
2.0
1.6
25
0.5
40
11593-014
0
40
11593-017
0.1
Rev. 0 | Page 12 of 44
ADP5063
1.4
1.3
ICHG = 1300mA
1.2
1.1
1.0
0.9
0.8
0.7
ICHG = 750mA
0.6
ICHG = 500mA
0.4
40
10
15
35
85
60
110
11593-020
0.5
6.90
6.85
10
20
35
50
65
80
95
110
125
11593-021
6.95
25
20
35
50
65
80
95
110
7.00
6.80
40
1.6
1.5
ILIM = 1500mA
1.4
1.3
1.2
1.1
1.0
0.9 ILIM = 900mA
0.8
0.7
0.6
0.5 ILIM = 500mA
0.4
0.3
0.2
ILIM = 100mA
0.1
0
5
40 25 10
Rev. 0 | Page 13 of 44
125
11593-022
Data Sheet
ADP5063
Data Sheet
TYPICAL WAVEFORMS
T
VISO_Sx
VISO_Sx
VVINx
VVINx
4
IISO_Bx
2
IVINx
IISO_Bx
IVINx
M1.00ms
A CH2
T
1.00ms
120mA
11593-023
CH1 2.00V
CH2 200mA
CH3 200mA CH4 2.00V
CH1 2.00V
CH2 200mA
CH3 200mA CH4 2.00V
Figure 20. Charging Startup, VVINx = 5.0 V, ILIM[3:0] = 0110 (Binary) = 500 mA,
ICHG[4:0] = 01110 (Binary) = 750 mA
M200.0s
T
0.00s
A CH2
216mA
11593-026
VISO_Sx T
VISO_Sx
1
3
1
IISO_Bx
IISO_Sx
IISO_Sx
M1.00ms
A CH2
T
3.00ms
820mA
CH1 1.00V
CH2 500mA
CH3 500mA
M1.0ms
A CH2
T
3.00ms
610mA
11593-027
11593-024
Figure 24. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA,
EN_CHG = High, ILIM[3:0] = 0110 (Binary) = 500 mA
VISO_Sx
2
VVINx
1
VISO_Bx
2
IISO_Bx
IISO_Bx
3
3
IVINx
M40.0s
T
0.00s
A CH3
610mA
CH2 2.00V
CH3 10.0mA
M200ms
T
0.00s
A CH3
17.2mA
11593-028
11593-025
Rev. 0 | Page 14 of 44
Data Sheet
ADP5063
THEORY OF OPERATION
SUMMARY OF OPERATION MODES
Table 7. Summary of Operation Modes
Mode Name
IC Off, Standby
IC Off, Suspend
LDO Mode Off, Isolation
FET On
LDO Mode Off, Isolation
FET Off (System Off)
LDO Mode, Charger Off
Trickle Charge Mode
Weak Charge Mode
Fast Charge Mode
Charge Mode, No Battery
Charge Mode, Battery
(ISO_Bx) Shorted
1
VVINx
Condition
0V
Battery Condition
Any battery condition
Trickle
Charge
Off
LDO FET
State
Off
Battery
Isolation FET
On
5V
5V
Off
Off
Off
Off
On
On
System Voltage
ISO_Sx
Battery voltage
or 0 V
Battery voltage
Battery voltage
5V
Off
Off
Off
0V
DIS_LDO = high
Disable LDO and enable
isolation FET
Enable battery charging
5V
5V
5V
5V
5V
5V
Off
On
On
Off
Off
On
LDO
LDO
CHG
CHG
LDO
LDO
Off
Off
CHG
CHG
Off
Off
4.3 V
4.3 V
3.4 V
3.4 V (minimum)
4.3 V
4.3 V
Additional Conditions 1
DIG_IOx
DIG_IO3
Not
applicable
Equivalent I2C
Address, Data Bit(s)
0x07, D0
0x07, D3, D0
Description
Low = all charging modes disabled (fast, weak, trickle).
High = all charging modes enabled (fast, weak, trickle).
Low = LDO enabled.
High = LDO disabled. In addition, when EN_CHG = low, the
battery isolation FET is on; when EN_CHG = high, the battery
isolation FET is off.
Rev. 0 | Page 15 of 44
ADP5063
Data Sheet
INTRODUCTION
The ADP5063 is a fully programmable I2C charger for single
cell lithium ion or lithium polymer batteries, suitable for a wide
range of portable applications.
The linear charger architecture enables up to 2.1 A output
current at 4.3 V to 5.0 V (I2C programmable) on the system
power supply, and up to 1.3 A of charge current into the battery
from a dedicated charger.
The ADP5063 operates from an input voltage of 4 V up to 6.7 V
but is tolerant of voltages of up to 20 V. The 20 V voltage tolerance
alleviates the concerns of the USB bus spiking during disconnection or connection scenarios.
The ADP5063 features an internal FET between the linear charger
output and the battery. This feature permits battery isolation and,
therefore, system powering under a dead battery or no battery
scenario, which allows immediate system function upon
connection to a USB power supply.
The ADP5063 is fully compliant with USB 3.0 and the USB Battery
Charging 1.2 Compliance Plan Specification. The ADP5063 is
chargeable via the mini USB VBUS pin from a wall charger, car
charger, or USB host port. Based on the type of USB source, which
Rev. 0 | Page 16 of 44
Data Sheet
6
TO USB VBUS
OR WALL
ADAPTER
7
ADP5063
VIN1
ISO_S1
HIGH VOLTAGE
BLOCKING
LDO FET
ISO_S2
VIN2
VIN3
ISO_S3
+
6.85V
+
LDO FET
CONTROL
VIN LIMIT
TO SYSTEM
LOAD
10
11
VIN
OVERVOLTAGE
CBP
BATTERY
ISOLATION FET
19
TRICKLE
CURRENT
SOURCE
+
3.9V
3MHz OSC
ISO_B1
12
VIN GOOD
EOC
1
17
5
3
2
ISO_B2
SCL
CHARGE CONTROL
ISO_B3
SDA
14
CV MODE
RECHARGE
DIG_IO1
DIG_IO2
I2C INTERFACE
AND
CONTROL LOGIC
WEAK
DIG_IO3
BATTERY
DETECTION
SINK
TRICKLE
BATTERY:
OPEN
SHORT
BAT_SNS
3.4V
1.9V
BATTERY DETECTION
SYS_EN
+
16
13
SYS_EN OUTPUT
LOGIC
VIN 150mV
BATTERY OVERVOLTAGE
TSD 140C
WARNING 130C
ISOTHERMAL 115C
TSD DOWN 110C
WARM
NTC CURRENT
CONTROL
HOT
THR
THERMAL CONTROL
AGND
0.5V
18
NTC
20
SINGLE
CELL
Li-Ion
Rev. 0 | Page 17 of 44
11593-029
ILED OUTPUT
LOGIC
COLD
COOL
ILED
15
ADP5063
Data Sheet
Table 9. DIG_IO1 Operation
CHARGER MODES
Input Current Limit
The VINx input current limit is controlled via the internal I2C
ILIM bits. The input current limit can also be controlled via the
DIG_IO1 pin (if factory programmed to do so) as outlined in
Table 9. Any change from the 100 mA I2C default takes precedence
over the pin setting.
DIG_IO1
0
1
Function
100 mA input current limit or I2C programmed
value
500 mA input current limit or I2C programmed
value (or reprogrammed I2C value from 100 mA
default)
USB Compatibility
The ADP5063 features an I2C-programmable input current
limit to ensure compatibility with the requirements listed in
Table 10. The current limit defaults to 100 mA to allow compatibility with a USB host or hub that is not configured.
The I2C register default is 100 mA. An I2C write command to the
ILIM bits overrides the DIG_IOx pins, and the I2C register default
value can be reprogrammed for alternative requirements.
When the input current-limit feature is used, the available input
current may be too low for the charger to meet the programmed
charging current, ICHG, thereby reducing the rate of charge and
setting the VIN_ILIM flag.
When connecting voltage to VINx without the proper voltage
level on the battery side, the high voltage blocking mechanism
is in a state wherein it draws a current of <1 mA until VVINx
reaches the VIN_OK level.
The ADP5063 charger provides support for the following connections through the single connector VINx pin, as shown in
Table 10.
Dedicated Charger
Rev. 0 | Page 18 of 44
ADP5063 Function
100 mA input current limit or I2C programmed value
300 mA input current limit or I2C programmed value
100 mA input current limit or I2C programmed value
500 mA input current limit or I2C programmed value
150 mA input current limit or I2C programmed value
900 mA input current limit or I2C programmed value
1500 mA input current limit or I2C programmed value
Data Sheet
ADP5063
A deeply discharged Li-Ion cell can exhibit a very low cell voltage,
making it unsafe to charge the cell at high current rates. The
ADP5063 charger uses a trickle charge mode to reset the battery
pack protection circuit and lift the cell voltage to a safe level for
fast charging. A cell with a voltage below VTRK_DEAD is charged
with the trickle mode current, ITRK_DEAD. During trickle charging
mode, the CHARGER_STATUS[2:0] bits are set.
When the battery voltage exceeds VTRK_DEAD and VWEAK, the charger
switches to fast charge mode, charging the battery with the constant
current, ICHG. During fast charge mode (constant current), the
CHARGER_STATUS[2:0] bits are set to 010.
As the battery charges, its voltage rises and approaches the termination voltage, VTRM. The ADP5063 charger monitors the voltage
on the BAT_SNS pin to determine when charging should end.
However, the internal ESR of the battery pack combined with the
printed circuit board (PCB) and other parasitic series resistances creates a voltage drop between the sense point at the
BAT_SNS pin and the cell terminal. To compensate for this
and to ensure a fully charged cell, the ADP5063 enters a constant
voltage charging mode when the termination voltage is detected
on the BAT_SNS pin. The ADP5063 reduces charge current
gradually as the cell continues to charge, maintaining a voltage of
VTRM on the BAT_SNS pin. During fast charge mode (constant
voltage), the CHARGER_ STATUS bits are set to 011.
Set the default 20 mA via the linear trickle charger branch (to
ensure that the microprocessor remains alive if powered by
the main charger output, ISO_Sx). Any residual current on
the main charger output, ISO_Sx, is used to charge the battery.
During weak current mode, other features may prevent the
weak charging current from reaching its full programmed
value. Isothermal charging mode or input current limiting
for USB compatibility can affect the programmed weak
charging current value under certain operating conditions.
During weak charging, the ISO_Sx node is regulated to
VISO_SFC by the battery isolation FET.
Watchdog Timer
The ADP5063 charger features a programmable watchdog timer
function to ensure that charging is under the control of the processor. The watchdog timer starts running when the ADP5063
charger determines that the processor should be operational,
that is, when the processor sets the RESET_WD bit for the first
time or when the battery voltage is greater than the weak battery
threshold, VWEAK. When the watchdog timer has been triggered,
it must be reset regularly within the watchdog timer period, tWD.
While in charger mode, if the watchdog timer expires without
being reset, the ADP5063 charger assumes that there is a software
problem and triggers the safety timer, tSAFE. For more information
see the Safety Timer section.
Rev. 0 | Page 19 of 44
ADP5063
Data Sheet
Safety Timer
Charge Complete
The ADP5063 charger monitors the charging current while in
fast charge constant voltage mode. If the current falls below IEND
and remains below IEND for tEND, charging stops and the CHDONE
flag is set. If the charging current falls below IEND for less than
tEND and then rises above IEND again, the tEND timer resets.
Recharge
After the detection of charge complete and the cessation of
charging, the ADP5063 charger monitors the BAT_SNS pin as
the battery discharges through normal use. If the BAT_SNS pin
voltage falls to VRCH, the charger reactivates charging. Under most
circumstances, triggering the recharge threshold results in the
charger starting directly in fast charge constant voltage mode.
The recharge function can be disabled in the I2C interface, but a
status bit (Register Address 0x0C, Bit 3) informs the system that
a recharge cycle is required.
IC Enable/Disable
The ADP5063 IC can be disabled by the DIG_IO2 digital input
pin (if factory programmed to do so) or by the I2C registers. All
internal control circuits are disabled when the IC is disabled. Disabling the IC1 option can also control the states of the LDO FET
and the battery isolation FET.
It is critical to note that during the disable IC1 mode, a high voltage
at VINx passes to the internal supply voltage because all of the
internal control circuits are disabled. The VINx supply voltage
must fulfill the following condition:
SYS_EN Output
The ADP5063 features a SYS_EN open-drain FET to enable the
system until the battery is at the minimum required level for
guaranteed system startup. When there are minimum battery
voltage and/or minimum battery charge level requirements, the
operation of SYS_EN can be set by I2C programming. The SYS_EN
operation can be factory programmed to four different operating
conditions, as described in Table 11.
Table 11. SYS_EN Mode Descriptions
SYS_EN Mode
Selection
00
01
10
11
Description
SYS_EN is activated when LDO is active and
system voltage is available.
SYS_EN is activated by the ISO_Bx voltage, the
battery charging mode.
SYS_EN is activated and the isolation FET is
disabled when the battery drops below VWEAK.
This option is active when VINx = 0 V and the
battery monitor is activated from Register 0x07,
Bit 5 (EN_BMON).
SYS_EN is active in LDO mode when the charger
is disabled.
SYS_EN is active in charging mode when
VISO_Bx VWEAK.
The ILED is an open-drain output for an indicator LED connection. Optionally, the ILED output can be used as a status output
for a microcontroller. Indicator LED modes are listed in Table 12.
Table 12. Indicator LED Operation Modes
ADP5063 Mode
IC Off
LDO Mode Off
LDO Mode On
Charge Mode
Timer Error (tTRK, tCHG, tSAFE)
Overtemperature (TSD)
Rev. 0 | Page 20 of 44
ILED Mode
Off
Off
Off
Continuously on
Blinking
Blinking
On/Off Time
167 ms/833 ms
1 sec/1 sec
Data Sheet
ADP5063
THERMAL MANAGEMENT
Isothermal Charging
Fault Recovery
Before performing the following operation, it is important to
ensure that the cause of the fault has been rectified.
To recover from a charger fault (when CHARGER_STATUS[2:0] =
110), cycle the power on VINx or write high to reset the I2C
fault bits in the fault register (Register Address 0x0D).
BATTERY DETECTION
Battery Voltage Level Detection
The ADP5063 charger features a battery detection mechanism to
detect an absent battery. The charger actively sinks and sources
current into the ISO_Bx node, and voltage vs. time is detected.
The sink phase is used to detect a charged battery, whereas the
source phase is used to detect a discharged battery.
The sink phase (see Figure 27) sinks ISINK current from the ISO_Bx
pins for a time period, tBATOK. If ISO_Bx is below VBATL when the
tBATOK timer expires, the charger assumes that no battery is present
and starts the source phase. If the ISO_Bx pin exceeds the VBATL
voltage when the tBATOK timer expires, the charger assumes that
the battery is present and begins a new charge cycle.
The source phase sources ISOURCE current to the ISO_Bx pins for
a time period, tBATOK. If ISO_Bx exceeds VBATH before the tBATOK
timer expires, the charger assumes that no battery is present. If
the ISO_Bx pin does not exceed the VBATH voltage when the tBATOK
timer expires, the charger assumes that a battery is present and
begins a new charge cycle.
Rev. 0 | Page 21 of 44
ADP5063
Data Sheet
SOURCE PHASE
VBATL
LOGIC
STATUS
tBATOK
VBATH
ISOURCE
SINK PHASE
LOGIC
STATUS
tBATOK
OPEN
OR
SHORT
OPEN
ISO_Bx
11593-030
OPEN
OPEN
ISINK
ISO_Bx
ISO_Bx
SHORT
OR
LOW
BATTERY
tBAT_SHR
SHORT
ISO_Bx
11593-031
tBATOK
LOGIC
STATUS
SHORT
OPEN
OR
SHORT
SHORT
SHORT
ISINK
tBATOK
LOGIC
STATUS
ISOURCE
LOGIC
STATUS
ISO_Bx
TRICKLE CHARGE
VBAT_SHR
SOURCE PHASE
VBATH
VBATL
ITRK_DEAD
SINK PHASE
VISO_Bx
<2.5 V
>2.5 V
Don't care
THR Function
Off
Off, controlled by I2C
Always on
The ADP5063 charger monitors the voltage in the THR pin and
suspends charging when the current is outside the range of less
than 0C or greater than 60C.
Rev. 0 | Page 22 of 44
Data Sheet
ADP5063
Symbol
IJEITA_COLD
IJEITA_COOL
IJEITA_TYP
IJEITA_WARM
IJEITA_HOT
Conditions
No battery charging occurs.
Battery charging occurs at approximately 50% of the programmed
level. See Table 15 for specific charging current reduction levels.
Normal battery charging occurs at the default/programmed levels.
Battery termination voltage (VTRM) is reduced by 100 mV from the
programmed value.
No battery charging occurs.
Min
0
Max
0
10
Unit
C
C
10
45
45
60
60
Table 15. JEITA1 Reduced Charge Current Levels, Battery Cool Temperature
ICHG[4:0] (Default)
00000 = 50 mA
00001 = 100 mA
00010 = 150 mA
00011 = 200 mA
00100 = 250 mA
00101 = 300 mA
00110 = 350 mA
00111 = 400 mA
01000 = 450 mA
01001 = 500 mA
01010 = 550 mA
01011 = 600 mA
01100 = 650 mA
01101 = 700 mA
01110 = 750 mA
01111 = 800 mA
10000 = 850 mA
10001 = 900 mA
10010 = 950 mA
10011 = 1000 mA
10100 = 1050 mA
10101 = 1100 mA
10110 = 1200 mA
10111 to 11111 = 1300 mA
ICHG JEITA1
50 mA
50 mA
50 mA
100 mA
100 mA
150 mA
150 mA
200 mA
200 mA
250 mA
250 mA
300 mA
300 mA
350 mA
350 mA
400 mA
400 mA
450 mA
450 mA
500 mA
500 mA
550 mA
600 mA
650 mA
Symbol
IJEITA_COLD
IJEITA_COOL
IJEITA_TYP
IJEITA_WARM
IJEITA_HOT
Conditions
No battery charging occurs.
Battery termination voltage (VTRM) is reduced by 100 mV from the
programmed value.
Normal battery charging occurs at the default/programmed levels.
Battery termination voltage (VTRM) is reduced by 100 mV from the
programmed value.
No battery charging occurs.
Rev. 0 | Page 23 of 44
Min
0
Max
0
10
Unit
C
C
10
45
45
60
C
C
60
ADP5063
Data Sheet
POWER-ON RESET
RESET ALL
REGISTERS
NO
NO
IC OFF
VIN_OK =
HIGH
SYSTEM
OFF
YES
YES
ENABLE
CHARGER
NO
ENABLE
LDO
YES
ENABLE
CHARGER
LDO MODE
NO
YES
YES
NO
VBAT_SNS
< VCHG_VLIM
NO
YES
TO
CHARGING MODE
Rev. 0 | Page 24 of 44
11593-032
LOW
BATTERY
CHG
Data Sheet
ADP5063
TO CHARGING
MODE
TO IC OFF
YES
RUN
BATTERY
DETECTION
tSTART
NO
EXPIRED
YES
VBAT_SNS
< VTRK
NO
POWER-DOWN
TRICKLE
CHARGE
VIN_OK =
HIGH
FAST CHARGE
NO
VIN_OK =
HIGH
YES
VBAT_SNS
< VTRK
YES
NO
YES
NO
VIN_ILIM = HIGH
IVINx = ILIM
NO
THERM_LIM = HIGH
TEMP = TLIM
YES
YES
WATCHDOG
EXPIRED
START tSAFE
IBUS = 100mA
NO
tWD EXPIRED
NO
YES
TIMER FAULT
OR
BAD BATTERY
YES
tSAFE OR tTRK
EXPIRED
tWD EXPIRED
YES
NO
WATCHDOG
EXPIRED
START tSAFE
IBUS = 100 mA
NO
tSAFE OR tCHG
YES1
EXPIRED
NO
RUN
BATTERY
DETECTION
VBAT_SNS =
VTRM
YES
NO
CC MODE
CHARGING
NO
CV MODE
CHARGING
CHARGE
COMPLETE
YES
Rev. 0 | Page 25 of 44
11593-033
YES
VBAT_SNS =
VRCH
NO
TIMER FAULT OR
BAD BATTERY
ADP5063
Data Sheet
I2C INTERFACE
the master after the 8-bit data byte has been written (see Figure 31
for an example of the I2C write sequence to a single register).
The ADP5063 increments the subaddress automatically and
starts receiving a data byte at the next register until the master
sends an I2C stop, as shown in Figure 32.
Register values are reset to the default values when the VINx
supply falls below the falling voltage threshold, VVIN_OK_FALL.
The I2C registers also reset when the battery is disconnected
and VIN is 0 V.
The subaddress content selects which of the ADP5063 registers
is written to first. The ADP5063 sends an acknowledgement to
0 = WRITE
0
CHIP ADDRESS
0
SUBADDRESS
0 SP
ADP5063 RECEIVES
DATA
11593-034
ADP5063 ACK
ADP5063 ACK
ADP5063 ACK
ST
MASTER STOP
CHIP ADDRESS
0
SUBADDRESS
REGISTER N
0
ADP5063 RECEIVES
DATA TO REGISTER N
ADP5063 RECEIVES
DATA TO REGISTER N + 1
0 SP
ADP5063 RECEIVES
DATA TO LAST REGISTER
11593-035
ADP5063 ACK
ADP5063 ACK
ADP5063 ACK
ADP5063 ACK
ADP5063 ACK
ST
MASTER STOP
CHIP ADDRESS
1 SP
MASTER ACK
SUBADDRESS
ADP5063 ACK
CHIP ADDRESS
0 ST 0 0 1 0 1 0 0 1
ADP5063 ACK
0 0 1 0 1 0 0 0 0
ADP5063 ACK
ST
MASTER
STOP
1 = READ
ADP5063 SENDS
DATA
11593-036
0 = WRITE
ADP5063 SENDS
DATA OF REGISTER N
Rev. 0 | Page 26 of 44
ADP5063 SENDS
DATA OF REGISTER
N+1
1 SP
ADP5063 SENDS
DATA OF LAST
REGISTER
11593-037
CHIP ADDRESS
MASTER ACK
MASTER ACK
0 ST 0 0 1 0 1 0 0 1 0 0
MASTER ACK
CHIP ADDRESS
SUBADDRESS
REGISTER N
ADP5063 ACK
0 0 1 0 1 0 0 0 0
ADP5063 ACK
ST
MASTER
STOP
1 = READ
ADP5063 ACK
0 = WRITE
Data Sheet
ADP5063
These bits reset to default I2C values when VINx is connected or disconnected.
The default I2C values of these bits are partially factory programmable.
3
The default I2C values of these bits are fully factory programmable.
2
Rev. 0 | Page 27 of 44
ADP5063
Data Sheet
Bit Name
MANUF[3:0]
MODEL[3:0]
Access
R
R
Default
0001
1001
Description
The 4-bit manufacturer identification bus
The 4-bit model identification bus
Bit Name
Not used
REV[3:0]
Access
R
R
Default
Description
0111
Bit Name
Not used
ILIM[3:0]
Access
R
R/W
Default
Description
0000 = 100 mA
VINx input current-limit programming bus. The current into VINx can
be limited to the following programmed values:
0000 = 100 mA.
0001 = 150 mA.
0010 = 200 mA.
0011 = 250 mA.
0100 = 300 mA.
0101 = 400 mA.
0110 = 500 mA.
0111 = 600 mA.
1000 = 700 mA.
1001 = 800 mA.
1010 = 900 mA.
1011 = 1000 mA.
1100 = 1200 mA.
1101 = 1500 mA.
1110 = 1800 mA.
1111 = 2100 mA.
Rev. 0 | Page 28 of 44
Data Sheet
ADP5063
Bit Name
VTRM[5:0]
Access
R/W
Default
000101 = 3.60 V
[1:0]
CHG_VLIM[1:0]
R/W
00 = 3.2 V
Description
Termination voltage programming bus. The values of the floating voltage can
be programmed to the following values:
000101 = 3.60 V.
000110 = 3.62 V.
000111 = 3.64 V.
001000 = 3.66 V.
001001 = 3.68 V.
001010 = 3.70 V.
001011 = 3.72 V.
001100 = 3.74 V.
001101 = 3.76 V.
001110 = 3.78 V.
001111 = 3.80 V.
010000 = 3.82 V.
010001 = 3.84 V.
010010 = 3.86 V.
010011 = 3.88 V.
010100 = 3.90 V.
010101 = 3.92 V.
010110 = 3.94 V.
010111 = 3.96 V.
011000 = 3.98 V.
011001 = 4.00 V.
011010 = 4.02 V.
011011 = 4.04 V.
011100 = 4.06 V.
011101 = 4.08 V.
011110 = 4.10 V.
011111 = 4.12 V.
100000 = 4.14 V.
100001 = 4.16 V.
100010 = 4.18 V.
100011 = 4.20 V.
100100 = 4.22 V.
100101 = 4.24 V.
100110 = 4.26 V.
100111 = 4.28 V.
101000 = 4.30 V.
101001 = 4.32 V.
101010 = 4.34 V.
101011 = 4.36 V.
101100 = 4.38 V.
101101 = 4.40 V.
101110 = 4.42 V.
101111 = 4.44 V.
110000 = 4.44 V.
110001 = 4.46 V.
110010 = 4.48 V.
110011 to 111111 = 4.50 V.
Charging voltage limit programming bus. The values of the charging voltage
limit can be programmed to the following values:
00 = 3.2 V.
01 = 3.4 V.
10 = 3.7 V.
11 = 3.8 V.
Rev. 0 | Page 29 of 44
ADP5063
Data Sheet
Bit Name
Not used
ICHG[4:0]
Access
R
R/W
Default
Description
01110 = 750 mA
[1:0]
ITRK_DEAD[1:0]
R/W
10 = 20 mA
Bit Name
DIS_RCH
Access
R/W
Default
0 = recharge
enabled
[6:5]
VRCH[1:0]
R/W
11 = 260 mV
Description
0 = recharge enabled.
1 = recharge disabled.
Recharge voltage programming bus. The values of the recharge
threshold can be programmed to the following values (note that
the recharge cycle can be disabled in I2C by using the DIS_RCH bit):
00 = 80 mV.
01 = 140 mV.
10 = 200 mV.
11 = 260 mV.
Rev. 0 | Page 30 of 44
Data Sheet
ADP5063
Bit No.
[4:3]
Bit Name
VTRK_DEAD[1:0]
Access
R/W
Default
00 = 2.0 V
[2:0]
VWEAK[2:0]
R/W
011 = 3.0 V
Description
Trickle to fast charge dead battery voltage programming bus. The
values of the trickle to fast charge threshold can be programmed to
the following values:
00 = 2.0 V.
01 = 2.5 V.
10 = 2.6 V.
11 = 2.9 V.
Weak battery voltage rising threshold.
000 = 2.7 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.1 V.
101 = 3.2 V.
110 = 3.3 V.
111 = 3.4 V.
Bit Name
Not used
EN_TEND
Access
Default
Description
R/W
EN_CHG_TIMER
R/W
CHG_TMR_PERIOD
R/W
EN_WD
R/W
WD_PERIOD
R/W
RESET_WD
Bit Name
Not used
DIS_IC1
Access
Default
Description
R/W
EN_BMON
R/W
EN_THR
R/W
DIS_LDO
R/W
0 = normal operation.
1 = the ADP5063 is disabled; VVINx must be VISO_Bx < VVINx < 5.5 V.
0 = when VVINx < VVIN_OK_RISE or VVIN_OK_FALL, the battery monitor is
disabled. When VVINx = 4 V to 6.7 V, the battery monitor is enabled
regardless of the EN_BMON state.
1 = the battery monitor is enabled even when the voltage at the
VINx pins is below VVIN_OK.
0 = when VVINx < VVIN_OK_RISE or VVIN_OK_FALL, the THR current source is
disabled. When VVINx = 4 V to 6.7 V, the THR current source is
enabled regardless of the EN_THR state.
1 = THR current source is enabled even when the voltage at the
VINx pins is below VVIN_OK_RISE or VVIN_OK_FALL.
0 = LDO is enabled.
1 = LDO is off. In addition, if EN_CHG = low, the battery isolation
FET is on. If EN_CHG = high, the battery isolation FET is off.
Rev. 0 | Page 31 of 44
ADP5063
Data Sheet
Bit No.
2
Bit Name
EN_EOC
Access
R/W
Default
1
Description
0 = end of charge not allowed.
1 = end of charge allowed.
1
0
Not used
EN_CHG
R/W
Bit Name
EN_JEITA
Access
R/W
Default
0 = JEITA disabled
JEITA_SELECT
R/W
0 = JEITA1
EN_CHG_VLIM
R/W
[4:3]
IDEAL_DIODE[1:0]
R/W
00
[2:0]
VSYSTEM[2:0]
R/W
000 = 4.3 V
Description
0 = JEITA compliance of the Li-Ion temperature battery charging
specifications is disabled.
1 = JEITA compliance enabled.
0 = JEITA1 is selected.
1 = JEITA2 is selected.
0 = charging voltage limit disabled.
1 = voltage limit enabled. The charger prevents charging until the
battery voltage drops below the VCHG_VLIM threshold.
00 = ideal diode operates constantly when VISO_Sx < VISO_Bx.
01 = ideal diode operates when VISO_Sx < VISO_Bx and VBAT_SNS > VWEAK.
10 = ideal diode is disabled.
11 = ideal diode is disabled.
System voltage programming bus. The values of the system voltage
can be programmed to the following values:
000 = 4.3 V.
001 = 4.4 V.
010 = 4.5 V.
011 = 4.6 V.
100 = 4.7 V.
101 = 4.8 V.
110 = 4.9 V.
111 = 5.0 V.
Bit Name
Not used
EN_THERM_LIM_INT
Access
Default
Description
R/W
EN_WD_INT
R/W
EN_TSD_INT
R/W
EN_THR_INT
R/W
EN_BAT_INT
R/W
EN_CHG_INT
R/W
EN_VIN_INT
R/W
Rev. 0 | Page 32 of 44
Data Sheet
ADP5063
Bit Name
Not used
THERM_LIM_INT
Access
Default
Description
WD_INT
TSD_INT
THR_INT
BAT_INT
CHG_INT
VIN_INT
0 = no interrupt.
1 = indicates an interrupt caused by isothermal charging.
0 = no interrupt.
1 = indicates an interrupt caused by the watchdog alarm. The
watchdog timer expires within 2 sec or 4 sec, depending on the
watchdog period setting of 32 sec or 64 sec, respectively.
0 = no interrupt.
1 = indicates an interrupt caused by an overtemperature fault.
0 = no interrupt.
1 = indicates an interrupt caused by THR temperature thresholds.
0 = no interrupt.
1 = indicates an interrupt caused by battery voltage thresholds.
0 = no interrupt.
1 = indicates an interrupt caused by a charger mode change.
0 = no interrupt.
1 = indicates an interrupt caused by VINx voltage thresholds.
Bit Name
VIN_OV
VIN_OK
VIN_ILIM
Access
R
R
R
Default
N/A
N/A
N/A
THERM_LIM
N/A
CHDONE
N/A
[2:0]
CHARGER_STATUS[2:0]
N/A
Description
1 = the voltage at the VINx pins exceeds VVIN_OV.
1 = the voltage at the VINx pins exceeds VVIN_OK_RISE and VVIN_OK_FALL.
1 = the current into a VINx pin is limited by the high voltage blocking
FET and the charger is not running at the full programmed ICHG.
1 = the charger is not running at the full programmed ICHG but is
limited by the die temperature.
1 = the end of a charge cycle has been reached. This bit latches on,
in that it does not reset to low when the VRCH threshold is breached.
Charger status bus.
000 = off.
001 = trickle charge.
010 = fast charge (CC mode).
011 = fast charge (CV mode).
100 = charge complete.
101 = LDO mode.
110 = trickle or fast charge timer expired.
111 = battery detection.
Rev. 0 | Page 33 of 44
ADP5063
Data Sheet
Mnemonic
THR_STATUS[2:0]
Access
R
Default
N/A
Description
THR pin status.
000 = off.
001 = battery cold.
010 = battery cool.
011 = battery warm.
100 = battery hot.
111 = thermistor OK.
4
3
Not used
RCH_LIM_INFO
N/A
[2:0]
BATTERY_STATUS[2:0]
Bit Name
Not used
BAT_SHR
Access
Default
Description
R/W
0 = no fault.
1 = indicates detection of a battery short.
2
1
Not used
TSD 130C
R/W
R/W
TSD 140C
R/W
0 = no fault.
1 = indicates an overtemperature (lower) fault.
0 = no fault.
1 = indicates an overtemperature fault.
To reset the fault bits in the fault register, cycle the power on VINx or write the corresponding I2C bit high.
Bit Name
TBAT_SHR[2:0]
Access
R/W
Default
100 = 30 sec
Description
Battery short timeout timer.
000 = 1 sec.
001 = 2 sec.
010 = 4 sec.
011 = 10 sec.
100 = 30 sec.
101 = 60 sec.
110 = 120 sec.
111 = 180 sec.
[4:3]
[2:0]
Not used
VBAT_SHR[2:0]
R/W
100 = 2.4 V
Data Sheet
ADP5063
Bit Name
IEND[2:0]
Access
R/W
Default
010 = 52.5 mA
C/20 EOC
R/W
C/10 EOC
R/W
C/5 EOC
R/W
1:0
SYS_EN_SET[1:0]
R/W
00
Description
Termination current programming bus. The values of the termination current can
be programmed to the following values:
000 = 12.5 mA.
001 = 32.5 mA.
010 = 52.5 mA.
011 = 72.5 mA.
100 = 92.5 mA.
101 = 117.5 mA.
110 = 142.5 mA.
111 = 170.0 mA.
The C/20 EOC bit has priority over the other settings (C/5 EOC, C/10 EOC, and
IEND[2:0]).
0 = not active.
1 = the termination current is ICHG[4:0] 20 with the following limitations:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
The C/10 EOC bit has priority over the other termination current settings (C/5 EOC
and IEND[2:0]), but it does not have priority over the C/20 EOC setting.
0 = not active.
1 = the termination current is ICHG[4:0] 10, unless C/20 EOC is high. The
termination current is limited to the following values:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
The C/5 EOC bit has priority over the other termination current settings (IEND[2:0])
but it does not have priority over the C/20 EOC setting or the C/10 EOC setting.
0 = not active.
1 = the termination current is ICHG[4:0] 5, unless the C/20 EOC or the C/10 EOC
bit is high. The termination current is limited to the following values:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
Selects the operation of the system enable pin (SYS_EN).
00 = SYS_EN is activated when the LDO is active and the system voltage is available.
01 = SYS_EN is activated by the ISO_Bx voltage, the battery charging mode.
10 = SYS_EN is activated and the isolation FET is disabled when the battery drops
below VWEAK. 1
11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active
in charging mode when VISO_Bx VWEAK.
This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit 5 (EN_BMON).
Rev. 0 | Page 35 of 44
ADP5063
Data Sheet
APPLICATIONS INFORMATION
Substituting these values in the equation yields
EXTERNAL COMPONENTS
ISO_Sx
ISO_Bx
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
60
50
CAPACITANCE (F)
IC1
SUM OF EFFECTIVE
CAPACITANCES
ON ISO_Sx NODE > 10F
CISO_Bx
10F
VIN2
IC2
11593-038
CIN2
55
45
40
35
30
11593-041
25
20
VIN1
CIN1
ADP5063
CISO_Sx > 5F
Rev. 0 | Page 36 of 44
Data Sheet
ADP5063
Part Number
GRM31CR61A226KE19
GRM31CR60J226ME19
C3216X5R0J226M
JMK316ABJ226KL-T
Value
22 F
22 F
22 F
22 F
Voltage
10 V
6.3 V
6.3 V
6.3 V
Size
1206
1206
1206
1206
Part Number
GRM155R70J104KA01
C1005X7R1A104K050BB
Value
100 nF
100 nF
Voltage
6.3 V
10 V
Size
0402
0402
Rev. 0 | Page 37 of 44
Part Number
GRM21BR61E106MA73
C2012X5R1E106K
Value
10 F
10 F
Voltage
25 V
25 V
Size
0805
0805
ADP5063
Data Sheet
VIN1 TO VIN3
ADP5063
20-LEAD LFCSP
19
ISO_S1 TO ISO_S3
CBP
C1
100nF
9
10
GRM155R70J104KA01
11
C3
22F
GRM31CR60J226ME19
VDDIO
R1
1.5k
R2
1.5k
CHARGER
CONTROL
BLOCK
TO MCU
SCL
TO MCU
17
SDA
12
TO MCU/NC
DIG_IO1
13
TO MCU/NC
DIG_IO2
TO MCU/NC
DIG_IO3
14
ISO_B1 TO ISO_B3
BAT_SNS
VDDIO
CONNECT
CLOSE TO
BATTERY +
THR 18
R4
10k
TO MCU
VLED
16
SYS_EN
15
ILED
C2
22F
R5 NTC 10k
(OPTIONAL)
GRM31CR60J22ME19
AGND
11593-040
20
C1: 100nF,
16V/X7R,
0402
CBP
ISO_Bx
PGND
C2: 22F,
16V/X5R,
1206
ISO_Sx
PGND
VINx
C4: 10F,
25V/X5R,
0805
PGND
11593-100
C3: 22F,
16V/X5R,
1206
Rev. 0 | Page 38 of 44
Data Sheet
ADP5063
(1)
where:
PLDOFET is the power dissipated in the input LDO FET.
PISOFET is the power dissipated in the battery isolation FET.
Calculate the power dissipation in the LDO FET and the battery
isolation FET using Equation 2 and Equation 3.
PLDOFET = (VIN VISO_Sx) (ICHG + ILOAD)
(2)
(3)
where:
VIN is the input voltage at the VINx pins.
VISO_Sx is the system voltage at the ISO_Sx pins.
ICHG is the battery charge current.
ILOAD is the system load current from the ISO_Sx pins.
VISO_Bx is the battery voltage at the ISO_Bx pins.
(4)
where:
RDSON_ISO is the on resistance of the battery isolation FET
(typically 110 m during charging).
ICHG is the battery charge current.
The thermal control loop of the ADP5063 automatically limits
the charge current to maintain a die temperature below TLIM
(typically 115C).
The most intuitive and practical way to calculate the power
dissipation in the ADP5063 device is to measure the power
dissipated at the input and all of the outputs. Perform the
measurements at the worst-case conditions (voltages, currents,
and temperature). The difference between input and output
power is the power that is dissipated in the device.
JUNCTION TEMPERATURE
In cases where the board temperature, TA, is known, the thermal
resistance parameter, JA, can be used to estimate the junction
temperature rise. TJ is calculated from TA and PD using the formula
TJ = TA + (PD JA)
(5)
LDO Mode
The system regulation voltage is user-programmable from 4.3 V
to 5.0 V. In LDO mode (charging disabled, EN_CHG = low),
calculation of the total power dissipation is simplified, assuming
that all current is drawn from the VINx pins and the battery is
not shared with ISO_Sx.
PD = (VIN VISO_Sx) ILOAD
Charging Mode
In charging mode, the voltage at the ISO_Sx pins depends on
the battery level. When the battery voltage is lower than VISO_SFC
(typically 3.4 V), the voltage drop over the battery isolation FET
is higher and the power dissipation must be calculated using
TJ = TC + (PD JC)
(6)
Rev. 0 | Page 39 of 44
ADP5063
Data Sheet
FACTORY-PROGRAMMABLE OPTIONS
CHARGER OPTIONS
Table 37 to Table 49 list the factory-programmable options of
the ADP5063. In each of these tables, the selection column
represents the default setting of Model ADP5063ACPZ-1-R7.
Table 37. Default Termination Voltage
Option
000 = 4.20 V
001 = 3.60 V
010 = 3.70 V
011 = 3.80 V
100 = 3.90 V
101 = 4.00 V
110 = 4.10 V
111 = 4.40 V
Selection
001 = 3.60 V
Selection
100 = 750 mA
Selection
000 = 52.5 mA
Selection
0 = 10 k
Selection
0100 = 3150
Selection
0 = DIC_IC1 mode select, VINx
current = 280 A, ISO_Bx can
float, no leak to ISO_Bx
Selection
000 = 4.3 V
Option
0 = 10 k
1 = 100 k
Option
000 = 4.3 V
001 = 4.4 V
010 = 4.5 V
011 = 4.6 V
100 = 4.7 V
101 = 4.8 V
110 = 4.9 V
111 = 5.0 V
Selection
01 = 2.0 V
Option
0 = after timeout LDO off,
charging off
1 = after timeout LDO mode
active, charging off
Rev. 0 | Page 40 of 44
Selection
Data Sheet
ADP5063
DIS_RCH
EN_WD
DIS_IC1
EN_CHG
EN_JEITA
JEITA_SELECT
EN_CHG_VLIM
IDEAL_DIODE[1:0]
Option
0 = limit 3.2 V
1 = limit 3.7 V
0 = recharge enabled
1 = recharge disabled
0 = watchdog disabled
1 = watchdog enabled
0 = not activated
1 = activated
0 = charging disabled
1 = charging enabled
0 = JEITA function disabled
1 = JEITA function enabled
0 = JEITA1 charging
1= JEITA2 charging
0 = limit disabled
1 = limit enabled
00 = ideal diode operates when VISO_Sx < VISO_Bx
Selection
0 = limit 3.2 V
0 = recharge enabled
0 = disabled
0 = not activated
0 = charging disabled
0 = JEITA function disabled
0 = JEITA1 charging
0 = limit disabled
00 = ideal diode operates
when VISO_Sx < VISO_Bx
This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON).
Rev. 0 | Page 41 of 44
Selection (Default)
00
ADP5063
Data Sheet
Selection
0 = high active
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DIG_IO1 Function
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
Charging
Low = charging disabled
High = charging enabled
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High = 500 mA
IVINx limit
Not applicable
High = IVINx limit 1500 mA
Disable IC1
Low = not activated
High = activated
DIG_IO2 Function
Disable IC1
Low = not activated
High = activated
IVINx limit
Not applicable
High = IVINx limit at 1500 mA
IVINx limit
Not applicable
High = IVINx limit at 1500 mA
IVINx limit
Not applicable
High = IVIN limit at 1500 mA
IVINx limit
Not applicable
High = IVINx limit at 1500 mA
Recharge
Not applicable
High = disable recharge
Disable IC1
Low = not activated
High = activated
IVINx limit
Not applicable
High = IVINx limit 1500 mA
Charging
Low = charging disabled
High = charging enabled
Disable IC1
Low = not activated
High = activated
Recharge
Not applicable
High = disable recharge
Fast charge current
Low = ICHG
High = ICHG[4:0] 2
LDO
Low = LDO active
High = LDO disabled
Charging
Low = charging disabled
High = charging enabled
Charging
Low = charging disabled
High = charging enabled
Rev. 0 | Page 42 of 44
DIG_IO3 Function
Charging disable/enable
Low = charging disable
High = charging enabled
Disable IC1
Low = not activated
High = activated
Fast charge current
Low = ICHG[4:0]
High = ICHG[4:0] 2
LDO
Low = LDO active
High = LDO disabled
Charging
Low = charging disabled
High = charging enabled
Charging
Low = charging disabled
High = charging enabled
Recharge
Not applicable
High = disable recharge
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Interrupt output
Not applicable
Not applicable
Selection
0101
Data Sheet
ADP5063
PIN 1
INDICATOR
20
16
15
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
5
10
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
020509-B
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
ORDERING GUIDE
Model 1, 2
ADP5063ACPZ-1-R7
ADP5063CP-EVALZ
1
2
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Rev. 0 | Page 43 of 44
Package Option
CP-20-8
ADP5063
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
Rev. 0 | Page 44 of 44