ISDRS 2009, December 9-11, 2009, College Park, MD, USA

Student Paper

Design of ADCs and DACs using 3-state Quantum DOT Gate FETs
Supriya Karmakar, Anjana P. Suresh, John A. Chandy, Faquir C. Jain
Department of Electrical and Computer Engineering, University of Connecticut
371, Fairfield Way, U-2157, Storrs, 06269-2157
Email: suk06001@engr.uconn.edu
Abstract: This paper presents the circuit model of 3-state quantum dot gate FETs and design of
three bit Analog to Digital Converter (ADC) and Digital to Analog (DAC) converter based on
that model.
Vdd

I. Introduction: In quantum dot gate FETs, the drain current is

independent of gate voltage in certain region. We generate a circuit
model [1] for a quantum dot gate FET in verilog AHDL. According
to this model when the Gate voltage is within the upper threshold
voltage (Vg2) and the lower threshold voltage (Vg1), drain current is
independent of the gate-source (VGS) voltage.

P-QDFET

Vout

Vin

II. Comparator: The basic building block of an Analog to Digital

Converter (ADC) and a Digital to Analog Converter (DAC) is the
comparator. Figure 1 is showing the comparator circuit based on
variable threshold voltage transistor. Here the variable threshold
voltage transistor changes the switching voltage or the reference
voltage of the comparator based on its threshold voltage.

N-QDFET

Variable
Threshold Voltage
QDFET

III. Analog to Digital Converter (ADC): The threshold voltage

Gnd

of Quantum dot gate FET depends on the device parameters which

Figure 1: Comparator
can be controlled during fabrication. Using these controllable
properties, we can fabricate 3-state Quantum DOT FETs having different threshold voltage. The
conventional flash architecture of Analog to Digital converter is shown in figure 2. These
variable threshold voltage FETs is used to switch the reference voltage of a comparator which is
used to quantize the input analog signal in different signal levels. The 8-to-3 encoder following
the comparators, converts different voltage levels into different digital bit combinations.
Analog Input
Voltage(Vin)

Over Range

(2 N -1) to
N Encoder

Comparators

Digital
O utput

Priority
Encoder(PE )

(a)

(b)

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ISDRS 2009, December 9-11, 2009, College Park, MD, USA

Figure 2: (a) 3-Bit Analog To Digital Converter (ADC) (b) 3-Bit ADC Output

IV. Digital to Analog Converter (DAC): Digital to Analog converter (DAC) works in
the opposite convention of Analog to Digital Converter. The Digital input is decoded
using 3-8 decoder. The variable threshold voltage comparators in the output convert these
decoded input in different analog voltage output based on there threshold voltage. Figure
3(a) shows the designed DAC architecture and Figure 3(b) shows the corresponding
input-output voltages.

Comparators

Most
Significant
Bit(MSB)
3-8
Decoder

Analog Output

Least
Significant
Bit(LSB)

(a)
(b)
Figure 3: (a) 3-Bit Digital to Analog Converter (DAC) (b) 3-Bit DAC Output

V. Conclusion: In this paper, we have presented the circuit diagram of 3-Bit Analog to
Digital converter and Digital to Analog converter based on Quantum dot gate FET. The
controllable threshold voltage of these devices made them effective for ADC and DAC
circuit design application. Precise control of the comparator reference voltage by
controlling the threshold voltage of QDFET makes this circuit free from the R-2R ladder
problem. In addition to their usefulness in ADC and DAC applications, three-state
quantum dot gate FET also provide many advantages such as more bit handling capacity
with fewer circuit elements. However, more testing is needed in order for them to be
promising circuit elements in the future.
This work is supported by ONR Contracts N00014-02-1-0883 and N00014-06-1-0016,
and NSF Grant ECS 0622068. Discussions with Dr. D. Purdy (ONR) and Dr. R. Khosla
(NSF) are gratefully acknowledged.
References:
[1] John A. Chandy and Faquir C. Jain, Multiple Valued Logic Using 3-State Quantum
Dot Gate FETs in Proceedings of International Symposium on Multiple Valued
Logic,08
[2] F.C.Jain, E.Heller, S.Karmakar, and J.Chandy, Device and Circuit Modeling using
novel 3-state quantum DOT gate FETs in Proceedings of International Semiconductor
Device Research Symposium, Dec. 2007.
[3] F.C.Jain, E.Suarez, M.Gogna, F.AlAmoody, D.Butkiewicus, R.Hohner, T.Liaskas,
S.Karmakar, P.Y.Chan, B.miller, J.Chandy and E.Heller, Novel Quantum Dot Gate
FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators, Journal
of ELECTRONIC MATERIALS, Vol. 38, No. 8, 2009.
ISDRS 2009 http://www.ece.umd.edu/ISDRS2009