ANALYSIS, DESIGN AND CONTROL OF A UNIFIED

POWER-QUALITY CONDITIONER BASED ON A

CURRENT-SOURCE TOPOLOGY AND ANN

ABSTRACT
The theory and modeling of unified power quality conditioner (UPQC), a FACTS device,
is described in this paper. This paper discusses the compensation principle and control strategy of
the UPQC in detail. This paper presents a three - phase unified power quality conditioner based
on current source converters (CSCUPQC), including the design guide lines of the key
components, an appropriate control scheme includes the artificial neural networks (ANN), and a
selection procedure of the dc current level. Particularly, the ride through capability
criterion is used to define a minimum dc current level so that the CSC - UPQC achieves the same
characteristics as a UPQC based on voltage-source converters in terms of voltage disturbance
compensation in the point of common coupling (PCC) and load power factor compensation. The
control law is incorporated in a previously proposed current controller, which is designed for
good voltage sag ride-through capability. The proposed UPQC-CSC design has superior
performance for mitigating the power quality problems. The proposed structure prevents voltage
sag and phase-angle jump of the substation PCC after fault occurrence. This structure has a
simple control method. A 1.17 MVA load fed from a 3.3 kV system is used to show the proposed
design procedure, and a laboratory prototype is implemented to show the system compensating
sags and swells using low switching frequency in the CSC and maintaining a unitary
displacement power factor in the PCC. The simulation results show that the ANN-controlled
UPQC can significantly reduce harmonic distortion in the supply system.

INTRODUCTION

Power quality is often defined as the electrical network's or the grid's ability to supply a
clean and stable power supply. In other words, power quality ideally creates a perfect power
supply that is always available, has a pure noise-free sinusoidal wave shape, and is always within
voltage and frequency tolerances. However, with increasing and varying energy demands from
various industrial processes, many loads regularly impose disturbances on the grid, making
deviations from these ideal conditions are frequent. Poor power quality is a problem for a many
industries, from data centers to offshore oil rigs. Low power quality contributes to high energy
cost and rising energy and production disturbances which is especially problematic for
increasingly sensitive modern production equipment. Ironically, it is often the equipment itself
that generates the disturbances. Unstable energy loads waste energy and cause electrical and
production disturbances. They are a growing problem in the electrical environment. Electrical
current behaviors that create losses constitute reactive behavior (phase displacement due to
electric or magnetic fields), harmonics (disturbances to production and/or the energy grid), and
unbalance (uneven power distribution between the phases in the electrical network). Current
behaviors that create electrical disturbances include transients (fast disturbances, bursts of
energy), voltage

variations, flicker, and resonance (oscillations

that cause

instability and

overloading). Traditionally, fixed electro-mechanical and semiconductor controlled filters and/or

compensators have been used to limit behaviors that waste energy. They operate mainly on a
fixed or stepped basis using passive elements.
But these solutions have multiple disadvantages - they add losses, are installationspecific, and have no ability to adapt to dynamic load changes. Active Filters, such
as ADF Power Tuning, eliminate energy-wasting behaviors such as harmonics, flicker, voltage
variations, and reactive energy using a highly dynamic, digitally controlled compensation and
filtering approach. ADF Power Tuning restores the current waveform instantaneously, lowers the
current consumption, and fully compensates changes in load or installation conditions at all
times. Read more about ADF Technology. Active filtering of electric power has now become a
mature technology for harmonic and reactive power compensation in two-wire (single phase),
three-wire (three phase without neutral), and four-wire (three phase with neutral) AC power
networks with nonlinear loads.

This paper proposes a series active filter and shunt active filter to minimize the power
quality impact present in matrix converters instead of passive filter. A matrix converter produces
significant harmonics and nonstandard frequency components into load. The proposed system
compensates the sag and swell problems efficiently in matrix converter. Power quality is a set of
limits or conditions of electrical properties that allows electrical devices to function in their
planned manner without loss of performance. The use of CSC in UPQCs should add the
advantages: 1) rapid response to accommodate voltage disturbances due to the existence of just a
first-order filter stage and 2) natural protection against short circuits due to the dc link reactor.
Without the proper power, an electrical utility may malfunction, fail permanently, or not operate
well. There are many possible ways in which electric power can be of poor quality and many
more causes or effects of such poor, quality power.
Ideally, the voltage is fed as a sinusoidal having a magnitude and a frequency given by
the international standards or system specifications with impedance of zero ohms at all
frequencies. Power quality disturbance is produced by the inverters and the converters. A matrix
converter is a three to three-phase configuration and is just one of the possible direct AC-AC
converter topologies. The unified power-quality conditioner (UPQC) in this paper is based on the
union of a series active filter and a shunt active filter sharing a common dc reactor. The resulting
equipment is installed close to a critical load (Fig. 1) and it has the ability to compensate
simultaneously with the PCC voltage and load power factor. Previous works concerning the
UPQC based on current source converters (CSC-UPQC) have presented control strategies but
they do not consider: 1) a deep analysis of the topology; 2) component and controllers design
guidelines, 3) considerations for choosing an operating point, nor 4) the natural limited
compensation capability of the equipment . This work reviews the aforementioned considerations
and proposes design guidelines for the components and control scheme parameters. The design
guidelines are used to characterize a UPQC for a 1.17 MVA linear load fed from a 3.3 kV
system, and a laboratory prototype is implemented and tested.

Fig. 1. UPQC application.

Current Source Inverters:

The main objective of these static power converters is tom produce ac output current
waveforms from a dc current power supply. For sinusoidal ac outputs, its magnitude, frequency,
and phase should be controllable. Due to the fact that the ac line currents ioa, iob, and ioc (Fig.
14.23) feature high di=dt, a capacitive filter should be connected at the ac terminals in inductive
load applications (such as ASDs).
Thus, nearly sinusoidal load voltages are generated that justifies the use of these
topologies in medium-voltage industrial applications, where high-quality voltage waveforms are
required.

should be closed at any time; the dc bus is of the current-source type and thus it cannot be
opened; therefore, there must be at least one top switch and one bottom switch (closed at all
times. Note that both constraints can be summarized by stating that at any time, only one top
switch and one bottom switch must be closed.
There are nine valid states in three-phase CSIs. produce zero ac line currents. In this case,
the dc link current freewheels through either the switches S1 and S4, switches S3 and S6, or
switches S5 and S2.
The remaining states produce nonzero ac output line currents. In order to generate a given
set of ac line current waveforms, the inverter must move from one state to another. Thus, the
resulting line currents consist of discrete values of current, which are ii , 0, and ii . The selection
of the states in order to generate the given waveforms is done by the modulating technique that
should ensure the use of only the valid states.
Carrier-based PWM Techniques in CSIs:
It has been shown that carrier-based PWM techniques that were initially developed for
three-phase VSIs can be extended to three-phase CSIs. Obtains the gating pattern for a CSI from
the gating pattern developed for a VSI. As a result, the line current appears to be identical to the
line voltage in a VSI for similar carrier and modulating signals.
It is composed of a switching pulse generator, a shorting pulsegenerator, a shorting pulse
distributor, and a switching and shorting pulse combinatory. The circuit basically produces the
gating signals ..S.1...6 . .S1 . . . S6.T . According to a carrier iD and three modulating signals
.ic .abc . .ica icb ica.T .

Therefore, any set of modulating signals which when combined result in a sinusoidal
line-to-line set of signals, will satisfy the requirement for a sinusoidal line current pattern.
Examples of such a modulating signals are the standard sinusoidal, sinusoidal with third
harmonic injection, trapezoidal, and dead band waveforms. The first component of this stage
(Fig. 14.24) is the switching pulse generator, where the signals .Sa.123 are generated according
to:

The outputs of the switching pulse generator are the signals .Sc .1...6, which are basically
the gating signals of the CSI without the shorting pulses. These are necessary to freewheel the dc
link current ii when zero ac output currents are required. Table 14.5 shows the truth table of .Sc .
1...6 for all combinations of their inputs .Sa.123. It can be clearly seen that at most one top
switch and one bottom switch is on, which satisfies the first constraint of the gating signals as
stated before.
In order to satisfy the second constraint, the shorting pulse .Sd . 1. is generated (shorting
pulse generator (when none of the top switches .Sc1 . Sc3 . Sc5 . 0. or none of the bottom
switches .Sc4 . Sc6 . Sc2 . 0. are gated. Then, this pulse is added (using OR gates) to only one leg
of the CSI (either to the switches 1 and 4, 3 and 6, or 5 and 2) by means of the switching and
shorting pulse combinatory./
The signals generated by the shorting pulse generator (a) only one leg of the CSI is
shorted, as only one of the signals is high at any time; and (b) there is an even distribution of the
shorting pulse, as .Se .123 is HIGH for 120_ in each period. This ensures that the rms currents
are equal in all legs. the relevant waveforms if a triangular carrier iD and sinusoidal modulating
signals .ic .abc are used in combination with the gating pattern generator this is SPWM in CSIs.
It can be observed that some of the waveforms are identical to those obtained in threephase VSIs, where a SPWM technique Specifically: (i) the load line VSI is identical to the load
line current; and (ii) the dc link current is identical to the dc link voltage in the CSI. This brings

up the duality issue between both topologies when similar modulation approaches are used.
Therefore, for odd multiple of 3 values of the normalized carrier frequency mf , the harmonics in
the ac output current appear at normalized frequencies fh centered around mf and its multiples,
specifically, at

where l . 1; 3; 5; . . . for k . 2; 4; 6; . . . and l . 2; 4; . . . for k . 1; 5; 7; . . . , such that h is not a

multiple of 3. herefore,the harmonics will be
; . . . .For nearly sinusoidal ac load
voltages, the harmonics in the DClinks voltage are at frequencies given by

where l . 0; 2; 4; . . . for k . 1; 5; 7; . . . , and l . 1; 3; 5; . . . for k . 2; 4; 6; . . . , such that h . l _ mf

_ k is positive and not a multiple of 3. For instance, Fig. 14.25h shows the sixth harmonic .h . 6.,
which is due to h . 1 _ 9 2 1 . 6. Identical conclusions can be drawn for the operation at small
and large values of mf in the same way as for three phase VSI configurations. Thus, the
maximum amplitude of

The three-phase CSI. Ideal waveforms for the SPWM .ma . 0:8, mf . 9): (a) carrier and
modulating signals; (b) switch S1 state; (c)switch S3 state; (d) ac output current; (e) ac output
current spectrum; (f) ac output voltage; (g) dc voltage; (h) dc voltage spectrum; (i) switch
S1current; ( j) Switch S1 voltage.

To further increase the amplitude of the load current, the over modulation approach can be used.
In this region, the fundamental line currents range in

To further test the gating signal generator circuit a sinusoidal set with third and ninth
harmonic injection modulating signals is used.

POWER QUALITY
Power

quality determines

the

fitness

of electric

power to consumer devices.

Synchronization of the voltage frequency and phase allows electrical systems to function in their
intended manner without significant loss of performance or life. The term is used to describe
electric power that drives an electrical load and the load's ability to function properly. Without
the proper power, an electrical device (or load) may malfunction, fail prematurely or not operate
at all. There are many ways in which electric power can be of poor quality and many more
causes of such poor quality power.
The electric power industry comprises electricity generation (AC power), electric power
transmission and ultimately electric power distribution to an electricity meter located at the
premises of the end user of the electric power. The electricity then moves through the wiring
system of the end user until it reaches the load. The complexity of the system to move electric
energy from the point of production to the point of consumption combined with variations in
weather, generation, demand and other factors provide many opportunities for the quality of
supply to be compromised.

While "power quality" is a convenient term for many, it is the quality of the voltage
rather than power or electric currentthat is actually described by the term. Power is simply the
flow of energy and the current demanded by a load is largely uncontrollable.
The quality of electrical power may be described as a set of values of parameters, such as:

Continuity of service

Variation in voltage magnitude (see below)

Transient voltages and currents

Harmonic content in the waveforms for AC power

It is often useful to think of power quality as a compatibility problem: is the equipment

connected to the grid compatible with the events on the grid, and is the power delivered by the
grid, including the events, compatible with the equipment that is connected? Compatibility
problems always have at least two solutions: in this case, either clean up the power, or make the
equipment tougher.
The tolerance of data-processing equipment to voltage variations is often characterized by
the CBEMA curve, which give the duration and magnitude of voltage variations that can be
tolerated.
Ideally, AC voltage is supplied by a utility as sinusoidal having an amplitude and frequency
given by national standards (in the case ofmains) or system specifications (in the case of a power
feed not directly attached to the mains) with an impedance of zero ohms at allfrequencies.
No real-life power source is ideal and generally can deviate in at least the following ways:

Variations in the peak or RMS voltage are both important to different types of equipment.

When the RMS voltage exceeds the nominal voltage by 10 to 80% for 0.5 cycle to 1
minute, the event is called a "swell".

A "dip" (in British English) or a "sag" (in American English the two terms are equivalent)
is the opposite situation: the RMS voltage is below the nominal voltage by 10 to 90% for 0.5
cycle to 1 minute.

Random or repetitive variations in the RMS voltage between 90 and 110% of nominal
can produce a phenomenon known as "flicker" in lighting equipment. Flicker is rapid visible
changes of light level. Definition of the characteristics of voltage fluctuations that produce
objectionable light flicker has been the subject of ongoing research.

Abrupt, very brief increases in voltage, called "spikes", "impulses", or "surges", generally
caused by large inductive loads being turned off, or more severely by lightning.

"Undervoltage" occurs when the nominal voltage drops below 90% for more than 1
minute. The term "brownout" is an apt description for voltage drops somewhere between full
power (bright lights) and a blackout (no power no light). It comes from the noticeable to
significant dimming of regular incandescent lights, during system faults or overloading etc.,
when insufficient power is available to achieve full brightness in (usually) domestic lighting.
This term is in common usage has no formal definition but is commonly used to describe a
reduction in system voltage by the utility or system operator to decrease demand or to
increase system operating margins.

"Overvoltage" occurs when the nominal voltage rises above 110% for more than 1
minute.

Variations in the frequency.

Variations in the wave shape usually described as harmonics.

Nonzero low-frequency impedance (when a load draws more power, the voltage drops).

Nonzero high-frequency impedance (when a load demands a large amount of current,

then stops demanding it suddenly, there will be a dip or spike in the voltage due to the
inductances in the power supply line).

Each of these power quality problems has a different cause. Some problems are a result
of the shared infrastructure. For example, a fault on the network may cause a dip that will affect
some customers; the higher the level of the fault, the greater the number affected. A problem on
one customers site may cause a transient that affects all other customers on the same subsystem.
Problems, such as harmonics, arise within the customers own installation and may propagate
onto the network and affect other customers. Harmonic problems can be dealt with by a
combination of good design practice and well proven reduction equipment.
Power conditioning is modifying the power to improve its quality.
An uninterruptible power supply can be used to switch off of mains power if there is
a transient (temporary) condition on the line. However, cheaper UPS units create poor-quality
power themselves, akin to imposing a higher-frequency and lower-amplitude square wave atop
the sine wave. High-quality UPS units utilize a double conversion topology which breaks down
incoming AC power into DC, charges the batteries, then remanufactures an AC sine wave. This
remanufactured sine wave is of higher quality than the original AC power feed.[2]
A surge protector or simple capacitor or varistor can protect against most overvoltage conditions,
while a lightning arrester protects against severe spikes.
Electronic filters can remove harmonics.

UNIFIED POWER-QUALITY CONDITIONER (UPQC)

A power conditioner (also known as a line conditioner or power line conditioner) is a
device intended to improve the quality of the power that is delivered to electrical load equipment.
While there is no official definition of a power conditioner, the term most often refers to a device
that acts in one or more ways to deliver a voltage of the proper level and characteristics to enable
load equipment to function properly. In some uses, power conditioner refers to a voltage
regulator with at least one other function to improve power quality (e.g. power factor correction,
noise suppression, transient impulse protection, etc.)

The terms "power conditioning" and "power conditioner" can be misleading, as the word
"power" here refers to the electricity generally rather than the more technical electric power.
Conditioners specifically work to smooth the sinusoidal A.C. wave form and maintain a
constant voltage over varying loads.
TYPES
An AC power conditioner is the typical power conditioner that provides "clean" AC power to
sensitive electrical equipment. Usually this is used for home or office applications and has up to
10 or more receptacles or outlets and commonly provides surge protection as well as noise
filtering.
'Power line conditioners take in power and modify it based on the requirements of the
machinery to which they are connected. Attributes to be conditioned are measured with various
devices, such as, Phasor measurement units. Voltage spikes are most common during electrical
storms or malfunctions in the main power lines. The surge protector stops the flow of electricity
from reaching a machine by shutting off the power source.
The term "Power Conditioning" has been difficult to define historically. However, with
the advances in power technology and recognition by IEEE, NEMA, and other standards
organizations, a new actual engineering definition has now been developed and accepted to
provide an accurate depiction of this definition.
"Power Conditioning" is the ability to filter the AC line signal provided by the power
company. "Power Regulation" is the ability to take a signal from the local power company, turn it
into a DC signal that will run an oscillator, which generates a single frequency sine wave,
determined by the local area needs, is fed to the input stage of power amplifier, and is then
output as specified as the ideal voltage present at any standard wall outlet.
DESIGN
A good quality power conditioner is designed with internal filter banks to isolate the
individual power outlets or receptacles on the power conditioner. This eliminates interference or

"cross-talk" between components. If the application will be a home theater system, the noise
suppression rating listed in the technical specifications of the power conditioner will be very
important. This rating is expressed in decibels (db). The higher the db rating, the better the noise
suppression.
The power conditioner will also have a "joule" rating. A joule is a measurement of energy
or heat required to sustain one watt for one second, known as a watt second. Since electrical
surges are momentary spikes, the joule rating indicates how much electrical energy the
suppressor can absorb at once before becoming damaged itself. The higher the joule rating, the
greater the protection.
USES
Power conditioners vary in function and size, generally according to their use. Some
power conditioners provide minimal voltage regulation while others protect against six or
more power quality problems. Units may be small enough to mount on a printed circuit board or
large enough to protect an entire factory.
Small power conditioners are rated in volt-amperes (VA) while larger units are rated in kilovoltamperes (kVA).
Ideally electric power would be supplied as a sine wave with the amplitude and frequency
given by national standards (in the case of mains) or system specifications (in the case of a
power feed not directly attached to the mains) with an impedance of zero ohms at all frequencies.
No real life power feed will ever meet this ideal. Deviations may include:

Variations in the peak or RMS voltage are both important to different types of equipment.

When the RMS voltage exceeds the nominal voltage by 10 to 80% for 0.5 cycle to 1
minute, the event is called a "swell".

A "dip" (in British English) or a "sag" (in American English the two terms are
equivalent) is the opposite situation: the RMS voltage is below the nominal voltage by 10 to
90% for 0.5 cycle to 1 minute.

Random or repetitive variations in the RMS voltage between 90 and 110% of nominal
can produce a phenomenon known as "flicker" in lighting equipment. Flicker is the
impression of unsteadiness of visual sensation induced by a light stimulus on the human eye.
A precise definition of such voltage fluctuations that produce flicker has been subject to
ongoing debate in more than one scientific community for many years.

Abrupt, very brief increases in voltage, called "spikes", "impulses", or "surges", generally
caused by large inductive loads being turned off, or more severely by lightning.

"Undervoltage" occurs when the nominal voltage drops below 90% for more than 1
minute. The term "brownout" in common usage has no formal definition but is commonly
used to describe a reduction in system voltage by the utility or system operator to decrease
demand or to increase system operating margins.

"Overvoltage" occurs when the nominal voltage rises above 110% for more than 1
minute.

Variations in the frequency

Variations in the wave shape usually described as harmonics

Nonzero low-frequency impedance (when a load draws more power, the voltage drops)

Nonzero high-frequency impedance (when a load demands a large amount of current,

then stops demanding it suddenly, there will be a dip or spike in the voltage due to the
inductances in the power supply line).

Voltage Source Inverters:

Half-bridge VSI:

Figure 2shows the power topology of a half-bridge VSI, where two large capacitors are
required to provide a neutral point N, such that each capacitor maintains a constant voltage vi /2.
Because the current harmonics injected by the operation of the inverter are low-order harmonics,
a set of large capacitors (C+ and C) is required.
It is clear that both switches S+ and S cannot be on simultaneously because a short
circuit across the dc link voltage source vi would be produced. There are two defined (states 1
and 2) and one undefined (state 3) switch state as shown in Table 2(a). In order to avoid the short
circuit across the dc bus and the undefined ac output-voltage condition, the modulating technique
should always ensure that at any instant either the top or the bottom switch of the inverter leg is
on

Fig2. Single-phase half-bridge VSI.

2(a).Switch states for a half-bridge single-phase VSI

Figure 3 shows the ideal waveforms associated with the half-bridge inverter shown in
Fig.2. The states for the switches S+ and S are defined by the modulating technique, which in
this case is a carrier-based PWM

A.The Carrier-based Pulse Width Modulation (PWM) Technique

As mentioned earlier, it is desired that the ac output voltage, vo = vaN , follow a given
waveform (e.g. sinusoidal) on a continuous basis by properly switching the power valves. The
carrier-based PWM technique fulfills such a requirement as it defines the on- and off-states of
the switches of one leg of a VSI by comparing a modulating signal vc (desired ac output voltage)
and a triangular waveform v_ (carrier signal). In practice, when vc > v_ the switch S+ is on and
the switch S is off; similarly, when vc < v_ the switch S+ is off and the switch S is on.
A special case is when the modulating signal vc is a sinusoidal at frequency fc and amplitude vc
, and the triangular signal v_ is at frequency f_ and amplitude v_. This is the sinusoidal PWM
(SPWM) scheme. In this case, the modulation index ma (also known as the amplitudemodulation ratio) is defined as

And the normalized carrier frequency mf (also known as the frequency-modulation ratio) is

Figure 3e clearly shows that the ac output voltage vo = vaN is basically a sinusoidal waveform
plus harmonics, which features:
(a) the amplitude of the fundamental component of the ac output voltage vo1 satisfying the
following expression:

for ma 1, which is called the linear region of the modulating technique (higher values of ma
leads to over modulation that will be discussed later);

FIGURE 3 The half-bridge VSI. Ideal waveforms for the SPWM (ma = 0.8, mf = 9):
(a) carrier and modulating signals; (b) switch S+ state; (c) switch S state; (d) ac output voltage;
(e) ac output voltage spectrum; (f) ac output current; (g) dc current;
(h) dc current spectrum; (i) Switch S+ current; and (j) diode D+ current.
(b) for odd values of the normalized carrier frequency mf the harmonics in the ac output voltage
appear at normalized frequencies fh centered around mf and its multiples, specifically,

Where k = 2, 4, 6, . . . for l = 1, 3, 5, . . .; and k = 1, 3, 5, . . . for l = 2, 4, 6,;

(c) the amplitude of the ac output voltage harmonics is a function of the modulation index ma
and is independent of the normalized carrier frequency mf for
mf > 9;
(d) the harmonics in the dc link current (due to the modulation) appear at normalized frequencies
fp centered around the normalized carrier frequency mf and its multiples, specifically,

Where k = 2, 4, 6, . . . for l = 1, 3, 5, . . .; and k = 1, 3, 5, . . . for l = 2, 4, 6, . . .. Additional

important issues are:
(a) for small values of mf (mf < 21), the carrier signal v_ and the signal vc should be
synchronized to each other (mf integer), which is required to hold the previous features; if this is
not the case, sub harmonics will be present in the ac output voltage;
(b) for large values of mf (mf > 21), the sub harmonics are negligible if an asynchronous PWM
technique is used, however, due to potential very low-order sub harmonics, its use should be
avoided; finally
(c) in the over modulation region (ma > 1) some intersections between the carrier and the
modulating signal are missed, which leads to the generation of low-order harmonics but a higher
fundamental ac output voltage is obtained; unfortunately, the linearity between ma and vo1
achieved in the linear region does not hold in the over modulation region, moreover, a saturation
effect can be observed (Fig. 4).
The PWM technique allows an ac output voltage to be generated that tracks a given
modulating signal. A special case is the SPWM technique (the modulating signal is a sinusoidal)
that provides, in the linear region, an ac output voltage that varies linearly as a function of the
modulation index, and the harmonics are at well-defined frequencies and amplitudes. These
features simplify the design of filtering components.
Unfortunately, the maximum amplitude of the fundamental ac voltage is vi/2 in this
operating mode. Higher voltages are obtained by using the over modulation region (ma > 1);

however, low-order harmonics appear in the ac output voltage. Very large values of the
modulation index (ma > 3.24) lead to a totally square ac output voltage that is considered as the
square-wave modulating technique.
B. Square-wave Modulating Technique
Both switches S+ and S are on for one half-cycle of the ac output period. This is equivalent to
the SPWM technique with an infinite modulation index ma. Figure 5 shows the following:

FIGURE4 : Normalized fundamental ac component of the output voltage in a half-bridge VSI

SPWM modulated.
(a) The normalized ac output voltage harmonics are at frequencies h = 3, 5, 7, 9, . . ., and for a
given dc link voltage;
(b) The fundamental ac output voltage features an amplitude given by

And the harmonics feature an amplitude given by

It can be seen that the ac output voltage cannot be changed by the inverter. However, it
could be changed by controlling the dc link voltage vi . Other modulating techniques that are
applicable to half-bridge configurations (e.g., selective harmonic elimination) are reviewed here
as they can easily be extended to modulate other topologies.

FIGURE 5 The half-bridge VSI. Ideal waveforms for the square-wave modulating technique: (a)
ac output voltage and (b) ac output voltage spectrum

C. Selective Harmonic Elimination

The main objective is to obtain a sinusoidal ac output voltage waveform where the
fundamental component can be adjusted arbitrarily within a range and the intrinsic harmonics
selectively eliminated. This is achieved by mathematically generating the exact instant of the
turn-on and turn-off of the power valves. The ac output voltage features odd half and quarterwave symmetry; therefore, even harmonics are not present (voh = 0, h = 2, 4, 6, . . .). Moreover,
the phase voltage waveform (vo = vaN in Fig. 2), should be chopped N times per half-cycle in

order to adjust the fundamental and eliminate N 1 harmonics in the ac output voltage
waveform. For instance, to eliminate the third and fifth harmonics

FIGURE 6 The half-bridge VSI. Ideal waveforms for the SHE technique:
(a) ac output voltage for third and fifth harmonic elimination;
(b) Spectrum of (a);
(c) Ac output voltage for third, fifth, and seventh harmonic elimination; and
(d) Spectrum of (c).
To perform fundamental magnitude control (N = 3), the equations to be solved are the following:

Where the angles 1, 2 and 3 are defined as shown in Fig. 6a. The angles are found by
means of iterative algorithms as no analytical solutions can be derived. The angles 1, 2, and 3
are plotted for different values of vo1/vi in Fig. 7a. The general expressions to eliminate an even
N 1, (N 1 = 2, 4, 6, . . .) number of harmonics are

Where 1, 2,, N should satisfy 1<2< <N </2. Similarly, to eliminate

an odd number of harmonics, for instance the third, fifth, and seventh, and to perform the
Fundamental magnitude control (N 1 = 3), the equations to be solved are:

Where the angles 1, 2, 3, and 4 are defined as shown in Fig. 6b. The angles 1, 2,
and 3 are plotted for different values of vo1/vi in Fig. 7b. The general expressions to eliminate
an odd N 1 (N 1 = 3, 5, 7, . . .) number of harmonics are given by

Where 1, 2, . . ., N should satisfy 1<2< <N </2. To implement the SHE

modulating technique, the modulator should generate the gating pattern according to the angles
as shown in Fig. 7. This task is usually performed by digital systems that normally store the
angles in look-up tables.
D. DC Link Current
The split capacitors are considered a part of the inverter and therefore an instantaneous
power balance cannot be considered due to the storage energy components (C+ and C).
However, if a lossless inverter is assumed, the average power absorbed in one period by the load
must be equal to the average power supplied by the dc source. Thus, we can write

Where T is the period of the ac output voltage. For an inductive load and a relatively high
switching frequency, the load current io is nearly sinusoidal and therefore, only the fundamental
component of the ac output voltage provides power to the load. On the other hand, if the dc link
voltage remains constant vi (t ) = Vi , Eq. (12) can be simplified to

Where Vo1 is the fundamental rms ac output voltage, Io is the rms load current, is an
arbitrary inductive load power factor, and Ii is the dc link current that can be further simplified to

UPQC-BASED-ON CURRENT SOURCE CONVERTERS

A . Operation and Description
The topology, in combination with the proposed control scheme, is able to modify the
voltage of the load and the current drained from the PCC . For the case of compensating the
voltage disturbances in the PCC, the series active filter stage injects a voltage in a controlled
manner for compensating either a sag [Fig. 2(d)] or a swell [Fig. 2(e)], while the load power
factor is compensated by modifying either the current in the PCC by means of the shunt filter
current or modifying the phase of the load voltage by means of the series active filter voltage
[Fig. 2(c)]. A back to back approach based on CSCs is used in the proposed UPQC [Fig. 2(a)].
The topology is connected to the distribution line through passive filters aimed at mitigating the
generated by the switching of the power valves of the CSCs. For the case of compensating the
voltage disturbances in the PCC, the series active filter stage injects a voltage in a controlled
manner for compensating either a sag [Fig. 2(d)] or a swell [Fig. 2(e)], while the load power
factor is compensated by modifying either the current in the PCC by means of the shunt filter

current or modifying the phase of the load voltage by means of the series active filter voltage
[Fig. 2(c)]. In this paper, the load power factor compensation is achieved using a fixed angle ,
while the shunt active filter stage: 1) compensates the phase shift introduced by the LC filter, 2)
compensates small variations in the load power factor, and 3) maintains constant the dc link
current, reducing the losses in the LC filter compared to compensating the full power factor with
this stage. Then, the angle of the load voltage is chosen as
=a cos ( p f pcc )=(1)
where is the load displacement angle, is the PCC power factor, and is the displacement angle in
the PCC.

UPQC based on current-source converters. (a) Power topology.

B . Modeling
According to Fig. 2(c), one can write

V 1a bc =V pcc a bc +nt V csa bc (2)

i pcca bc =i 1a bc +i pa bc (3)

V 1a bc =V pcc a bc +nt V csa bc =L p

i pa bc=irpa bc + C p

d a bc
i p +V cp a bc ( 4)
dt

d
V a bc (5)
dt cp

nt ( i1a bc + i p a bc ) +C s

d
V a bc +i rsa bc =0(6)
dt cs

V dcsV dcpRdc i dc Ldc

d
i ( 7)
dt dc

Finally, one can write in a synchronous frame

d dq 1
dq
dq
dq
V =
Gs mdq
s i dc nt ( i p +i 1 ) W s V cs (12)
dt cs C s

d dq 1 dq
dq
dq
V cp = ( i p G p mp i dc ) W s V cp (13)
dt
Cp
d dq 1
dq
dq
i =
V dq +nt V dq
cs V cp ) W s i p (14)
dt p L P ( p
cc

d
1
dq
dq
dq
i dc =
G s mdq
(
s V cs G p m p V cp Rdc i dc ) (15)
dt
Ldc
T

Where

W s=

][

0 w s
0
2 f s
=
16
ws
0
2 f s
0

And f s is the ac network frequency.

(b) Equivalent circuit per phase .

C.Ride through Capability and DC Current
The losses in the topology are a function of the dc current level, so the lower dc current in
the topology, the lower the losses are, while a higher dc link inductance implies a bigger
equipment size and internal resistance, increasing the losses due to the I 2 R factor. However, as
shown later, reducing the dc current level or the dc inductor size has implications on the CSCUPQC compensation capability, especially in terms of the PCC voltage compensation range.
From (2) and considering that the voltage v dq
cs

to be injectedthrough the series stage is

conveniently defined by
V dq
cs =

[ ] ]

1
cos ( )
3V l . rms
V dq
17
p
nt
sin ( )
cc

Where V l ,rms

is the load desired rms voltage and defining K pcc as the ratio of the PCC

voltage to the nominal load voltage as

v
|V p | 18
kp = p =
vl 3 v l .rms
dq

cc

cc

cc

( k pcc >1

for swell and k pcc <1

for sag), it is possible toobtain the required dc current from

the state variable model for an operating point I dc as

a2 +b 2
I dc=
19
Gs|mdq
s |
Using (19), one can conclude that higher the term

|mdqs |

is,the lower the required dc current is.

On the other hand, by neglecting the losses (just to find the next expression), one shows that the
load power pl is defined by
Pl=P pcc + P serice + Pshant
Pl=i pcc k pcc V l p f pcc ++ Pupqc =ilvlpfl 22

Where p pcc is the power provided by the PCC defined by

Pupqc=P serice + Pshant 23

And pseries

and

pshunt are the power provided by the seriesstage and the shunt stage of

the UPQC, respectively. In steady state, p pcc is equal to pl and pupqc is equal to zero, then
the UPQC must either inject or absorb the power difference in the PCC under transients
conditions by means of the series stage, which either drains or injects this power into the dc side,
thus
pupqc = pseri es=v 1 ( i 1 p f 1i pcc k pcc p f pcc ) =( 1k pcc ) pl . ( 24 )
The power transferred from the dc side into the ac side during the period t 1 t 2 by the CSC
in the series stage can also be defined by
pupqc =

1 1
L dc [ i dc ( t 2) 2i dc ( t 1) 2 ]=( 1k pcc ) p l (25)
t 2t 1 2

From (25), one can conclude that compensating perturbations in the PCC voltage will
produce a change in the dc current. However, the higher the dc current or the higher is, the higher
the UPQC capacity is to compensate for voltage disturbances at the expense of higher losses in
the topology and higher size and cost of the equipment. On the other hand, (19) shows that there
is a minimum dc current required to compensate a disturbance defined by k pcc
bringing the series CSC into over modulation (

|mdqs | 3/ 2

or

|mdqs |1

without

). Then, it is

necessary to obtain this current for a given load and a desired range of voltage disturbances to
compensate. Finally, a dc current level for nominal operation higher than the minimum dc
current is considered and the dc reactor Ldc using (25) is finally chosen.

(c) Phasorial diagram for nominal conditions.

(d) Phasorial diagram for a sag condition.

(e) Phasorial diagram for a swell condition.

KEY DESIGN GUIDELINES

The CSCUPQC can be simplified as presented in Fig. 3(a) and (b) for the fundamental
component and any harmonic component, respectively, for designing purposes. Differently, the
dc inductor design considers a compensating range for voltage disturbances.
A. Design Guidelines for the Shunt Stage:
The resonant frequency of the LC filter is
r =2 f r =

1
. ( 26 )
C p Lp

For design purposes, one can further simplify the CSC in theseries stage as Fig. 3(c)
shows, considering it an open circuit and the load and the capacitor in the series stage like
impedance Z eqp [Fig. 3(e)] in series with the LC filter defined by
Z eqp =( n 2t X Cs + X tx ) Z l .(27)

These results are used to design the LC filter according, where C p

and L p

are

calculated to obtain a desirable frequency response, THD for the current in the shunt stage(
THD IP )and THD for the capacitor voltage ( THDV

cp

)neglecting Z eqp and then its effect in

the current harmonics must be evaluated considering Z eqp

B. Design Guidelines for the Series Stage:

From Fig. 3(b), it is possible to further simplify the UPQC asFig. 3(d) shows in order to
obtain an equivalent impedance

Z eqs in parallel with

Cs

through the coupling transformer

[Fig. 3(f)]defined by
Z eqs =( X Cp + X Lp ) Z l +X tx .(28)
In order to ensure a desired THD in the capacitor voltage Z eqs is considered in the calculations

of the value of

. The THD of the injected voltage is defined by

Cs

THDV =
cs

1
V Cs,1

h=2

V Cs ,h )2 ( 29 )

Where V cs, 1 corresponds to the fundamental component of the voltage in

corresponds to the h harmonic of the voltage in C s
I rs , maxnt ( I p+ I l ) =

( I p + I l ) Z eqs

nt
V Cs,1 =X Cs

Cs

and

V cs, h

and are defined by

,( 30)

V Cs, h=I rs, h X Cs /h=I dc f ac ,h X Cs /h .

(31)

Where f ac, h is the gain of the PWM technique for the h harmonicand I rs , max is the maximum
PWM current injected by the CSC in the series stage and is defined by
I rs , max=G s M s I dc , max ( 32 )
And

Ms

corresponds to the CSC modulation index in the seriesstage. Considering (30) and

(32), one can obtain

I dc, max=

I p +I l Z eqs
+n . ( 33 )
Gs M s n t X Cs t

Then, considering (29)(31) and (33)

THDV =
Cs

1
Gs M s

h=1

f ac, h
h

( )(

X Cs 2
n +1 . ( 34 )
Z eqs t

Fac is introduced for a particular PWM technique as

1
Fac =
Gs M s

h=2

f ac , h 2
(35 )
h

And Fig. 4(a) shows Fac

for the SPWM technique as a functionof the modulating index M s

and various normalized carrier frequencies f sw . Hence, using (34), X C

X Cs =

becomes

THD V
Z
1
=
1 eqs
. ( 36 )
s C s
F ac
n2t

cs

C. DC Reactor Design Guidelines:

The dc reactor should accumulate enough energy to compensatesags/swells in the PCC
voltage and limit the THD of the dc current THD Idc defined by

THD I =
dc

1
I dc ,0

h=1

I dc , h )2 ( 37 )

Where I dc, h is the harmonic in the dc current and

I dc ,0 is thecontinuous component of the dc

current. Because the voltageharmonics on the dc side of the topology are defined by the
summationof the dc voltages in each CSC, the h voltage harmonic

V dc ,h in the dc side of the

topology becomes
V dc ,h=V dcs ,hV dcp ,h=f sdc ,h V CSf pdc , h V cp, ( 38 )
Therefore, each dc current harmonic I dc , h is given by
I dc, h=

V dc, h
f
V f
V
= sdc , h cs pdc ,h cp (39 )
h s Ldc
h X Ldc

Where f sdc , h and f pdc ,h correspond to the dc voltage harmonicgain of the PWM technique for
the h harmonic of the series and shunt CSC, respectively. The highest dc harmonic voltage gain
is achieved when the modulation index is the highest and this condition occursaccording to
(19)for the CSC in the series stage. Therefore, it is possible to simplify the dc link voltage
harmonics computation considering just the series stage modulation index and using (30) as
V dc ,h 2 f sdc , h V cs =2 f sdc ,h Z eqs (I l + I p)/n t .

(40)

Hence, considering (37), (39), and (40) one has

THD Idc =2

( I l+ I p ) Z eqs
nt X Ldc I dc

h=1

f sdc , h 2
. ( 41 )
h

In the series stage, the capacitor voltage v cs

and the PWMCurrent I rs

of the CSC are

defined by
I rs nt ( I l+ I p ) =( I l + I p ) Z equs / nt ,
V cs =X Cs

(42)

I rs =G s M s I dc / 2 ,

(43)

respectively, combining (41)(43), one has

[ ]
X Cs Z eqs

F
THD I =2 dc
X Ldc
dc

Where Fdc

n2t

X Cs

(44)

Z eqs
2

nt

corresponds to the contribution of distortion of themodulating technique and it is

defined as
Fdc =

Gs M s
2

h=1

Finally, solving for

f sdc , h 2
. ( 45 )
h

XL

in (44), one gets

dc

[ ]
X Cs Z eqs

F dc
X Ldc =2 f s Ldc=2
THD Idc

Fig. 4(b) shows Fdc

Ms

n 2t

X Cs

Z eqs

( 46)

n 2t

for the SPWMtechnique as a function ofthe modulation index

for different values of the normalized carrier frequency f sw

. Thus, (46) gives the dc

inductor size as a function of a desired THD of the dc current.

The ridethrough capability criterion is also considered in the design procedure to ensure
the ability to compensate for voltagedisturbances (25). Defining the initial current i dc (t 1)

as a

proportionof the current after the disturbance i dc (t 2) hence

i dc ( t 1) =k i idc ( t 2 ) ( 47 )
dc

and (25) can be written as

Ldc =

2 pln cycles ( k pcc 1 )

f s ( 1k 2idc ) I 2dc
Where I dc

ncycles

( 48 )

can be obtained for an extreme case of sag/swell tobe compensated and

corresponds to the number of network cycles. Clearly, (48) shows that by increasing the

dc current, the required Ldc

higher

size decreases; however, the losses will increase because of the

I dc . The design of Ldc

should consider a minimum current required to compensate

the disturbance i dc (t 2) , which can be obtained from (19) and an acceptable variation of the dc
current during the disturbance k idc

. Finally,the inductor Ldc

should be chosen considering

(46) and (48), selecting the value that meets both conditions.

Fig. 3. Simplified circuit of CSC-UPQC. (a) Equivalent circuit for fundamental frequency. (b)
Equivalent circuit for harmonics . (c) Simplified circuit for the shunt stage analysis. (d)
Simplified circuit for the series stage analysis. (e) Simplified circuit with equivalent impedance
for the shunt stage. (f) Simplified circuit with equivalent impedance for the series stage.

Fig. 4. Fac and Fdc

for different values of f sw (p.u). (a) 100 Fac . (b) 100 Fdc

CONTROL SCHEME:
A control scheme based upon an inner input/output linearizationtechnique is proposed
since the system is nonlinear (Fig. 5). This approach ensures the desired dynamic within the
operating region and enables designing outer controllers based on the systems parameters and the
modulating technique.

A.Series Stage Control:

The control objectives of the series stage are regulating therms value V l ,rms

and the

phase of the load voltage by manipulating thedq components of the series capacitor voltage
dq
V dq
cs . Considering (12)(15) and in order to have a linear relation for V cs , the input/output

linearization technique suggests defining an auxiliary input vector udq

as
s
Cs

d dq
dq
dq
dq
dq
V =Gs mdq
s i dc n t ( i 1 + i p ) C s W s v cs =us ( 49 )
dt cs
The previous expression allows defining the CSC inputs mdq
according to the auxiliary
s

inputs udq
s

and system state variables [Fig. 5(a)] as

dq
dq
dq
u dq
s nt ( i1 +i p ) C s W s V cs
m =
Gs idc
dq
s

(50)

Hence, a first-order relationship between the capacitor voltage V dq

and udq
cs
s

is obtained as

v dcs v qcs
1
= q=
. (51 )
d
us u s C s S
The resulting system is a pure integrator and it could be controlled by a P regulator, but small
variations in the parameters would generate a steady-state error since
exactly computed. Then, a PI regulator is proposed as
uds
v

dt
cs . ref

uqs
v

qt
cs .ref

=k p . vcs +

k i. vcs
( 52 )
s

Then
d

v cs
v

dt
cs . ref

v cs
v

qt
cs.ref

ki . v + k p. v s
cs

. ( 53 )

cs

Cs s +k p . v s+ k i .v
cs

cs

dq

ms

in (50) cannot be

Fig. 5(a) Control scheme for the series stage.

'
In order to compensate for the zero in (53), a first order filter between V dq
cs . ref

and

V cs. ref

dq

is defined [Fig. 5(a)], allowing a typical second order relationship between V dq

cs and

dq

. The parameters of the PI can be defined as a function of a desired natural frequency

V cs. ref
0. V

cs

and damping ratio V

cs

as

k i . v = 2o .v Cs , ( 54 )
cs

cs

k p . v =2 v
cs

cs

Cs
. ( 55 )
k i .v
cs

Finally, the reference for V dq

cs

can be obtained from (17). Forthe V dq

cs

loop, tuning is

recommended to use a natural frequency at least five times greater than the switching frequency
of the CSC. Otherwise, the delay should be considered in the model.

B. Shunt Stage Control:

Fig. 5(b) Control scheme for the shunt stage.

In order to control the PCC power factor (p f pcc ) and the dcCurrent ( i dc ), the control
strategy will be based on regulating i dq
by the shunt stage as a slave loop, and a master
p
controller is synthesized to control thep f pcc
present in the i dq
p

and i dc , Fig. 5(b). The inputs mdq

are not
p

dynamics (14), so the input/output linearization technique requires deriving

this expression until the inputs appear. Hence

d 2 dq 1 d dq d dq
d dq
i =
V 1 V cp W s i p ( 56 )
2 p
L
dt
dt
dt
dt
p

Using the state variable model (12)(15), one can write

T

d 2 dq
d
i = A p mdq
P ( 57 )
p +Bp x p Pp
2 p
dt p
dt

Where
T

X p =[ i dp i qp v dcp v qcp i dc ] , ( 58 )
T

P p=[ v dl v ql ] , (59 )
A p=

G p i dc
,(60)
C p Lp

[]
( 2r +2s ) 0

0( 2r +2s )
2 s /L p 0
00
B p= 02 /L (61)
s
p
2 s / L p 0
1/ L p 0
0 1/ L p

And s

is the angular frequency of the ac network and r

frequency of the LC filter (26).

is theresonance angular

The second derivative of i dq

p

is a nonlinear function of thestate variables, disturbances,

and system entries. Imposing a decoupled behavior for i dq

requires an auxiliary input udq
p
p

as

d 2 dq
d dq
dq
dq
i +k 1 i p + k 2 i p =k 2 u p ( 62 )
2 p
dt
dt
Whereit is possible to define di dq
p /dt

in matrix form as

d 2 dq ( )
dq d dq
i l =D p udq
i ( 63 )
p +Fp ip
2 p
dt p
dt

With
D p=k 2 ,( 64)

F p = k 2 0k 1 0 ( 65 )
0k 2 0k 1
Then, equating (57) and (63) and solving for mdq
p

[ ]

Xp
i dq
p
1
dq
m =
D u + F p d dq B p P p ( 66 )
Ap p p
i
d
P
dt p
dt p
dq
p

[ ]

The dynamic between udq

p

and i dq
p

is defined by (62); however, small variations in the

parameters will lead to small errorsin the computation of (66) and steady-state errors. This is
overcome by adding an integrative block [Fig. 5(b)] between udq
and the current reference
p
i dq
p ,ref

as

up
i

d
p . ref

up
i

q
p .ref

1
( 67 )
T i .ip S

Resulting in a third order relationship between i dq

p ,ref
i dp
i

d
p . ref

i qp
i

q
p .ref

k2
1
(68)
T i .ip S 3 +k 1 S 2+ k 2 S+ k 2 /T i . ip

and i dq
p

Then, using the ITAE criterion, one can obtain the constants k 1 , k 2 ,and T i , i
settling time t s .i

for a desired

of this loop [14].

C. DC Current Control:
A master loop over the i dp

control loop to regulate the dc currentis added Fig. 5(b).

Neglecting the loses of the CSC (just to obtain the next expression), it is possible to write a
power balance between the ac side and dc side of the topology as
v dcp i dp + v qcp i qp=L dc i dc

d
i +i ( i R + v ) (69)
dt dc dc dc dc dcs

Defining an auxiliary input uid c as

ui =Ldc
dc

d
i (70)
dt dc

Then, an appropriate reference i dp ,ref

for the i dp control loop using(69) and (70) becomes

i dp .ref =( ui i dc v qep i qp .ref + pdc ) /v dcp (71)

dc

Where
pdc =i dc ( i dc Rdc + v dcs ) +i dc 2 Rdc + i dc v dcs ( 72 )
Corresponds to the power taken by the topology, including thelosses in the CSCs and the dc
reactor in the term i 2dc Rdc
term i dc v dcs

, where v dcs

and the power either consumed or injected by the series stage in the
is the dc voltage of the CSC in the series stage that can be

calculated as
t

dq
v dcs =Gs m dq
s v cs ( 73 )

The auxiliary input defined in (70) requires the computationof (71) and small parameter
variations that will lead tosteady-state errors. Therefore, a PI regulator between the
auxiliaryinput uidc and a dc current reference i 'dc .ref
ui
i

dc

'
dc .ref

=k p . idc +

k i .i
( 74 )
S
dc

given by

is added leading to a second order relationship between i 'dc.ref and i dc as

i

dc
'
dc .ref

k i .i + k p .idc S
dc

L dc S + k p .idc S+k i .idc

( 75 )

A first order filter between i 'dc.ref and i dc .ref

is added to compensatethe zero [Fig. 5(b)].

Finally, the previous block allows a standard second order relationship between i dc .ref
i dc

and

. Thus, it is possible to define the PI parameters as a function of a desired natural

frequency 0. i

dc

and damping ratio i

dc

for this loop as

k i .i =2 i Ldc (76)
dc

dc

k p . i =2 i dc
dc

Ldc
( 77 )
k i .i
dc

Because the dc link current i dc

loop is the master loop, it isadvised to set its settling time at

least 5 times slower than t s .ip .

D. Power Factor Control:
This loop basically sets the reference for the inner loop for a given power factor reference
pf pcc. ref

. The PCC power factor can be defined as

p f pcc =cos ( tan1 ( q pcc / p pcc ) ) (78 )

Where q pcc

and p pcc are the reactive and active power, respectively,and are defined in thedq

rotating frame by
q pcc =( v dpcc +nt v dcs )( iql +i qp ) ( v qpcc + nt v qcs )( i dl +i dp ) ( 79 )
p pcc =( v dpcc + nt v dcs )( i dl +i dp ) + ( v qpcc +nt v qcs )( i ql +i qp ) ( 80 )
Defining conveniently an auxiliary input u pcc
v pcc =tan (cos1 ( p f pcc . ref ) )=

as

q pcc
( 81 )
p pcc

Therefore i qp can be used to control the pf pcc by defining theappropriate reference i qp ,ref
i

q
p .ref

u pcc ( v dl ( i dl +i dp ) + v ql i ql ) +v ql ( i dl + i dp ) i ql v dl
v dl + v ql u pcc

( 83)

as

Hence, the dynamic response of the power factor loop is given by the dynamic of the i qp loop.
The final block diagram is depicted in Fig. 5(b).
CASE OF EXAMPLE:
A load of 1.17 MVA with a 0.85 inductive power factor feed from a 3.3 kV, 50 Hz is used as a
theoretical example. The parameters are shown in Table I, and the control parameters and criteria
are shown in Table II. The SPWM technique is set to use a carrier frequency of 750 Hz (15 p.u.)
for the CSCs modulation and the LC resonance frequency is set at f r=
considering that z eqs z l

, an acceptable THDV

cs

3.5 p.u. Using (28),

= 0.1(10%) and (36), the series capacitor

becomes
TABLE I
CSC-UPQC PARAMETERS

TABLE II
CONTROLLERS PARAMETERS

Fig. 6. Minimum dc current versus k pcc

In order to obtain the Ldc
between i dc
pf pcc

and k p cc

for various PCC power factors pf pcc .

size using the ride through capabilitycriterion, the relationship

is depicted in Fig. 6 for

. The plot shows that while the pf pcc

k pcc

from 0.7 to 1.2 for different values of

is closer to the unity, the lower is the dc current

required by the CSC-UPQC. Considering a minimum dc current equal to 235 A for k pcc = 0.75
and pf pcc =1 , ncycles = 7 ms/20 ms, where the dc current must be compensated by the shunt
control loop and a nominal dc current equal to 270 A ( k idc = 1.15), then using (48)
Ldc =

2 pln cycles ( k pcc 1 )

f s ( 1k 2i ) i2dc

=194 mH ( 83 )

dc

On the other hand, imposing a THD Idc =0.2 (20%) for Ldc design purposes one has by using
(46)
2 F dc
Ldc =
2 f s TH D I

dc

X cs Z l
2

nt
=58 mH (84)
2
X csZ l /nt

Because the value of

Ldc obtained by the ridethrough capabilitycriterion meets the THD

criterion, the value obtained in (84) should be finally considered.

MATLAB CIRCUIT MODEL

Fig. matlab circuit model

Fig. fuzzy logic controller circuit madel

SIMULATION RESULTS
Two DSP TMS320C6713 systems are used to implement the control scheme algorithms
in order to control independently the shunt stage and the series stage using the parameters that
are shown in Table II calculated by using the proposed design procedure and guidelines. A lowpower prototype was assembled in order to test the theoretical approach. The equipment was
designed to compensate a 2 kVA inductive load (0.8 lagging power factor) (Table I). The
expressions shown in Fig. 5 were properly converted to discrete mathematics using standard
control theory. The tests were implemented using a load nominal voltage of 74 V and 5 A in the
dc link current.
Fig. 9 shows the CSC-UPQC operation under nominal conditions meaning no sag/swell (
k pcc =

1) but unitary displacement power factor in the PCC ( pf pcc = 1). The PCC current

is in phase with the PCC voltage showing unitary displacement power factor in the PCC.
Using a programmable three-phase voltage source, the system was tested under a sudden
17% swell ( k pcc =

1.17) and sudden 10% sag ( k pcc =

0.9) conditions, which are

presented in Figs. 8 and 10, respectively. In both cases, the CSC-UPQC is able to compensate for
the PCC voltage perturbation byholding the load voltage in the desirable value in less than oneac
cycle.

Fig. 7. Dynamic behavior for a step up (17% swell) of the PCC voltage. (The PCC voltage is
used to trigger the scope.)

Fig. 8. Steady-state waveforms for pf pcc = 1 and a permanent swell of 17% of the PCC
voltage.

Fig. 9.Experimental steady-state waveforms for pf pcc = 1 and k pcc =

1.

In both cases, there is a dc current variation because the energy is transiently either
injected (for a swell) or drawn (for a sag) from the dc link. The proper dynamic operation
confirms that the shunt stage control loop prevents the dc current value from decreasing beyond
the minimum value required for compensation and goes back to the desired value in less than
250 ms, without affecting the performance of the power factor correction and load voltage.
Finally, Figs. 9 and 11 show the operation of the CSC-UPQC in steady state under a
sustained swell (17%

87 V in the PCC, CH1) and sag (10%

67 Vin the PCC),

respectively. The plots show that the equipmentis able to keep the desirable condition for the
PCC (unitary displacement power factor) and load (constant rms voltage close to 74 V).

Fig. 10.Dynamic behavior for a step down (10% sag) of the PCC voltage. (The dc link current is
used to trigger the scope.)

Fig. 11. Steady-state waveforms for pf pcc = 1 and permanent sag of 10% of the PCC voltage.

CONCLUSION
A low power laboratory setup confirms the theoretical considerations as various static and
dynamic tests demonstrate the performance. The proposed UPQC-CSC design has superior
performance for mitigating the power quality problems. A CSC-based UPQC in combination
with an appropriate control strategy based on the input/output linearization is presented. This
allows the design of the controllers independent of the operating point and only dependent on the

topology capacitors and inductors size as well as the PWM technique. The resulting topology in
combination with the control scheme can provide currents and voltages as required by the
references independent of the operating point and for all of the desired compensation range as in
voltage-source-based topologies. A 1.17 MVA load fed from a 3.3 kV system is used to show the
proposed design procedure, and a laboratory prototype is implemented to show the system
compensating Harmonics, interruptions, sags and swells using low switching frequency in the
CSC and maintaining a unitary displacement power factor in the PCC with ANN technique.

REFERENCES
[1] M. H. H. Chen, Modeling and controlling of unified power quality conditioners, in Proc.
Conf. Rec., Hong Kong, China, pp. 413435.
[2] M. F. McGranaghan, D. R. Mueller, and M. J. Samotyi, Voltage sags in industrial system,
IEEE Trans. Ind. Appl., vol. 29, no. 2, pp. 397503, Mar./Apr. 1993.
[3] D. Graovac, V. Kati, A. Rufer, and J. Kne, Unified power quality conditioner based on
current source converter topology, presented at theConf. Rec. Elect. Power Eng., Graz, Austria,
Aug. 2001.
[4] H.Akagi, Trends in active filters line conditioner, IEEE Trans. Power Electron., vol. 9, no.
3, pp. 263268, May 1994.
[5] E. W. Gunther and H. Mehta, A survey of distribution system power quality-preliminary
results, IEEE Trans. Power Del., vol. 10, no. 1, pp. 322329, Jan. 1995.
[6] C. Seplveda, J. Espinoza, L. Moran, and R. Ortega, Analysis and design of a linear control
strategy for three-phase UPQCs, in Proc.Conf. Rec., Nov. 2004, vol. 3, pp. 30603065.
[7] L. Landaeta, C. Seplveda, J. Espinoza, and C. Baier, A mixed LQRI/PI based control for
three-phase UPQCs, in Proc. Conf. IECON, Nov. 2006, pp. 24942499.
[8] P. Melin, J. Espinoza, N. Zargari, M. Sanchez, and J. Guzman, Modeling issues in threephase current source rectifiers that use damping resistors, in Proc. Conf. Rec., Jan. 2007, vol. 2,
pp. 453458.

[9] P. Kenneth, Current-source converter for AC motor drives, IEEE Trans. Ind. Appl., vol. IA8, no. 6, pp. 679683, Nov. 1972.
[10] H. Akagi, New trends in active filters for power conditioning, IEEE Trans. Ind. Appl.,
vol. 32, no. 6, pp. 13121322, Nov./Dec. 1996.
[11] K. Vadirajacharya, P. Agarwal, and H. Gupta, A simple control strategy for unified power
quality conditioner using current source inverter, in Proc. Conf. Rec. IPEC, May 2008, pp.
12191223.
[12] H. Fujita and H. Akagi, The unified power quality conditioner: The integration of series
active filters and shunt active filter, IEEE Trans.Power. Electron., vol. 13, no. 2, pp. 315322,
Mar. 1998.