Reduced Comparator Low power Flash ADC using 35nm CMOS

Dharmendra Mani Varma

Department of Microelectronics,
Indian Institute of Information Technology,
Allahabad-India
imi2009016@iiita.ac.in
evenly-spaced reference voltages generated by a resistor
ladder. Comparators, including several amplification-andlatching stages, amplify the differences between the input
signal and those reference voltages. They deliver the
comparison results as an array of digital bits or a
codeword to the encoder. This codeword is called a
thermometer code, due to the thermometer-like
appearance of 1s and 0s in it (see Figure 1). The
encoder converts the thermometer code to a Gray or a
binary code. Flash ADCs have a simple architecture.
However, the circuitry required to achieve very high speeds
at reasonable power consumption, and also the provisions
required to overcome the comparator offsets, make their
implementation challenging.
The main concern is number of comprater that grows
exponentially and thus result in high power consumption.
This problem canbe solved by modifying artitecture to
reduce the no of comprater, that will result in less power
consumption

Abstract ADC is one of the basic elements in digital system,

as we need to interconnect the digital system to real world that
is analog, so these are a primary and important block of any
digital system. In this paper, a new design for a low power
CMOS flash ADC is proposed. A 4 bit flash ADC with
maximum acquisition speed of 2Gs/s, is implemented with 1.2V
supply voltage. Hspice simulation result for proposed
architecture verifying the analytical result is given. It shows
that the proposed ADC consumes about 24mW.The INL/DNL
is 0.34/0.4.This is due to reduction in number of comparators
as compared to normal flash ADC. By reduced no of
comparator.

I.

INTRODUCTION

ADC is very important interface device for digital system

to connect to the real world they found there use in nearly all
digital systems varying from data storage to processers.
High-speed analog-to-digital converters (ADCs) are the
key building blocks in many applications including highdata-rate serial links [1][3], ultra-wideband (UWB)
systems [4], the read channels of magnetic and optical
data storage devices[5],high-speed instrumentation [6][7],
wideband radar and optical communications [8].
A majority of these applications require 4 to 6 bits of
resolution at mutli-GHz conversion rates. For high-speed
low-to-medium resolution, ADCs the most appropriate
architecture is flash. This architecture is widely used in
ADCs with resolutions of 7 bits or less. In CMOS
technology, for 6-bit resolution, conversion rates of
1GHz and beyond have been previously reported. For 4bit resolution, multi-GHz rates are also achieved using timeinterleaved architectures. It is important that such ADCs
be implemented in a standard CMOS process for easy
integration with other digital signal processing circuits.
The main challenges in designing high-speed CMOS
flash ADCs are optimizing the speed and power, static
and dynamic offset reduction, calibration, and low supply
voltage operation [9]. One application of high-speed low-tomedium resolution ADCs is in serial links. Because of their
lower cost and lower power consumption, serial links
are attracting more and more attention in wire line data
transmission. PCI-Express [10] is an example of multi-gigabit per second serial links.
II.

+V Full Range

VA

3R/2

+V HI

GND
+V HI

GND
+V HI

GND
+V HI

GND
+V HI

GND
+V HI

R/2

I6
I5
I4
I3
I2
I1
I0

E
N
C
O
D
E
R

GND
+V HI
GND

GND

Figure 1.Flash ADC Architecture [15]

STANDARD FLASH ADC

A generic architecture for a flash ADC is shown in

Figure 1. The input signal of the ADC is compared against
___________________________________
978-1-4244 -8679-3/11/$26.00 2011 IEEE

385

B2
B1
B0

III.

PROPOSED ARCHITECTURE

The proposed architecture uses the single comparator to

compare different reference voltages.This result in reduction
of comparer from 15 to four and uses 3 multiplexers to
generate the required binary code as shown in figure 2.

Figure 2 Proposed 4-bit flash ADC

Digital
Output

M
Input

Reference

Figure 3.Schematic for comparator

multiplexer for the reference voltage switching based on

next significant bits.
The Primary component that shown in the Figure 3 is the
comparator that is divided into two parts as L (left) and R
(right). Left side is a two stage cascaded differential
amplifier. On right side there are two inverters first one
from left is designed to reduce VIH to reduce gain of
differential amplifier to detect the change of even 0.1mV in
input with respect to reference voltage, next inverter is to
provide full voltage swing to the output stage. All
MOSFETs have channel length of 35nm. Vdd and Vss are
respectively +1.2.V and -1.2V for differential amplifier
where as for inverter it is 1.2V and GND respectively.

In this all the bit values are decided sequentially as the delay
of analog multiplexer and the comparer are small enough to
perform all the comparison in one clock cycle so it qualifies
the one clock cycle conversion of flash ADC.
The basic algorithm that is used is we first check
whether the input is greater than *Vref or not, if it is we set
B3 as high or else low and for B2, if B3 is high and input is
more than *Vref than we set B2 as high or if B3 is low
and the input is greater than *Vref than also B2 is high
otherwise it is low. Similarly we can expend this algorithm
for other bit values.
The main parts of this ADC are analog multiplexer and
comparator. In this paper we used a simple analog

386

The delay of the transmission gate is low which is

suitable for the proposed architecture. A schematic of the
analog multiplexer is shown in figure 4. This has a digital
control Input1 and input2 among which one is connected to
output at a time depending on the value of the digital control
logic as in figure3 it connect the input 1 to output for logic
high and connect the input 2 to the output for a logic low.
Input1

Select

Figure 5.The simulation results of 8*1 MUX

Output

Input2
Figure 4. Schematic for analog multiplexer

IV.

SIMULATION RESULTS

The proposed ADC has been implemented on a 35nm

model that was made by Sakurai Lab using Alpha Power
Law and simulated in Tanner T-Spice simulator. The supply
voltage used is 1.2V and the reference voltage Vref=0.2V and
a sampling rate of 2GS/s is achieved. The comparison of the
proposed ADC with related work is shown in Table I.
TABLE I.

Resources
Technology
Sampling
Rate
(GS/S)
Resolution
Input
range
INL
DNL
Power

COMPARISION OF DIFFERENT DESIGN

This
Work
35nm
2

[11]

[12]

[13]

[14]

90nm
2.5

180nm
2

180nm
1.356

180nm
4

4biu
0.2

4bit
-

4bit
0.6

4bit
0.4

4bit
-

0.34

0.03

0.48

0.26

0.4

0.04

0.44

0.35

24mW

30.2mW

42mW

68mW

43mW

Figure 6.The simulation results of the proposed ADC For ramp input

Figure 5 shows the simulation results of the 8X1analog

multiplexer, figure 6 shows the result of full architecture for
a ramp signal of 0 to 0.2V, figure 7 shows the output for a
128MHz sine wave., figure 8 shows the DNL(Differential
Non Linearity) and figure 9 shows the INL(Integral Non
Linearity) for the proposed ADC

Figure 7.The simulation results of the proposed ADC For 128MHz sine
wave

387

REFERENCES
[1]

[2]

[3]

[4]

[5]

Figure 8. |DNL| (Differential Non Linearity)

[6]

[7]

[8]

[9]

[10]

[11]

Figure 9. |INL| (Integral Non Linearity)

V.

[12]

CONCLUSION
[13]

In this work, the design and simulation result of a 4-bit

CMOS flash ADC has been presented. That provides
maximum sampling frequency of 2GS/s and low INL of
0.34 and DNL of 0.4 and at analog supply of voltage 1.2V it
consumes 24mW of power only. This can be used as a
module for pipeline ADC to implement a low device count,
fast, and high resolution pipeline ADCs.

[14]

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