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10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
I.
INTRODUCTION
V
O
VT
(1)
Q1
V1
RS1
RS2
Q2
V2
Fig. 1
A conventional 1:1 RSCC. The resistors, RS1 and RS2,
represent loop series resistances, V1 and V2 represent the input and
output potentials.
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IC
Average I2
per cycle
VC
t
Excess charge
build-up
2
Fig. 2
Typical waveforms of the flying capacitor in the RSCC
described in Fig. 1.
II.
PRINCIPLE OF OPERATION
Q1 RS1
V1
I1
RS2
RS3
S1
Q3
Q2
V2
(a)
Q1 RS1
V1
RS3
Q3
RS2
L
S2
Q2
V2
I2
(b)
Q1 RS1
V1
RS3
Q3
RS2
L
S3
I3
Q2
V2
(c)
Fig. 3
The introduced RSCC configuration and operation
principle: (a) charge, (b) discharge, and (c) balance states.
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IC [A]
VC [V]
50
(V1 +V2 )
10
(V2 -V1 )
5
25
t [ sec]
0
0
-5
S1
S2
(V1 -V2 )
S3
IC
VC
-10
0
10
15
-25
-50
20
Fig. 4
Typical waveforms (obtained from simulation) of the flying
capacitor voltage and current. The circuit parameters are: V1=20V,
V2=31V, RS=0.15, L=5.2H, C=0.25F.
III.
t
VC t Vi Vi VC 0 cos
,
LC
IC t
Vi VC 0
L/C
t
sin
,
LC
(2a)
(2b)
VC ,1 V1 V1 VC ,3 2V1 VC ,3
VC ,2 V2 V2 VC ,1 2V2 VC ,1 ,
VC ,3 0 0 VC ,2 -VC ,2
(3)
VC ,2 V2 V1 .
V V V
C ,3 1 2
(4)
I pk ,S2 V1 / Z
I
pk ,S3 (V1 V2 ) / Z
, Z
L
.
C
(5)
g -1 V2
,
0 I2
g gn
2
.
3 Z
(6)
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V2 gRLV1 .
(7)
V2
gRL .
V1
(8)
fn
IV.
3 LC
(9)
A. Voltage Regulation
The basic operation mechanism that follows a charge,
discharge and balance states creates a rigid gyration
relationship as in (6). In the case that voltage regulation is
desired, g should be controlled. By introducing time delay
between cycles, that is, effectively changing the operating
frequency, g is made controllable and the gyration ratio g and
operating frequency can be re-defined as:
f s Gf n
3 LC
(10b)
0.9
0.8
Z/Rs=1000
Z/Rs=250
Z/Rs=100
Z/Rs=33
Z/Rs=10
0.7
0.6
2
1
6G
(11)
G RL
I2
6 Z
(12)
RS
2 Z
A A
-1
1 .
(13)
RL
I2
Z
1
I2
6G
3 2 RL2 G RL
Ploss I 22
RS .
2
2Z
4G 3Z
(10a)
G
I
rms,S1
I rms,S2
2
I rms,S3 3
2
2G
,
g Gg n
3 Z
Fig. 5
Theoretical efficiency curves as a function of the voltage
gain, A, with RS normalized by Z as a parameter.
RL
RL Re
1
1
RS
2Z
(14)
( A A-1 1)
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10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
(15)
Substituting (7), (8) and (10) into (15) yields the expression for
the normalized output ripple:
V2 1 C G
1 ,
V2 A CL 3
(16)
Converter Function
Step up/down2
Step up2
Step down2
Doubler step up/down
Doubler step down
Divider step up/down
Divider step down
1.
2.
Q1a
1
1
1
S
S
1
1
Q1b
D
D
D
3
D
S
S
Q2a
2
D
D
D
D
S
S
Q2b
2
S
2
S
S
2
2
Q3a
3
3
D
3
3
O
O
Q3b
O
O
O
O
O
3
D
Q4
S
S
S
1
1
2
2
Q1a
V1
Q1b
Q2b
L
Q3a
Q2a
V2
Q3b
Q4
Fig. 7
A gyrator converter in a generalized configuration, with
optimized efficiency at voltage gains of A = {2,1,0.5}. The dashed
lines represent alternative routes optimized for a 1:1 configuration.
I2
Q
1/fs-1/3fn
Fig. 6
The current on the output capacitor, CL for one cycle. The
confined area is symmetrical above and below zero, and represents
the charge processed by CL at each cycle.
V.
V1
Q2
TOPOLOGY DERIVATIVES
Q1
V2
Q3
Q4
Fig. 8
A gyrator converter realized in full bridge configuration,
with optimized efficiency at voltage gain of A = -1.
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for this case would be: discharge (S2), balance (S3), charge
(S1), delay. It should be noted that, as analyzed above, the
order in which the sequence is applied does not affect the
characteristics of the converter.
td
t1
Q1
1
t2
Q2
VI.
t3
3
Q3
S1 Ts S2
(a)
Td Ts 3T , T LC .
TABLE II
ig. 9a
F
Fig. 9b
(17)
t2
T
2T
t3
T
2T
t4
T
1
3T
T
2
2T
3T
3
T
2T
4
3T
S3
td
t1
1
Q1
t2
Q2
t3
3
Q3
t4
Q4
S2 Ts S3
(b)
S1
Fig. 9
Timing diagrams for the switching sequences of the
GRSCC: (a) Basic configuration (Fig. 3), (b) Bridge realization (Fig.
8).
B. Inductor design
The inductor, although having a small inductance value,
has to sustain relatively high rms currents. However, in
contrary to the magnetics design in switched-inductor
converters, the per-cycle energy that is stored in the inductor is
zero. As a result, the main factor of the inductor sizing stems
from the core losses, rather than saturation limits. A
convenient way to estimate the volume of the magnetic
element is by the area product Ap, which can be expressed as:
Ap
LII rms
,
JK B
(18)
Ap
3 JKBf
(19)
max
0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
0.9
Buck
BCM
RS = 10m
RS = 25m
0.4
GRSCC
50
10
10
B [T]
0.2
0.2
0.2
0.05
0.2
L [H] at
100kHz
35
10
0.5
0.5
0.5
Rod
Air
10
BB
2
2
R 1 A ttr 1 A
1 1.3 s
RL A Ts 3 A
buck-boost at 250kHz
0.7
Full
core
40
buck-boost at 100kHz
0.8
GRSCC
(20)
where 1.3 is the rms to average current factor at BCM and ttr is
the on-off transition time of the switch.
Fig. 10 plots the efficiency of (20) compared with the
efficiency estimation of the GRSCC derived in (14) as a
function of the voltage gain A. The figure shows the results for
various loop resistances and operating frequencies. As can be
observed, the main advantage of GRSCC is the ZCS operation
that exhibits higher efficiency than the buck-boost at higher
operating frequencies. This allows further enhancement of the
power density of the GRSCC. For cases of higher conduction
losses and lower switching frequency, utilization of a buckboost converter, is still preferred.
1.6
2.8 A
2.2
VII.
EXPERIMENTAL VERIFICATION
Converter A
Value Model
Polypropyl
0.26 F
ene
5.3 H
ETD 34
2NMOS
uniIRFP3077
directional
Electrolytic
1 mF
Drivers
510 F
MIC4427Y
N
dsPIC30F2
020
MCU
RS
fn
dead time
Vin (max)
Vout (max)
Pout (max)
Converter B
Value Model
C4532C0G2A1
10 0.1 F
04J320KA
0.5 H
RM8/I-3F3
PMOS
IXTP96P085T
IXTP160N10T
NMOS
130 m
~100 kHz
~180 ns
55 V
70 V
200 W
C5750X7SR1H
106K
MIC4427YN
dsPIC33F16GS
502
48 m
~130kHz
100 ns
30 V
30 V
100 W
0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
IRFP3077
1N914
S2
S3
S2
S1
S3
Simulation
Theoretical
Experimental
0.7
0.6
0
Fig. 13
0.5
1.5
gn
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
Fig. 14
S2
S3
(a)
S1
0.8
Simulation
Theoretical
Experimental
0.5
1.5
IRFP3077
JE170
S1
0.9
33
3.3
Fig. 11
JE181
Switch
Out
4-Quad.
Switch
S1
S2
S3
(b)
Fig. 12 Experimental waveforms: (a) In a step-up operation mode,
(b) In a step down operation mode. Upper trace inductor current
(5A/Div.), Lower traces S(1,2,3) gate signals. Horizontal scale
2S/Div.
0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
10K
0.47
Q1
V1
510
Q2
12V
OB I B
Vs 0
OA IA
Experimental
Simulation
Theoretical
0.8
0.47
15V
0.9
Driver
3.3
100.1
0.85
10
15V
3.3
From
MCU
10K
0.75
0.5
0.75
1.25
= 21.5
/1
10
Fig. 18
15V
3.3
0.5
10K
0.47
Q3
Load
510
Q4
12V
Driver
OB I B
Vs 0
OA IA
0.9
3.3
0.89
Fig. 15
In/Out
Capacitors
0.87
Drivers
Resonant
Tank
Experimental
Simulation
Theoretical
0.88
Power
Supplies
0.25
0.5
0.75
= /1
Switches
0.9
MCU
0.89
0.88
Fig. 16
A = 1.5
A = 1.25
A=1
A = 0.75
0.87
0.86
0
0.25
0.5
0.75
= /
1
VIII.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
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0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2317758, IEEE Transactions on Power Electronics
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0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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