Fig. 3.4.15: Reference Design for DSSS Shift Registers Subsystem [6].

DSSS Synchronization Subsystem

The DSSS Synchronization Subsystem underwent the most modification of any
subsystem from the reference design throughout the construction phase. The reference design
for DSSS Synchronization Subsystem was built specially for a 2 MHz CLOCK frequency
application. The best example of this frequency dependence is seen in the final DSSS design
U12D in Fig. 2.3.7. For a closer theoretical look, the components of interest are labeled Rs, R1,
R2, and Cs in Fig. 3.4.16 and described below.

Rs and Cs provide harmonic difference of inputs to U12D. This harmonic difference is

exploited through U12D to produce twice the frequency of the input applied at pin 12. Rs and
Cs values are highly dependent on the frequency applied. In the final DSSS Synchronization
Subsystem design Rs was 3 kΩ and Cs was 33 nF for the 10 kHz CA applied. At this stage,
output of U12D is sent to U18A, B where R1 and R2 are selected as to provide a Schmitt Trigger
waveform shaping stage. For DSSS Synchronization Subsystem R1 was 56 kΩ and R2 was 100
kΩ At the output of U18B pin 4, a smooth sinusoidal approximation of pin 1 input is fed to pin 5
of U18C and output as TTL zero logic low or 5V logic high. In the end these two ICs form a
multiply-by-two stage for the input carrier CA producing (2 x CA) for use in DSSS
Synchronization Subsystem.

52
 The last modification from the reference design of DSSS Synchronization Subsystem
presented in Fig. 3.4.17 was the placement of R2 Reset at the SR latch formed via NAND gates
U16A and U16B in Fig. 3.2.7. R2 Reset is renamed Q’ Reset in Fig. 3.1.9 to be more relevant to
the block diagram, and its purpose is actually better described with this renaming. The purpose
of this reset switch is to reset the value of Q’ at U16A, B to logic high 5 V. When the switch is
activated 5 V is fed into feedback of U16A, B into pin 6, setting VAR_CLOCK to value (2 x
CA) in order to bring Local PN Generator up to synchronize with OCO feed from Shift Register.
When synchronization is achieved, SYNC’ goes low and the SR latch U16A outputs Q’ as logic
low, locking the VAR_CLOCK to speed CA. This lock will remain until Q’ Reset is pressed
again, useful in situations where the synchronization has been lost between OCO and LCO.

Fig. 3.4.16: Theoretical Multiply-by-two stage via ICs.

53
 Fig. 3.4.17: Reference Design of DSSS Synchronization Subsystem [6].

DSSS Demodulation Subsystem

The DSSS Demodulation Subsystem went through considerable modification from the
reference design. The AUDIO OSCILLATOR U12A and U12B circuit from the reference
design was removed completely; see Fig. 3.4.18 below for the reference design. In its place, Fig.
3.2.8 depicts several stages of LPF and inversion via U14C, D, E, F. The LPF stages are first a
2nd order passive LPF with R = 300 Ω and C = 0.47 uF, followed by another 1st order LPF of R =
51 Ω and C = 0.47 uF. The cutoff frequencies of each are 84 Hz and 204.25 Hz, respectively.
The inverter stages of U14 help to power the inputs to full 5 V high or 0 V low values. At the
output of the circuit in Fig. 3.2.8, an in-phase equivalent DA is recovered.

54
Fig. 3.4.18: DSSS Demodulation Subsystem.

55
1. Task List and Work Distribution
• Research of hardware - Matt Elder 50% and Ryan Ginter 50%
• Investigation of existing car alarm systems – Matt Elder
• DSSS Subsystem – Matt Elder
a. Building, testing, and analysis of circuit presented in “Experimenting With Direct-
Sequence Spread Spectrum” [13]
b. Design of full-duplex direct-sequence transmission subsystem
c. Building, testing, and analysis of one direction of full-duplex direct-sequence
transmission subsystem
• Sensor/transmissions triggering subsystems – Ryan Ginter
a. Sensor hardware research
b. Building and testing of prototype Sensor Subsystem
• Baseband Data Transmit and Receive Communications – Ryan Ginter
a. Investigation of parallel-to-serial and serial-to-parallel conversion methods.
b. Investigation of synchronization of the data being encoded at the transmitters with
that which it is decoded at the receivers
c. Building, testing, and analysis of serial data transmissions
d. Building, testing, and analysis of start bit/stop bit creation and detection schemes
e. Building, testing, and analysis of receiver sampling and hold methods for
capturing data
f. Integrating, testing, and analysis of the Baseband Data Communications
Subsystems
g. Integrating, testing, and analysis of the Sensors Subsystem and Transmissions
Triggering Subsystem with the Baseband Data Communications Subsystems
h. Designed printed circuit boards for Baseband Transmit Data Subsystem and
Baseband Received Data Subsystem. Note designs also have Hamming Subsystem
integrated within it.
• Error detection and correction methods – Ryan Ginter
a. Investigation and simulation of methods such as repetition codes, single parity bit,
Cyclic Redundancy Checking, and Hamming codes
b. Building, testing, and analysis of Hamming circuitry
c. Integrating and test of Hamming subsystems with Baseband Data
Communications Subsystems
• Wireless Communication
Matt Elder
a. Research of transmission unit hardware
b. Research of DSSS circuit hardware
c. Simulation of various wireless transmission schemes
Ryan Ginter
a. Hardware test and analysis of OOK transceiver option
b. Test and analysis of integration between Baseband Data Communications
Subsystems with OOK transceivers
• Security of transmissions by minimization of code reuse – Matt Elder
• Final integration test and analysis between Baseband Data Communications and DSSS
Subsystems– Matt Elder 50% and Ryan Ginter 50%
56
• Cost Analysis – Ryan Ginter
• Marketability – Matt Elder
• Manufacturability – Matt Elder

2. Design Project Details

The following sections describe the theoretical considerations that were taken into
account during the design of the subsystems that were implemented in the final prototype.
These sections also provide more detailed descriptions of the design procedure followed in
designing of the subsystem. Finally all simulated test results are displayed along with any
observed and measured results.

5.1 Sensors Subsystem

Team member who designed this subsystem: Ryan Ginter
Team member who wrote this subsection: Ryan Ginter

This is one of the smaller subsystems of the final design. It consists of the sensors to
indicate where on the car vandalism or theft was attempted. The prototype system has two
sensors one to sense if a window is broken the other for if the car handle is pulled in an attempt
to get in. While the prototype only has two sensors simulated, it still sends four data bits of
information. The third and fourth bits are simply duplicates of the first and second data bits of
the two sensor system. The reason why in the Figure 3.2.1 the outputs are used twice is because
the Hamming (7, 4) error correction method requires four data bits. The reasons behind this will
be discussed further in the Hamming subsystem section. In the final product there will be four
sensors hooked up and every Q output will correspond to only one data bit. This section will
effectively show the capabilities of the sensor subsystem and what makes it important to the
overall system.

5.1.1 Theoretical Considerations

The ideal sensor chosen for this subsystem is the SQ-SEN-200. This sensor is omni-
directional meaning that it can be mounted in any orientation. The SQ-SEN-200 acts as a closed
switch when it is at rest in its mounted position. Then when tilted or vibrated in any direction it
chatters open and closed.
The sensor’s characteristic of chattering open and closed means to detect that the sensor
was tripped a transition from closed to open must be captured. To do this an SR latch is used.
The SR latch has two inputs S and R, S for set and R for reset. When R is low and S goes high
the output Q will also go high. Q will remain high even if S goes back to a low state. The only
way to bring Q back to a low logic state is to have R go high.
Using this information the sensor subsystem circuit of Fig. 3.2.1 can be developed. In this
circuit notice first the way the sensor is connected to S of the SR latch circuit. Since when the
sensor is at rest it acts as a closed switch the S input will be short to ground when the sensor is at
rest. When the sensor chatters the respective S will toggle between a high and low logic state.

57
This causes the respective Q output to go high and remain high until a reset command is received
from the user. When the Q output is high the data bit it corresponds to will be a logic one
indicating an alert at the respective sensor.

5.1.2 Design Procedure

While the SQ-SEN-200 is the ideal sensor for this system it was not ordered because it is
a surface mount component, and the exact price of it was not determined till later in the design
process. Instead for prototyping purposes, toggle switches have been used to simulate the effect
of each sensor. To test subsystem prototype the following procedure was followed:

Procedure for Sensor Subsystem Test

1. Build the circuit in Fig. 3.2.1 was but with a toggle switch in place for
each sensor.
2. Connect a LED to each of the first two Q outputs to make it easier to read
if the output is logic one or zero.
3. Repeatedly and rapidly open and close the toggle switches to simulate
chattering of the sensor.
4. Observe the LEDs and how they do or do not change.
5. Toggle the reset signal and record its effect.

No matter what the final state of the switches the LEDs at the output remained on, until
the R input was raised high. This test thus passed successfully in proving that, given a sensor like
SQ-SEN-200, the data to indicate the alerts at specific sensors can be generated. Further it was
proven that the SR latch can be used to ensure that even if the sensor goes back to rest the alert
will still be sent.
There are no simulations or observed results necessary for this subsystem considering the
test was mainly one that checked if the SR-latch was functioning properly. The reason this
system is of importance though is because it controls when data is sent, what data is sent, and
thus what parity bits are sent. If this system does not work properly then none of the other
systems can work properly either. Note that in the final prototype the SR-latches were removed
to allow for quicker test that do not involve manually resetting the latch after each test. In the
final system the latches would be put back in because there would be the ability to reset the
latches from the user.

58
 5.2 Baseband Transmit Data Communications Subsystem
Team member who designed this subsystem: Ryan Ginter
Team member who wrote this subsection: Ryan Ginter

This subsystem involves receiving the data from the sensors and the parity bits from the
Hamming Parity Bit Generator Subsystem, framing them together and sending them serially.
Along with this task is the need for the Transmission Triggering Subsystem that simply
compares the data and indicates there is a need to transmit if the data has been changed. While
these are all important components of the Baseband Transmit Data Subsystem the main
component that will be discussed in this section is the framing and parallel-to-serial conversion
of the data. As mentioned in the Section 3.4 this system went through several iterations before
the final hardware implementation became clearer with the internal UART IC design. The
Hamming Parity Generator component will be discussed within its own detailed subsystem
section. The Transmission Triggering Subsystem will be briefly mentioned because there is not
much left to say to describe it. As mentioned before it simply lets the transmitter know when it
needs to send, via simple logic comparisons. The following sections will describe how this
baseband system is to ideally work based on the model UART design. It will also be described
how the complete system was tested before any integration took place. Note that the following
descriptions are in direct reference to the block diagrams of Fig. 3.1.2 – 3.1.4 and the schematics
shown in Figs. 3.2.3 and 3.2.4.

5.2.1 Theoretical Considerations

The first major part of the Baseband Transmit Data Subsystem is the frequency divider
that is used to generate the transmit clock (TCK). To accomplish this frequency division a
74HC163, 4-bit binary counter, is used. The counter cycles through counting from 0000 to 1111.
It is noted that the most significant bit (MSB) is zero for eight clock cycles, counting from 0000-
0111. Then on the ninth clock cycle the MSB becomes a one for another eight clock cycles,
1000-1111. It is this MSB of the counter that creates the appropriate frequency division of the
local clock. This creates the TCK signal that is one sixteenth of the clock signal. This signal
determines the data rate by being used to control the clock of two parallel-to-serial shift registers,
74HC166. Not only is this TCK signal used to clock the data out of parallel-to-serial shift
registers, but it also is used to clock another counter that is used to count the data bits as they get
sent.
This second counter only starts counting when the need to transmit (NTX) signal triggers
a D-flip-flop’s clock input. This is the signal generated from the Transmission Triggering
Subsystem. When this occurs as long as no data is currently being sent the bit counter has the
binary number 0111 loaded into it. It then begins to count from 0111-1111. This requires exactly
nine TCK cycles. These nine TCK cycles account for the four data bits, three party bits, start bit,
and stop bit being transmitted. After it reaches 1111 the RCO output of the bit counter goes high
and is fed back to ensure that the counter is turned off.

59
 Other than triggering the D-flip-flop to start the transmission, the NTX signal also
triggers the clock on the hold register allowing the current set of data to be passed from the hold
register to the input of the parallel-to-serial shift register. This does not however load the
parallel-to-serial shift register. That task is accomplished by the transmission load signal TLD.
This is the same signal that triggers the loading of the bit counter. The reason why it is used
instead of directly by NTX is to prevent the corruption of data when there is data currently being
transmitted out of the parallel-to-serial shift register. Now when new data is available to transmit
during a current transmission NTX will indicate that there is new data to be sent. TLD, however,
will wait until the current data is sent, then will load the next set of data to be sent.
The reason for there being two parallel-to-serial shift registers is simply because there is
more data to be sent then what is possible for one shift register to accomplish. The bottom most
register, of Fig. 3.2.4 is used for the start bit, data bits, and parity bits. The register above it has
all its inputs set high, and has its serial output connected to the serial input of the bottom register.
The reason why all these inputs are high is to create a stop bit, in the same way as mentioned in
Section 3.4 that was initially thought of when the first UART idea was abandon. In the same
manner the start bit is created by having the first bit to be shifted out of the lower shift register
held low.
One other contribution from the UART schematic that was found, along with the design
was a timing diagram for how the signals propagate through the system as shown below.

Fig. 5.2.1: Timing diagram of Baseband Transmit Data Subsystem.

Note that T1-T4 would represent the four data bits and T5-T7 would be the parity bits.

60
 5.2.2 Design Procedure
As mention in Section 3.4 even after the internal design of the UART was discovered
there were still several modifications to be made. To avoid being redundant refer back to these
modification in Section 3.4. Note that the theory described above takes into account these
modifications.

The first thing that was tested was the frequency counter by itself, to ensure that the TCK
signal would be generated properly. To do this the following procedure was carried out:

Procedure for frequency divider test

1. Connect a toggle switch to the CLK input of the 74HC163 4-bit binary counter.
2. Enable the counter by connecting the ENP, ENT, and LD inputs to power.
3. Make sure when initially powered on the output QA – QD are zeros.
4. Toggle the switch to simulate a clock pulse and observe the output at QD.
5. Verify that this output does in fact create a signal that has a frequency of one sixteenth of
the clock.

The results of this test are tabulated in Table 5.2.1 of the following section. From this
table it can be seen that the clock cycle is in fact at a frequency of one sixteenth of the clock,
because clock cycles are needed for each half cycle of the output. In other words the output is
zero for eight pulses of the clock and one for eight additional pulses of the clock.

The next test for this system was done to verify that the Data Load / Send Control creates
the appropriate TLD and TX Busy signals after receiving multiple NTX signal. Note that the
Data Load / Send Control again makes use of the 74HC163 binary counter. However the enable
and load inputs are of much more importance than they were with the counter that was used for
frequency divider.

Procedure for Data Load / Send Control test

1. Again use the toggle switch as the input to the CLK input of the 74HC163. However,
note that now this simulated CLK signal is actually simulating the TCK signal.
2. Make sure the counter is set up in accordance to Fig. 3.2.4, along with the NAND gates
and D-flip-flops within the Data Load / Send Control. Also check that the counter is
outputting 1111 at QA – QD.
3. Check that after a clock cycle this output of the bit counter is unchanged.
4. Manually toggle the NTX signal to indicate that data is ready to be sent.
5. Record the TX Busy signal at pin 5 of the D-flip-flop.
6. Record the TLD output at pin 9 of the counter, and the ENP input at pin 7 of the counter.
7. Toggle the switch simulating the clock and again record TX Busy, TLD, and ENP.
8. Repeat step 7 for 5 clock cycles.
9. Toggle NTX again indicating there is more data to be sent.
10. Repeat step 6.
61
 11. Repeat step 7 except for just 4 clock cycles instead of 5.
12. Complete 9 more clock cycles and ensure that the counter and signals TX Busy, TLD,
and ENP are back in their idle state.
13. Compare with timing diagrams from theory in Fig 5.2.1.

These test results are tabulated in Table 5.2.2. They do follow what the timing diagrams
demonstrated in theory. Note that at TCK cycle 6 the first set of data is still being counted out so
the TX Busy signal is raised. Then immediately following the last bit being counted out at TCK
cycle, 1111, the counter restarts counting and the TX Busy signal is lowered. However after it
finishes counting out the data this time it is not reset because there was no request to send more
data. It is also notable that the TLD input goes low before each set of data is started to be
counted. It is at this time the parallel-to-serial shift registers should be loaded with the data from
the hold register. Note also that the ENP output is high during transmissions but low when the
transmissions are complete. This will be of greater concern when discussing the Wireless
Transceiver Subsystem.
With these two initial test completed successfully the total system in the schematic of
Fig. 3.2.4 was built and tested. The final test followed the same procedure in the previously
mentioned control test. The only difference now being that data was input to the hold register
and the serial output was monitored. These results are tabulated in Table 5.2.3 of the Observed
and Measured Results. Note that the first set of data input to the hold register was D0 = [1 0 1 0 1
0 1], then in the middle of when D0 was being serialized D1 = [1 1 1 0 1 1 0] was input to the hold
register. This test was another success and finalized the capability of the Baseband Transmit
Data Subsystem.

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 5.2.3 Observed and Measured Results
Table 5.2.1: Frequency divider test results.

Simulated CLK QD Output Trial QD Output Trial

Pulse #1 #2
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 1 1
10 1 1
11 1 1
12 1 1
13 1 1
14 1 1
15 1 1
16 1 1

Table 5.2.2: Data Load / Send Control results.

Simulated NTX QDQCQBQA TX Busy TLD ENP

TCK Pulse
1 1 1111 0 1 0
2 1 0  1 1111 1 0 0
3 1 0111 0 1 1
4 1 1000 0 1 1
5 1 1001 0 1 1
6 1 0  1 1010 1 1 1
7 1 1011 1 1 1
8 1 1100 1 1 1
9 1 1101 1 1 1
10 1 1110 1 1 1
11 1 1111 1 0 0
12 1 0111 0 1 1
13 1 1000 0 1 1
14 1 1001 0 1 1
15 1 1010 0 1 1
16 1 1011 0 1 1
17 1 1100 0 1 1
63
Simulated NTX QDQCQBQA TX Busy TLD ENP
TCK Pulse
18 1 1101 0 1 1
19 1 1110 0 1 1
20 1 1111 0 1 1
21 1 1111 0 1 0
22 1 1111 0 1 0
23 1 1111 0 1 0
24 1 1111 0 1 0

Table 5.2.3: Final test of Baseband Transmit Data Subsystem using D0 = [1 0 1 0 1 0 1]

and D1 = [1 1 1 0 1 1 0].

Simulated NTX QDQCQBQA TX Busy TLD TX

TCK Pulse
- 1 1111 0 1 0
1 1 1111 0 1 0
- 1 0  1 1111 0 0 0
2 1 0111 0 1 0 (start bit)
3 1 1000 0 1 1 D1
5 1 1001 0 1 0 D2
- 1 0  1 1001 1 1 0 D2
6 1 1010 1 1 1 D3
7 1 1011 1 1 0 D4
8 1 1100 1 1 1 P1
9 1 1101 1 1 0 P2
10 1 1110 1 0 1 P3
11 1 1111 0 1 1 (stop bit)
12 1 0111 0 1 0 (start bit)
13 1 1000 0 1 1 D1
14 1 1001 0 1 1 D2
15 1 1010 0 1 0 D3
16 1 1011 0 1 1 D4
17 1 1100 0 1 1 P1
18 1 1101 0 1 1 P2
19 1 1110 0 1 1 P3
20 1 1111 0 1 1 (stop bit)
21 1 1111 0 1 1
22 1 1111 0 1 1
23 1 1111 0 1 1
24 1 1111 0 1 1

64
 5.3 Baseband Receive Data Communications Subsystem
Team member who designed this subsystem: Ryan Ginter
Team member who wrote this subsection: Ryan Ginter

This subsystem carries out the task of receiving the serial data that has been sent, and
interpreting the data so that it can be used to trigger alerts. The designed subsystem accomplishes
the issue of synchronization that was of great concern during the initial designs. At the same time
the issue of converting the serially received data to a parallel form is also accomplished. This
subsystem can further be broken up into three parts the digital filter that samples the data, the
start bit detector, and the sampling and serial-to-parallel converter. As mentioned in Section 3.4
the sampling and serial-to-parallel conversion is done similar to how it was described in the
initial design review. However, as the inter-workings of the UART led to new hardware for the
serial-to-parallel system. The most significant find was the 74HC164 serial-to-parallel shift
register, which is used in start bit detection, digital filtering, and receiving the overall data. The
following sections will describe each part in more detail along with the tests that were completed
to finalize the subsystem.

5.3.1 Theoretical Considerations

First in this subsystem it is necessary to filter the data because if there is any interfering
noise it must be ignored. To accomplish this task the circuit in Fig. 3.2.9 was built. First note that
the CLK signal is the same as the local clock that was used in transmitting the data. That is, the
CLK signal is at a frequency 16 times the data rate. With this in mind the data being received is
connected to the controls of a 74HC151 8:1 multiplexer. The output of this multiplexer is
connected to a D-flip-flop, the output of which is fed back to every input of the multiplexer,
except input D0 and D7. The input D0 is connected to ground and the input D7 is connected to
power.
Now with this set up if a zero is received then after three CLK cycles the multiplexer’s
output will be that of D0, which is logic 0. This zero will be held at the output of the D-flip-flop.
Then because of the feedback from the flip-flop the output of the D-flip-flop will not change
until the control inputs of the multiplexer are 111 or 000. What this means is that in order for the
data to be received as a 1 or a 0 it must be held constant for three clock signals. Since the data
rate is at a frequency one sixteenth of the CLK, any interfering signal shorter then three CLK
cycles will be ignored. The output of the D-flip-flop is the data that will be sampled in the end,
and will from now on be referred to as RX1 or the filtered data.
This digital filter also helps in the detection of the start bit. Since each transmission ends in
logic 1, to act as a stop bit, after a set of data is received RX1 will be held high. This output is
then brought to another D-flip-flop, such that the previous value of RX1 is always at the output
of this second flip-flop, this output will be referred to as RX2. These outputs along with the
complementary value of the current RX1 are inputs to a NAND gate. The moment when a zero,
the start bit, is received the NAND gate will toggle low then high, starting the rest of the receiver
process. This signal is referred to as RX START, and is essentially doing what NTX did for
starting the transmitter. While this does accomplish the start bit detection it also disables the
second D-flip-flop so that it does not continue searching for a start bit. After all the data is

65
received the signal RX DONE is sent to the flip-flop to enable it again. The theoretical timing
diagrams of the start bit detector are shown below.

Fig. 5.3.1: Timing diagrams of start bit detector.

After the start bit is detected the sampling and serial-to-parallel conversion processes are
triggered by the RX START signal. Each bit received from the filtered data is then sampled as it
is received. Then after all the data is received it is output in a parallel form. This data will
eventually be sent to the Hamming error detection system. The system can be seen in the Fig.
3.2.10.
Similar to the parallel-to-serial converter there are two counters one for generating the clock
frequency division, and the other for keeping track of how many bits have been received.
Together they form the Data Sample and Release Control. The cycle counter acts as a frequency
divider, which creates the receiver clock (RCK) signal. The RCK runs at the same rate as the
TCK signal. RCK takes care of sampling the data at RX1 by shifting the data into the 74HC164
shift register. The second counter is used to count the number of bits that have been received.
After it finishes counting the RCO output will go high and be used to indicate that everything has
been received. This is essentially the RX DONE signal that turns the start bit detector back on
when everything has been received. RX DONE is also used to stop the counters from trying to
receive more data. It is also used to trigger the hold register to release the data; however it is first
connected to a D-flip-flop to create a delay. This prevents the data from being release too soon,
which could lead to bit errors. The full theoretical timing diagram is illustrated below.

Fig. 5.3.2: Timing diagram for sampling and serial-to-parallel conversion controls.
66
 Note that R1-R4 would represent the four data bit and R5-R7 would be the parity bits

5.3.2 Design Procedure

The start bit and digital filter combined system was able to be tested for its filtering and
detection abilities by controlling the input to the shift register and monitoring the outputs of RX1
and RX START. Testing the ability of preventing the start bit detection however was not able to
be tested initially because the signal RX DONE is determined by the serial-to-parallel conversion
system, which was not connected initially.
To test this system it was first integrated with the digital filter, and start bit detector. A test
similar two the Data Load/Send Control test was then designed and attempted to be carried out.
The procedure for this initial test is laid out below.

Procedure for initial Sampling and Serial-to-Parallel Conversion Subsystem test

1. Build circuit in Fig. 3.2.10.
2. Uses the same CLK toggle switch signal for both the working baseband transmit
subsystem and the baseband receiver subsystem that is to be tested.
3. Be sure that the transmitter is sending a stop bit, only sending ones.
4. Enter data into the hold register of the transmitter. Continuously transmit data serially
form the baseband transmitter.
5. Directly connect this transmitter’s output to serial input of the receiver.
6. Start clocking the data with the toggle switch.
7. Observe the outputs and functionality of the digital filter along with the start bit detector,
which should receive a start bit after three clock cycles. At which point the RX Start
signal should be toggled.
8. Ensure the start bit detector is then disabled by observing RX Done going low.
9. Continue clocking the data and recording the values of TCK, RX Start, RX Done, RX,
RX1, and the RCK. Do this until all data bits are received appropriately and the timing
diagrams from theory are verified.

The data that was starting to be captured is shown in Table 5.3.1 of the Observed and
Measure Results section. Note that during this process the clock being simulated with the toggle
switch was the local clock. This means that there was 16 clock cycles for every bit generated.
This means 144 cycles, 16 times 9, were needed before all of one set of data was to be received.
This was just not a practical test. After getting half way through the number of clock cycles
completed would be lost track of, leading to questioning of errors that arose. Simply put there
was too much of a possibility for human error in this test.
To fix this a similar test was designed that essentially was an overall integration test between
both baseband transmitter and receiver. Now instead of toggling the clock manually a low
frequency 1 Hz functionally generated signal was used as the clock. Then LEDs were place at
the signals of interest, TX Busy, RX Start, etc. This removed all human components of the test
while still allowing the tester to view the signals of interest at a slow enough rate that would
allow time for proper recording of results. In the end this worked perfectly and everything that
was sent was received. It was even tested at bit rates of 2 kbps without any troubles. Later rather
than hard wiring the data that was to be sent, the Hamming parity generator was integrated into

67
the transmission side to create data and parity bits solely base on the toggle switches, acting in
place of the sensors.
Furthermore after the baseband transmit and receive subsystems were working soundly, they
were integrated with the Hamming Parity Generator and Hamming Error Detection and
Correction Subsystems respectively. The integration however was done on printed circuit boards
(PCBs). One board containing the complete Baseband Transmit Data Subsystem shown in the
block diagram of Fig. 3.1.2, and the other Board for the completed Baseband Receive Data
Subsystem displayed in Fig. 3.1.11. This was done to save on protoboard space, and to make the
overall subsystem look nicer. The final manufactured PCBs are shown in the figures below.

Fig. 5.3.3: Baseband Transmit Data Subsystem PCB.

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 Fig. 5.3.4: Baseband Received Data Subsystem PCB.

5.3.3 Observed and Measured Results

Table 5.3.1: Initial baseband receiver test that while seemed like a good thorough design turned
out to be filled with human errors.

CLK TCK RX Start RX Done TX = RX RX1 RCK

- 0 1 1 1 0 1
1 0 1 1 1 0 1
2 0 1 1 1 0 1
3 0 1 1 1 0 1
4 0 1 1 1 0 1
5 0 1 1 1 0 1
6 0 1 1 1 0 1
7 0 1 1 1 0 1
8 0 1 1 1 0 1
9 0 1 1 1 0 1
10 1 1 1 1 0 1
11 1 1 1 1 0 1
12 1 1 1 1 1 1
13 1 1 1 1 1 1
14 1 1 1 1 1 1
15 1 1 1 1 1 1
16 1 1 1 1 1 1
17 1 1 1 1 1 1
18 1 1 1 1 1 1
19 0 1 1 1 1 1
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 CLK TCK RX Start RX Done TX = RX RX1 RCK
20 0 1 1 1 1 1
21 0 1 1 1 1 1
22 0 1 1 1 1 1
23 0 1 1 1 1 1
24 0 1 1 1 1 1
25 0 1 1 1 1 1
26 0 1 1 1 1 1
27 1 1 1 1 1 1
28 1 1 1 0 1 1
29 1 1 1 0 1 1
30 1 1 1 0 1 1
31 1 1 1 0 1 1
32 1 0 0 0 0 0
33 1 1 0 0 0 0
34 0 1 0 0 0 0
35 0 1 0 0 0 0
36 0 1 0 0 0 0
37 0 1 0 0 0 0
38 0 1 0 0 0 0
Note that this is only a small portion of the table that was initially completed. This table is meant
to highlight the complexity of analyzing the data in this initial test. This complexity led to the
design of more automated test that could be checked visually by observing LEDs.

5.4 Direct Sequence Spread Spectrum (DSSS) Subsystem

Team member who designed this subsystem: Matt Elder
Team member who wrote this subsection: Matt Elder

The original circuit construction presented in by Kasteloot [6] was designed for a CA of 2
MHz from a XTAL oscillator source of 4 MHz. However, the final DSSS design was to
accompany the Wireless Transceiver Subsystem that has a maximum transmit bit-rate of 10
kbps. In order to compensate for this the CA of the system had to be scaled down to CA = 10
kHz in hopes of correctly interfacing with the complete system.

5.4.1 Theoretical Considerations

The Direct-Sequence Spread Spectrum (DSSS) Subsystem depends entirely on the
generation of a pseudo-random binary sequence (PRBS) that is produced at both the DSSS
Transmission Subsystem and the DSSS Shift Registers subsystem via shift registers. A shift
register is composed of a series of linearly fed flip-flops triggered by a mutual clock. It functions
by shifting the binary state of the first flip-flop through each successive flip-flop linearly. When
the last flip-flop in the register is fed back to the first flip-flop after a simple logic operation, a
pseudo-noise generator with a set periodicity will be formed. Given a shift-register with m flip-
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flops and a logic feedback loop as shown in Fig. 5.4.1, the PN sequence output has periodicity
with at most 2m clock cycles.

Fig. 5.4.1: Pseudo-noise (PN) generator with m stages.

When the feedback logic circuit consists of entirely modulo-2 adders, or XOR
Gate logic components, it is truly linear in operation. Also, zero state of the shift
register must be avoided as once the shift-register possesses zeros in all registers it
cannot feedback and change from this zero state in future clock cycles. Thus, the
maximal length period of a PN generator is (2m-1). As m increases the PN sequence
begins to look more noise-like in randomness, which aids in security of transmissions
and also interference avoidance in DSSS and CDMA systems. [17]

Other logic components used in the DSSS Transmission Subsystem are D Flip-
flops, decade counters, and XOR gates. The logic of a D Flip-flop is provided in Table
5.4.1 from the datasheet of a 74HC74 IC. A high-speed CMOS D Flip-flop unit
74HC74 is used early on in this circuit as a divide-by-two stage for the input clock
signal 20 kHz to produce CA = 10 kHz. Also, a D Flip-flop is used to input the
manually keyed input precisely in step with the clock for gate timing purposes. A more
complex divider circuit is used through CD 4017 decade counter units U3, U4, and U5.
The decade counters are cascaded in series to accomplish a Divide-by-1000 circuit for a
test data square wave of 10 Hz. XOR gates take inputs and output logic high when the
inputs are different in logic level, and output a logic low otherwise.

Table 5.4.1: Logic table from datasheet of 74HC74 IC unit.

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 5.4.2 Design Procedure
With carrier signal CA set to 10 kHz, a master clock signal of 20 kHz must be sent
through U1A divide-by-two stage. The system design does not change considerably in the DSSS
TX Subsystem. 20 kHz was well below the maximum clock frequency of all the ICs in this
subsystem, so there were no apparent conflicts as long as a solid 0V to 5V sine or square wave
was input. In the DSSS TX Subsystem presented in Fig. 3.2.5, the only IC different from the
original design was the switch of U1A from a CD4013BC to a high-speed CMOS 74HC74. This
change was just for convention, a general inclination to shift the parts list toward high-speed
CMOS ICs per availability.

In order to test the operation of this subsystem, a procedure for the test is outlined
below:

Procedure for initial DSSS TX Subsystem test

1. Build circuit in Fig. 3.2.5.
2. Using input function of 20 kHz sine wave with amplitude 5 Vpk-pk, make sure that offset is
set so that Vlow is 0 V and Vhigh is 5 V via oscilloscope.
3. Input function signal from step 2 to the input of U1A divide-by-two circuit.
4. Acknowledge that 10 kHz square wave is output at U2A.
5. Acknowledge that 10 Hz square wave is output at U2B.
6. Acknowledge that PN generator U6 is outputting a PRBS with chipping rate 10 kHz.
7. Start with manual key input test data for now: ensure KEY is switched to logic low and
TEST_DATA SELECT is forwarding KEY data to DATA SELECT. Finally, ensure
DATA SELECT is switched to define DA = KEY data.
8. Acknowledge that OCO x DA spread data is output from U7C, visually compare this
spread output with the original OCO; the two signals should be identical. Now switch
KEY to logic high value (Vhigh) and acknowledge that OCO x DA is an inverted version
of OCO.

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