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1CY 621 28
CY62128
PRELIMINARY
Functional Description
The CY62128 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Pin Configurations
Top View
SOJ / SOIC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O4
A11
A9
A8
A13
I/O5
CE1
CE2
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
62128-1
OE
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A0
A1
A2
A3
62128-2
San Jose
CA 95134
408-943-2600
July 1996 - Revised November 1996
CY62128
PRELIMINARY
Selection Guide
CY6212855
CY6212870
55
70
Commercial
115 mA
110 mA
70 mA
60 mA
LL
70 mA
60 mA
10 mA
10 mA
100 A
100 A
LL
20 A
20 A
Commercial
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Operating Range
Range
Commercial
Ambient
Temperature[2]
VCC
0C to +70C
5V 10%
Description
Test Conditions
Min.
Max.
VOH
VOL
VIH
2.2
VCC +
0.3
VIL
0.3
IIX
GND VI VCC
IOZ
IOS
ICC
VCC Operating
Supply Current
ISB1
ISB2
2.4
Coml
Automatic CE
Power-Down Current
CMOS Inputs
Max. VCC,
CE1 VCC 0.3V,
or CE2 0.3V,
VIN VCC 0.3V,
or VIN 0.3V, f=0
Coml
Unit
V
0.4
2.2
VCC +
0.3
0.8
0.3
0.8
+1
+1
+5
+5
300
300
mA
115
110
mA
70
60
mA
LL
70
60
mA
25
25
mA
10
10
mA
Coml
Max.
2.4
0.4
Automatic CE
Power-Down Current
TTL Inputs
L
LL
mA
10
10
mA
100
100
LL
20
20
6212870
Min.
CY62128
PRELIMINARY
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
pF
pF
TA = 25C, f = 1 MHz,
VCC = 5.0V
R1 1800
5V
5V
OUTPUT
3.0V
90%
OUTPUT
R2
990
100 pF
R2
990
5 pF
INCLUDING
JIG AND
SCOPE
(b)
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
GND
10%
5ns
5 ns
62128-3
62128-4
Equivalent to:
THVENIN EQUIVALENT
639
1.77V
OUTPUT
Description
Min.
Max.
6212870
Min.
Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
OE LOW to Low Z
tHZOE
tLZCE
OE HIGH to High
55
5
20
Z[7, 8]
tPU
WRITE
ns
35
ns
ns
25
20
70
ns
ns
25
0
55
ns
ns
0
20
tHZCE
tPD
0
Z[8]
ns
70
55
Z[7, 8]
70
55
ns
ns
70
ns
CYCLE[9]
tWC
55
70
ns
tSCE
45
60
ns
tAW
45
60
ns
tHA
ns
tSA
ns
tPWE
WE Pulse Width
45
50
ns
tSD
45
55
ns
CY62128
PRELIMINARY
Switching Characteristics[3,6] Over the Operating Range (continued)
6212855
Parameter
tHD
Description
Min.
tHZWE
Max.
Z[8]
tLZWE
6212870
Min.
Max.
Unit
ns
ns
20
25
ns
Switching Waveforms
Read Cycle No.1[10,11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
DATA VALID
62128-5
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
62128-6
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
CY62128
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
62128-7
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
62128-8
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
CY62128
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13,14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 15
DATAI/O
tHD
DATA VALID
tLZWE
tHZWE
62128-9
Truth Table
CE1
CE2
OE
WE
I/O0 I/O7
Mode
Power
High Z
Power-Down
Standby (I SB)
High Z
Power-Down
Data Out
Read
Standby (I SB)
Active (ICC)
Data In
Write
Active (ICC)
High Z
Active (ICC)
Ordering Information
Speed
(ns)
55
70
Ordering Code
Package
Name
Package Type
CY6212855VC
V33
CY6212855SC
S34
CY6212855ZC
Z32
CY6212870VC
V33
CY6212870SC
S34
CY6212870ZC
Z32
CY62128L70SC
S34
CY62128L70ZC
Z32
CY62128LL70SC
S34
CY62128LL70ZC
Z32
Document #: 3800524
Operating
Range
Commercial
Commercial
PRELIMINARY
Package Diagrams
32-Lead (450 Mil) Molded SOIC S34
CY62128
PRELIMINARY
CY62128
Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.