UART Protocol

Giao tip v truyn nhn d liu l mt nhu cu khng th thiu trong h thng
nhng.
Tuy nhin c im ca cc UART l gi nhn d liu theo tng byte. Trong khi d
liu truyn nhn thng cha nhiu thng tin hn. Do vy gii php c a ra l
ng gi d liu thnh cc gi tin (thng m mng k t) v truyn i.
Gi tin do ngi pht trin t nh ngha, chng hn khi gi nhn d liu t cm
bin accerometer ln my tnh qua UART, mnh thng dng mt gi tin nh sau:
X[data trc x]Y[data trc y]Z[data trc z]
Trong X,Y,Z l cc k t dng nhn bit, data cc trc c chuyn thnh
dng char. Tt c c lu thnh mt mng.
Do UART truyn nhn lin tc nn nhn ra gi tin cn thm cc k t nh
du. Cc k t ny c gi l Flag byte. Flag byte l mt byte mang gi tr c
bit s dng bo hiu frame bt u hoc kt thc.
K thut s dng Flag byte v stuffing byte
Flag byte l mt byte mang gi tr c bit s dng bo hiu frame bt u hoc
kt thc.
Gi s cn gi mt bn tin di ty , ta thm vo u v cui bn tin y cc Flag
bytes. (Vic ny thc hin thit b truyn gi l m ha d liu, sau khi bn tin
c truyn i th phn nhn s thc hin gii m v ly cc thng tin cn thit).

Vn t ra khi thc hin l trong data c cha cc byte gi tr trng vi START

FLAG v END FLAG.
Mt gii php n gin thng c s dng gii quyt vn nu trn l s
dng stuffing byte.
Mi khi xut hin mt Flag gia bn tin, chng ta s chn mt bit c bit gi l
ESC c gi tr quy nh trc vo pha trc Flag. Khi nhn bn tin th thit b gii
m s bit l frame truyn cha kt thc.
Trng hp gi tr ESC cng xut hin trong bn tin th ta cng lm tng t bng
cch thm ESC trc chnh gi tr .
Minh ha phng php nh sau:

Gii php ny c chnh sa mt cht thnh chun Point-to-point Protocol (PPP)

c s dng trong ADSL.
PPC s dng cc tham s sau:
Start byte: 0x7E.
ESC: 0x7D
Mi khi gp ESC th n c chn ESC pha trc cn bn thn n th thc hin XOR
vi 0x20 (kt qu l 0x5E). thit b nhn s XOR vi 0x20 mt ln na c kt
qu ban u.
Lu : C mt cch khc chn cc gi tr Start byte, stop byte v ESC. Cc gi tr
c chn thng c bit v kh b nhm ln, v d nh 0x55, 0xAA. L do chn
cc k t ny v biu din dng nh phn ca chng c dng 01 xen k nhau do
kh b li hn. Hin ti mnh ang s dng cch ny.
V d thc hin
nh ngha cc tham s trong protocol:
Start flag
: 0x12
End flag
: 0x13
Escape (DLE)
: 0x7D
Trc khi gi, sender s x l bn tin theo nhng trng hp c ghi trn.

Qu trnh nhn v x l d liu c th c m t bng hnh sau: (C th m t r

hn bng State machine).

Mt s im cn lu

Cc byte trc khi nhn c Start byte s b b qua.

Start byte, stop byte, ESC s b b i khi x l bn tin.
Khi nhn c stop byte, receiver nhn c bn tin v sn sng truyn
ln tng cao hn. Sau quay li ch bn tin mi.
Nn ci t thm c ch check li bn tin. Nu bn tin li => yu cn
sender gi li.

Ci t hm nhn gi tin trn VK

 Demo, mnh chn VK MSP430G2553. Chng trnh c nhim v nhn gi tin

theo frame quy nh trn.
Mi khi nhn c mt byte t UART, chng trnh ngt s gi mt hm callback
x l x. Da vo phn tch trn ta c th thy s dng state machine ci t
l hp l.
Cc trng thi bao gm WAITE_START_BYTE, IN_MESG, STOP;
Khi WAITE_START_BYTE, hm s i cho n khi nhn c byte Start flag v
chuyn qua trng thi IN_MESG.
trng thi IN_MESG, hm s lu cc d liu nhn c vo buff cho n khi tha
mn iu kin chuyn sang trng thi stop.
Cc trng hp c bit trong trng thi IN_MESG nh sau:
Khi truyn li dn n trng hp khng nhn c stop flag. Khi s hy b d
liu frame truyn v tin hnh nhn li d liu.
Khi gp ESC, hm s tip tc thu thp d liu ng sau n.
iu kin chuyn trng thi l nhn c stop flag v k t nhn c trc
khng phi ESC. C th s dng mt bin tm lastRxData lu gi tr nhn c
cui cng nhn c nhm pht hin trng hp ny.
Ci t c th nh sau:
https://gist.githubusercontent.com/ksvbka/397516ef7cc278f37036/raw/bed8778d44
d026efc2a7a563af5b843399ab5392/initRxDataPackage.c
Ci t th vin m ha v gii m gi tin:
thun tin cho qu trnh x l gi tin th yu cu phi c cc hm ph c m ha
v gii m gi tin. Mnh thc hin th vin m ha v gii m gi tin nh sau:
1. nh ngha cc gi tr macro v struct biu din gi tin.
https://gist.githubusercontent.com/ksvbka/31f23e5c8b1e3744df5d/raw/b31fb62e96
4013a04111b39899d80e5ab6425c2c/dataPackageStruct.c
2. Ci t cc hm check gi tin hp l, hm m ha gi tin v hm gii m gi tin.
Thut ton cho cc hm ny da vo l thuyt trnh by trn. Ci t nh sau:
https://gist.githubusercontent.com/ksvbka/a7f918738dc41b6f9fd7/raw/8eb94226da
6315918731b14021942327b1cd4e50/dataPackageFunction.c
Source code full cho th vin ny c th tham kho link:
https://gist.github.com/ksvbka/f054a586ed5ef04d5453

SPI Protocol
SPI vit tt ca Serial Peripheral Interface, SPI bus Giao din ngoi vi ni tip, bus
SPI. Chun SPI c pht trin bi Motorola. y l mt chun ng b ni tip
truyn d liu ch song cng ton phn (full- duplex) tc trong cng mt thi
im c th xy ra ng thi qu trnh truyn v nhn. i khi SPI cn c gi l
chun giao tip 4 dy (Four-wire).
SPI l giao din ng b, bt c qu trnh truyn no cng c ng b ha vi tn
hiu clock chung. Tn hiu ny sinh ra bi master.

Trong giao din SPI c bn tn hiu s:

MOSI hay SI cng ra ca bn Master ( Master Out Slave IN). y l chn

dnh cho vic truyn tn hiu t thit b ch ng n thit b b ng.
MISO hay SO Cng ra bn Slave (Master IN Slave Out). y l chn dnh
cho vic truyn d liu t Slave n Master.
SCLK hay SCK l tn hiu clock ng b (Serial Clock). Xung nhp ch c to
bi Master.
CS hay SS l tn hiu chn vi mch ( Chip Select hoc Slave Select). SS s
mc cao khi khng lm vic. Nu Master ko SS xung thp th s xy ra qu
trnh giao tip. Ch c mt ng SS trn mi slave nhng c th c nhiu
ng iu khin SS trn master, ty thuc vo thit k ca ngi dng.

Nguyn l hot ng
bt u hot ng th ko chn SS xung thp v kch hot clock c Maser v
Slave.

Mi chip Master hay Slave c mt thanh ghi d liu 8 bits.

C mi ca xung nhp do Master to ra trn ng gi nhp SCK, mt bit trong thanh
ghi d liu ca Master c truyn qua Slave trn ng MOSI, ng thi mt bit
trong thanh ghi d liu ca chip Slave cng c truyn qua Master trn ng
MISO.
Lu , c th config tn hiu ng b clock theo sn, theo mc .
Hin ti c 4 mode c bn (MODE 0. 1,2,3) ca SPI da vo config SCLK nh sau:

Cc ca xung gi nhp, phase v cc ch hot ng: cc ca xung gi nhp

(Clock Polarity) c gi tt l CPOL .y l khi nim dng ch trng thi ca chn
SCK trng thi ngh.
trng thi ngh (Idle), chn SCK c th c gi mc cao (CPOL=1) hoc thp
(CPOL=0).
Phase (CPHA) dng ch cch m d liu c ly mu (sample) theo xung gi
nhp.
D liu c th c ly mu cnh ln ca SCK (CPHA=0) hoc cnh xung
(CPHA=1).
S kt hp ca SPOL v CPHA lm nn 4 ch hot ng ca SPI. Nhn chung vic
chn 1 trong 4 ch ny khng nh hng n cht lng truyn thng m ch ct
sao cho c s tng thch gia Master v Slave.
Do 2 gi d liu trn 2 chip c gi qua li ng thi nn qu trnh truyn d liu
ny c gi l song cng.

I2C Protocol
IC, vit tt ca t ting Anh Inter-Integrated Circuit, l mt loi bus ni tip c
pht trin bi hng sn xut linh kin in t Philips. Ban u, loi bus ny ch c
dng trong cc linh kin in t ca Philips. Sau , do tnh u vit v n gin ca
n, IC c chun ha v c dng rng ri trong cc m un truyn thng ni
tip ca vi mch tch hp ngy nay.
Cu to v nguyn l hot ng
IC s dng hai ng truyn tn hiu:

Mt ng xung nhp ng h(SCL) ch do Master pht i ( thng thng

100kHz v 400kHz. Mc cao nht l 1Mhz v 3.4MHz).
Mt ng d liu(SDA) theo 2 hng.
S kt ni nh hnh di.

C mt lu nh v xung clock. Bn cht ca I2C l d liu trn ng SDA ch

c ghi nhn sn ln ca chn CLK. Do vy xung clock c th khng cn chnh
xc tc l 1MHz hay 3.4Mhz. Li dng im ny c th s dng 2 chn GPIO
lm chn giao tip I2C mm m khng nht thit cn mt chn CLK to xung vi tc
chnh xc (c th ch cn dng delay v bt tt mc logic, tham kho phn code
cui bi :D)
SCL v SDA lun c ko ln ngun bng mt in tr ko ln c gi tr xp x 4,7
KOhm (ty vo tng thit b v chun giao tip, c th dao ng trong khong
1KOhm n 4.7 Kohm. Ch rng theo cu hnh ny, mt thit b c th mc logic
LOW hay cao tr nhng ko th dng HIGH => Chnh tr pull up to ra mc logic
HIGH).

L do l cc chn ny c dng opendrain c th hot ng cc mc in p

logic khc nhau.
Vic la chn tr pull up ph hp s c trnh by phn sau.
Cc ch hot ng ca IC
Da vo tc ta chia lm 2 loi

Ch chun (standard mode) hot ng tc 100 Kbit/s.

Ch tc thp (low-speed mode) hot ng tc 10 Kbit/s.

Nu chia theo quan h ch t:

Mt ch mt t.
Mt ch nhiu t.
Nhiu ch nhiu t.

Qu trnh truyn d liu

Thit b A (ch) xc nh ng a ch ca thit b B (T), cng vi vic xc

nh a ch, thit b A s quyt nh c hay ghi vo thit b t.
Thit b A gi gi liu ti thit b B
Thit b A kt thc qu trnh truyn d liu.
Khi A mun nhn d liu t B, qu trnh din ra tng t, ch khc A s nhn
d liu t B.

Tn s xung nhp ng h c th xung 0 Hz.

Cch nh a ch

IC s dng 7 bit nh a ch, do trn mt bus c th nh a ch ti 112 nt,

16 a ch cn li c s dng vo mc ch ring. Bit cn li quy nh vic c hay
ghi d liu (1 l write, 0 l read)
V d:
a ch ca mt thit b l 0x20. Khi cn c vo thit b ny th thanh ghi s c
gi tr 0x40 (thm bit 0) cn khi ghi th gi tr l 0x41 (thm vo 0).
im mnh ca IC chnh l hiu sut v s n gin ca n: mt khi iu khin
trung tm c th iu khin c mt mng thit b m ch cn hai li ra iu khin.
Ngoi ra I2C cn c ch 10bit a ch:

nh dng d liu truyn

D liu c truyn trn bus I2C theo tng bit, bit d liu c truyn i ti mi
sn ln ca xung clock trn SCKL , Qu trnh thay i bit d liu xy ra khi SCL
mc thp.

Start = HIGH to LOW on SDA when SCL is HIGH

Stop = LOW TO HIGH on SDA when SCL is HIGH
Other when SCL low => Data!

Mi byte d liu c truyn c di l 8 bits. S lng byte c th truyn trong

mt ln l khng hn ch.

Mi byte c truyn s ch tn hiu phn hi l mt bit ACK bo hiu

nhn d liu. => Mi ln I2C s truyn 8bit v nhn 1bit.

Bit c trng s cao nht (MSB) s c truyn i u tin, cc bt s c truyn i

ln lt. Sau 8 xung clock trn dy SCL, 8 bit d liu c truyn i. Lc ny thit
b nhn, sau khi nhn 8 bt d liu s ko SDA xung mc thp to mt xung
ACK ng vi xung clock th 9 trn dy SDA bo hiu nhn 8 bit. Thit b
truyn
khi nhn c bit ACK s tip tc thc hin qu trnh truyn hoc kt thc.

Thut ton truyn nhn d liu:

B1: Host xc nh thit b cn giao tip v ch giao tip l read hay l write.
vic ny c thc hin bng cch gi 7bit a ch thit b v thm bit cui cng, 0
nu read v 1 nu write.
B2: Reset ch bng cch thc hin lin tip vic start v stop.

B3: Gi a ch thanh ghi cn truy nhp ca thit b cng nh ch read hay write.
B4: Gi hoc nhn 1byte d liu. Sau khi truyn 1byte d liu, bn nhn c d liu
s gi li 1bit ACK xc nhn nhn c d liu v tip tc truyn hoc bit
NACK bo nhn c d liu nhng kt thc qu trnh truyn.

Ch : ASK l bit do slave truyn ch ko phi do master truyn

Mt byte truyn i c km theo bit ACK l iu kin bt buc, nhm m bo cho

qu
trnh truyn nhn c din ra chnh xc. Khi khng nhn c ng a ch hay khi
mun kt thc qu trnh giao tip, thit b nhn s gi mt xung NotACK (SDA
mc
cao) bo cho thit b ch bit, thit b ch s to xung STOP kt thc hay lp
li mt xung START bt u qu trnh mi.
Chn tr Pullup I2C I2C Bus pullup resistor Calculation
Do I2C s dng u ra dng Opendrain/Open colector nn c th s dng vi nhiu
dng in p khc nhau. lm c iu ny ta cn s dng tr pullup ko ln
mc in p ph hp. Gi tr ca tr pullup tng i quan trng, nu chn khng
ph hp c th dn n vic mt mt tn hiu.

Gi tr tr pull up ph hp cn m bo 2 yu t:
Tha mn ph hp mc logic
m bo rise time ca tn hiu.
IC nhn ra ng mc logic th gi tr in p ti chn phi ln hn VOL. Ta c
cng thc tnh tr min nh sau:

Ngoi ra, do c th ca I2C c thm phn rise time. Nu gi tr tr qu ln s dn

n vic rise time cao.

Xem kt ni nh mt mch RC (C l t khng sinh) th ta c in p theo thi gian

tnh theo cng thc sau:

Thng thng, VIH v VIL thng tnh ln lt bng 0.7*VCC v 0.3*VCC nn ta c:

T ta c RMAX l

cc gi tr trn thng cho theo bng trong datasheet

V d v tnh tr pull up

Code mu cho I2C

Cc dng chip hin ti a s u c phn cng h tr sn I2C. Ty vo tng dng
Chip m cu hnh ph hp. Bn cht l bt tt cc bit tng ng trong thanh ghi cu
hnh I2C la chn xung, chn I2c hay to ra cc tn hiu Start, stop, Ack .
Ngoi cch trn ta c th s dng GPIO to giao tip I2C mm.
y mnh minh ha bng mt on code mu s dng PIC. Cc vi iu khin khc
ch cn chnh sa li phn define v cu hnh GPIO c th s dng c.
// B1: Define cc chn SCL v SDA thun tin vit code.
#define SCL
TRISB4
// I2C bus
#define SDA
TRISB1
// Cc chn ny iu khin
#define SCL_IN RB4 // Cc chn ny lu gi tr hin ti ca SCL v SDA.
#define SDA_IN RB1 //
// Khi to I2C bng cch ko cc chn SDA v SCL ln mc 1. y l trng thi mc
nh do s dng tr pullup ko ln in p VDD.
SDA = SCL = 1;
SCL_IN = SDA_IN = 0;
// S dng mt khong delay nh gia SDA v SCL m bo sequence. C th
ty chnh t yu cu tr.
void i2c_dly(void)
{
;
}
// C 4 hm c bn bao gm hm i2c_start(), i2c_stop(), i2c_rx() v i2x_tx(). Tt c
vic truyn nhn d liu u c th thc hin t cc hm trn.
// Hm start to ra tn hiu start bng cch ko chn SDA xung thp khi SCL ang
mc cao.
void i2c_start(void)
{
SDA = 1;
// i2c start bit sequence
i2c_dly();
SCL = 1;

i2c_dly();
SDA = 0;
i2c_dly();
SCL = 0;
i2c_dly();
}
// Hm stop to ra tn hiu stop bng cch ko SDA ln cao khi SCL ang mc cao.
void i2c_stop(void)
{
SDA = 0;
// i2c stop bit sequence
i2c_dly();
SCL = 1;
i2c_dly();
SDA = 1;
i2c_dly();
}
// Hm nhn d liu 1byte.
// Input l bit ACK,
// Output l mt byte c kiu unsigned char.
// ack = 1 => tip tc c
// ack = 0 => nack => kt thc vic c.
unsigned char i2c_rx(char ack)
{
char x, d=0;
SDA = 1;
for(x=0; x<8; x++) // Ln lt c tng bit.
{
d <<= 1;
do
{
SCL = 1;
}while(SCL_IN==0); // i xung sn ln ca SCL.
i2c_dly();
if(SDA_IN) d |= 1; // c SDA v chuyn bit ny vo d (1 th ghi 1, 0 gi nguyn)
SCL = 0;
}
if(ack) SDA = 0;
else SDA = 1;
SCL = 1;
i2c_dly();
// send (N)ACK bit
SCL = 0;
SDA = 1;
return d;
}
// Ham truyn d liu l mt bye c gi tr d
// Gi tr tr v l bit ACK.
bit i2c_tx(unsigned char d)
{
char x;

static bit b;
for(x=8; x; x--) {
if(d&0x80) SDA = 1; // Truyn t bit cao xung bit thp. 0x80 = 1000 0000
else SDA = 0;
SCL = 1;
d <<= 1;
SCL = 0;
}
SDA = 1;
SCL = 1;
i2c_dly();
b = SDA_IN;
// possible ACK bit
SCL = 0;
return b;
}
Phn tip theo l ng dng code I2C trn thc hin vic giao tip d liu vi
SRF08

i2c_start();
// send start sequence
i2c_tx(0xE0);
// SRF08 I2C address with R/W bit clear
i2c_tx(0x00);
// SRF08 command register address
i2c_tx(0x51);
// command to start ranging in cm
i2c_stop();
// send stop sequence
//Now after waiting 65mS for the ranging to complete (I've left that to you) the
following example shows how to read the light sensor value from register 1 and the
range result from registers 2 & 3.
i2c_start();
// send start sequence
i2c_tx(0xE0);
// SRF08 I2C address with R/W bit clear
i2c_tx(0x01);
// SRF08 light sensor register address
i2c_start();
// send a restart sequence
i2c_tx(0xE1);
// SRF08 I2C address with R/W bit set
lightsensor = i2c_rx(1); // get light sensor and send acknowledge. Internal register
address will increment automatically
// Ch , Khi c lin tip 2 ln th sensor s t ng chuyn sang thanh ghi k tip
// Trong v d ny, thanh ghi u tin ch vo lightsenssor, thanh ghi th 2 lu gi
// tr ca rangehing v thanh ghi k tip l ranglow.
rangehigh = i2c_rx(1); // get the high byte of the range and send acknowledge.
rangelow = i2c_rx(0);
// get low byte of the range - note we don't acknowledge
the last byte.
i2c_stop();

So snh SPI v I2C

Bus topology / Routing / Resouce

I2C ch cn 2 dy trong khi SPI cn t nht 3 4 dy (Trong trng hp dng SPI

mun thm Slave th s tng s lng dy). Vic to Bus I2C cng d dng hn
nhiu so vi SPI do ch cn 2bit l c th kt ni c s thit b ln (7bit).
Tc
V tc th SPI t ra vt tri so vi I2C. SPI l full-duplex, khng gii hn tc
ti a thng hn 10Mbps. Trong khi I2C gii hn tc thng thng 1Mbps nu
fasst mode v 3.4Mbps High speed mode.
Tnh nng
I2c c nhiu tnh nng cao cp hn nh automatic multi-master conflicts handling
and build-in address management. Tuy nhin chnh iu ny li lm gim tc .
SPI th rt d thc hin v cung cp rt nhiu tnh linh hot cho tin ch
m rng v cc bin th.