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TABLE OF CONTENTS
1.1
Pipeline ADC
1.2
SAR ADC
1.3
Delta-Sigma ADC
1.4
Flash ADC
12
CHAPTER-1 INTRODUCTION
13
16
REFERENCES ..
18
LIST OF FIGURES
Figure
Number
Figure-1
Description
Page No.
Figure-15
26
Figure-16
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Figure-2
Figure-3
Figure-4
Figure-5
Figure-6
Figure-7
Figure-8
Figure-9
Figure-10
Figure-11
Figure-12
Figure-13
Figure-14
7
8
9
10
12
13
15
16
17
19
21
24
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LIST OF TABLES
Table Number
Table-1
Description
Different Architecture of ADCs showing there
latency, speed and accuracy performance
Page No.
11
Table-2
Table-3
Table-4
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13
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CHAPTER-1
INTRODUCTION
In recent years, signal processing has gained ample significance making high
speed and low voltage analog to digital converters (ADC) inevitable in numerous
application.
Analog-to-Digital Converter (ADC)
An ADC converts real time analog signals into digital codes. An ADC has a
reference voltage or current against which the analog input is compared. The N-bit
digital output word indicates which fraction of the reference quantity Vref the
input quantity Vin is. The input-output transfer function is described by
Output-code,
---------- (1)
Where, N is the number of bits that can be resolved by the ADC, Vin or Iin
correspond to the input quantity.and Vref or Iref correspond to the reference value
against which the input will be compared. The resolution of an ADC is the number
of bits in the digital output code. Alternatively, it can be defined as the size of the
least significant bit (LSB). In a N-bit ADC, we will have 2 possible levels. If the
full scale range of the ADC is FSR, then
---------- (2)
There are basic four types of ADC and each has its own intended applications.
Although with present market needs more and more combinations of ADCs have
been coined up. A brief review of four types of ADC is given.
(A)SAR ADC
(B) Pipeline ADC
(C) Delta-Sigma ADC
(D)Flash ADC
The successive approximation ADC has been the mainstay of data acquisition
systems. Recent design improvements have extended the sampling frequency of
these ADCs into the megahertz region with 18 bit resolution. The basic successive
approximation ADC is shown in Figure 1. An N-bit conversion takes N steps.
Figure-2 Pipeline ADC with four 3-bit stages (each stage resolves two bits)
(D)Flash ADC
In this circuit analog voltage, Vo is applied simultaneously to a bank of comparators
with equally spaced threshold voltages (reference voltages VR1=V/8, VR2=2V/8,
etc.). This type of processing is called bin conversion, because the analog input is
sorted into a given voltage range or voltage bin determined by the threshold of
two adjacent comparators.
Conversion time is limited only by the speed of the comparator and of the priority
encoder. An obvious drawback of this technique is the complexity of the hardware.
The number of comparators needed is 2N -1, where N is the desired number of bits.
Hence the number of comparators approximately doubles for each added bit. Also,
larger the N, the more complex is the priority encoder.
Flash or Parallel Converters have the highest speed of any type of ADC. They use
one comparator per quantization level. Here, instead of using resistor for reference
voltage generation we have used diode connected PMOS transistors. MOS
transistors take considerably smaller area as compared to resistors in silicon, sizing
transistor is preferred compared to placing resistors. Also variation in length of
resistors creates more mis-match for reference voltage generation. The reference
voltage is divided into 2N values, each of which is fed into a comparator. The input
voltage is compared with each reference value and results in a thermometer code at
the output of the comparators.
A thermometer code exhibits all zeros for each reference level if the value of Vin is
less than the value on the reference, and ones if Vin is greater than or equal to the
voltage on the reference.
RESOLUTION VS BANDWIDTH FOR DIFFERENT TYPES OF ADC
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Latency
Low
Low
Low
Speed
High
Low-medium
Medium-high
Accuracy
Low
Medium-high
Medium
High
High
Low
Medium-high
High
Medium-high
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12
FUNCTIONAL DESCRIPTION
Pin Name
Description
VDD
Positive supply terminal, +1.8V
NON INVERTING Noninverting analog input of the differential input stage.
INPUT (VP)
The NONINVERTING INPUT must be driven in
conjunction with the INVERTING INPUT.
INVERTING
Inverting analog input of the differential input stage. The
INPUT (VM)
INVERTING INPUT must be driven in conjunction with
the NON INVERTING INPUT.
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OUT
PMOS
M12 10u/5u F=2
M214 10u/5u F=2
M215 10u/5u F=2
NMOS
M11 5u/1u F=1
M211 20u/500n F=2
M212 20u/500n F=2
M213 20u/500n F=2
M229 10u/5u F=2
M230 10u/5u F=2
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CHAPTER-3
FLASH/PARALLEL COMPARATOR ADC DESIGN
15
REFERENCE STAGE
COMPARATOR STAGE
NAND STAGE
PMOS
W/L=2u/1u F=2
Diode Connected
Stage
VBS=0
NMOS
Specified in Table1
M0,1 W/L=2u/500n
F=2
W/L=2u/500n F=2
Specified in Table1
M2,3 2u/500n F=2
THERMOMETER
W/L=1u/10u F=1
ENCODER STAGE
Table -4 W/L ratios of each block of 3 Bit Flash ADC
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CHAPTER-4
CHARACTERIZATION OF ADC
Using N bit analog-to-digital converter (ADC) does not necessarily mean that
system will have N bit accuracy. A system having an N bit ADC can have much
lower performance than expected. ADC specifications can lead to desired
performance of system. It also helps user to select right ADC for intended
application. Accuracy of the ADC is dependent on several key specs, which
include integral non linearity error (INL), offset and gain errors, and the accuracy
of the voltage reference, temperature effects, and AC performance. It is usually
wise to begin the ADC analysis by reviewing the DC performance, because ADCs
use a plethora of non-standardized test conditions for the AC performance, making
it easier to compare two ICs based on DC specifications. The DC performance will
in general be better than the AC performance.
DC Performance
1. Differential nonlinearity (DNL)
DNL reveals how far a code is from a neighboring code. The distance is
measured as a change in input-voltage magnitude and then converted to LSBs.
The key performance for an ADC is the claim no missing codes. This means
that, as the input voltage is swept over its range, all output code combinations will
appear at the converter output. A DNL error of < 1 LSB guarantees no missing
codes.
() =
() ( 1)
1
18
() ()
20
Figure-12 : DNL and INL Extracted from histogram DNL=0.2 LSB, INL=
0.04 LSB
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AC Performance
An ADC is defined by its bandwidth (the range of frequencies it can measure) and
its signal to noise ratio (how accurately it can measure a signal relative to the noise
it introduces). The actual bandwidth of an ADC is characterized primarily by its
sampling rate, and to a lesser extent by how it handles errors such as aliasing. The
dynamic range of an ADC is influenced by many factors, including the resolution
(the number of output levels it can quantize a signal to), linearity and accuracy
(how well the quantization levels match the true analog signal) and jitter (small
timing errors that introduce additional noise). The key specs to review are signalto-noise ratio (SNR), signal-to-noise and distortion ratio (SINAD), total harmonic
distortion (THD), and spurious-free dynamic range (SFDR). SINAD is defined as
the RMS value of an input sine wave to the RMS value of the noise of the
converter (from DC to the Nyquist frequency, including harmonic [total harmonic
distortion] content). Harmonic occurs at multiples of the input frequency. SNR is
similar to SINAD, except that it does not include the harmonic content. Thus, the
SNR should always be better than SINAD. Bot SNR and SINAD are typically
measured in dB.
SINAD = [6.02(N) +1.76] (dB)
------------------------------ (3)
------------------------------ (4)
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SNR is the signal-to-noise ratio with the distortion components removed. SNR
reveals where the noise floor of the converter is. One way to improve SNR is to
oversample, which provides a processing gain. Oversampling is a method of
lowering the noise floor of the converter by sampling at a rate much higher than
the signal of interest. This spreads the noise out over a wider range in the
frequency domain, thereby effectively reducing the noise at any one frequency bin.
A 2 oversampling reduces the noise floor by 3 dB. SNR can be computed using
,
= [
]
,
Spurious-Free Dynamic Range (SFDR) is defined as the ratio of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of
the next largest spurious component, excluding DC offset. It is typically expressed
in decibels relative to the carrier (dBc). SFDR is important in certain
communication applications that require maximizing the dynamic range of the
ADC. Spur prevent the ADC from converting small input signals, because the
distortion component can be much larger than the signal of interest. This limits the
dynamic range of the ADC. A large spur in the frequency domain in the frequency
domain may not significantly affect the SNR, but will significantly affect the
SFDR.
Total Harmonic Distortion (THD) measures the distortion content of a signal,
and is specified in decibels relative to the carrier (dBc). For ADCs, THD is the
ratio of the RMS sum of the selected harmonics of the input signal to the
fundamental itself. Only harmonics within the Nyquist limit are included in the
measurement.
22 + 32 + + 2
= 10log[
]
2
1
In many applications, the actual signal of interest occupies a smaller bandwidth,
BW, which is less than the Nyquist bandwidth. If digital filtering is used to filter
23
out noise components outside the bandwidth BW, then a correction factor (called
process gain) must be included in the equation for the resulting increase in SNR.
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25
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CHAPTERCONCLUSION
INL and DNL results shows that there is no missing code. We get SINAD= 9.0107
(including parasitic) and SINAD=16.162 (excluding parasitic). It results in
ENOB=1.21 and 2.39 respectively.Results shows that significant distortion is
present which reduces Effective Number of Bits. This is generally expected as
Flash ADC works in open loop conditions. Calibration can be done to reduce
distortion in the circuit.
FUTURE WORK
Calibration can be done to improve performance of ADC. If better results can be
obtained for three bit flash ADC, we can target for six bit flash ADC. ADC choice
depends on application and as per need. We can use pipeline ADC and flash ADC
can be employed for achieving higher resolution without compromising much on
speed.
27
REFERENCE
1. Baker, R. Jacob. CMOS: circuit design, layout, and simulation. Vol. 18.
John Wiley & Sons, 2011.
2. Gray, P. "EE247 lectures." University of California at Berkeley (1996).
3. Kester, Walt. "Mt-022: Adc architectures iii: Sigma-delta adc
basics." Analog Devices, Rev. 0: 02-06.
4. Razavi, Behzad, and Bruce A. Wooley. "Design techniques for high-speed,
high-resolution comparators." Solid-State Circuits, IEEE Journal of 27.12
(1992): 1916-1926.
5. Yukawa, Akira. "A cmos 8-bit high-speed a/d converter ic." Solid-State
Circuits, IEEE Journal of 20.3 (1985): 775-779.
6. Maloberti, Franco. "Layout of analog and mixed analog-digital
circuits." Design of analog-digital VLSI circuits for telecommunications and
signal processing. Prentice-Hall, Inc., 1994.
7. Kester, Walt. "MT-001: Taking the Mystery out of the Infamous Formula,"
SNR= 6.02 N+ 1.76 dB," and Why You Should Care." REV. 0 (2005): 1003.
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9. Uyttenhove, Koen, and Michiel SJ Steyaert. "A 1.8-V 6-bit 1.3-GHz flash
ADC in 0.25-m CMOS." Solid-State Circuits, IEEE Journal of 38.7
(2003): 1115-1122.
10. Kertis, Robert A., et al. "A 20 GS/s 5-bit SiGe BiCMOS dual-Nyquist flash
ADC with sampling capability up to 35 GS/s featuring offset corrected
exclusive-or comparators." Solid-State Circuits, IEEE Journal of 44.9
(2009): 2295-2311.
11. Kundert, Ken, et al. "Design of mixed-signal systems-on-achip." Computer-Aided Design of Integrated Circuits and Systems, IEEE
Transactions on 19.12 (2000): 1561-1571.
12. Jeon, HeungJun. "Low-power high-speed low-offset fully dynamic CMOS
latched comparator." (2010).
13. Jincheol Yoo, Kyusun Choi, Ali Tangel, A -GSPS CMOS Flash A/D
converter for System-on-Chip Applications, IEEE Computer society
workshop on VLSI, pp. 135-139, Apr. 2001.
14. A Abel and K Kurtz, Fast ADC, IEEE Trans. Nucl. Sci., vol. NS-22, pp.
446-451, Feb. 1975
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