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IntroductiontoPipelining
Latencyvs.throughput
Latency
Eachinstructiontakesacertaintimeto
complete.
Thisisthelatencyforthatoperation.
It'stheamountoftimebetweenwhenthe
instructionisissuedandwhenit
completes.

Throughput
Thenumberofinstructionsthatcompletein
aspanoftime.
Thisisnotnecessarilythesameasdividing
thetimespanbythelatencyifpipeliningis
used.
Pipelining
Definition
Pipeliningistheabilitytooverlapexecutionof
differentinstructionsatthesametime.
Itexploitsparallelismamonginstructions
andisNOTvisibletotheprogrammer.

Thisissimilartobuildingacaronanassembly
line.
Whileitmaytaketwohourstobuilda
singlecar,therearehundredsofcarin
progressatanytime.
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Thethroughputoftheassemblylineisthe#ofcars
completedperhour.
ThethroughputofaCPUpipelineisthe#of
instructionscompletedpersecond.

Pipelinestages
Eachstepinapipelineiscalledapipestage.
Inourassemblylineexample,astagecorresponds
toaworkstationontheassemblyline.
Pipelining
Cycletime
EverythinginaCPUmovesinlockstep,
synchronizedbytheclock("heartbeat"ofthe
CPU.)

Amachinecycle:timerequiredtocompletea
singlepipelinestage.
Amachinecycleisusuallyone,sometimes
two,clockcycleslong,butrarelymore.

Inmachineswithnopipelining:
Themachinecyclemustbelongenoughtocompleteasingle
instruction
Oreachinstructionmustbedividedintosmallerchunks(multiple
clockcyclesperinstruction).

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Pipelinecycletime
Allpipelinestagesmust,bydesign,takethesame
time.
Thus,themachinecycletimeisthatofthe
longestpipelinestage.

Ideally,allstagesshouldbeexactlythesame
length.
Pipelining
Pipelinespeedup
Theidealspeedupfromapipelineisequaltothe
numberofstagesinthepipeline.

However,thisonlyhappensifthepipelinestages
areallofequallength.
Splittinga40nsoperationinto5stages,
each8nslong,willresultina5xspeedup.
Splittingthesameoperationinto5stages,4
ofwhichare7.5nslongandoneofwhich
is10nslongwillresultinonlya4x
speedup.

Ifyourstartingpointisamultipleclockcycleper
instructionmachinethenpipeliningdecreases
CPI.
Ifyourstartingpointisasingleclockcycleper
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instructionmachinethenpipeliningdecreases
cycletime.
Wewillfocusonthefirststartingpointinour
analysis.
SimpleDLXoperation(withoutpipelining)
EachDLXinstructionhasfivephases.
Thus,eachinstructionrequiresfivecyclesto
execute(CPI=5)

Instructionfetch(IF)
Getthenextinstruction.
Instructiondecode&registerfetch(ID)
Decodetheinstructionandgettheregistersfrom
theregisterfile.
Execution/effectiveaddresscalculation(EX)
Performtheoperation.
Forloadandstores,calculatethememory
address(base+immed).
Forbranches,compareandcalculatethe
branchdestination.
Memoryaccess/branchcompletion(MEM)
Forloadandstores,performthememoryaccess.
Fortakenbranches,updatetheprogramcounter.
Writeback(WB)
Writetheresulttotheregisterfile.
Forstoresandbranches,donothing.
SimpleDLXoperation(withoutpipelining)
Datapathfortheunpipelinedversion:

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Redboxesaretemporarystoragelocations.
SimpleDLXoperation(withoutpipelining)
Thetemporarystoragelocationswereaddedtothedatapath
oftheunpipelinedmachinetomakeiteasytopipeline.

Notethatbranchandstoreinstructionstake4clockcycles.
Assumingbranchfrequencyof12%andastore
frequencyof5%,CPIis4.83.

Thisimplementationisnotoptimal.Improvementsinclude:
CompletingALUinstructionsduringtheMEMcycle(dropsCPI
to4.35assuming47%ALUoperationfrequency).

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OtherimprovementstoCPIarepossiblebutarelikelyto
increasetheclockcycletime.

Also,severalhardwareredundanciesexist:
ALUcanbeshared.
Dataandinstructionmemorycanbecombinedsinceaccess
occursondifferentclockcycles.
PipeliningDLX
Sincetherearefiveseparatestages,wecanhaveapipeline
inwhichoneinstructionisineachstage.

ThiswilldecreaseCPIto1,sinceoneinstructionwillbe
issued(orfinish)eachcycle.

Duringanycycle,oneinstructionispresentineachstage.

Ideally,performanceisincreasedfivefold!
However,thisisrarelyachievableaswewillsee.

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