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I. INTRODUCTION
The self-oscillating flyback converter, often referred to as
the ringing choke converter (RCC), is a robust, lowcomponent-count circuit that has been widely used in lowpower off-line applications. Since the control of the circuit
can be implemented with very few discrete components
without loss of performance, the overall cost of the circuit is
generally lower than the conventional PWM flyback
converter that employs a commercially available integrated
control .
Generally, the operation of the circuit is not well
understood. This is primarily due to the fact that existing
literature deals with the circuit in a very superficial manner
[1]-[2]. Therefore, the design of this converter usually
follows a cut- and-try approach, which is a time consuming
process and which usually doesnt lead to an optimized
design.
The purpose of this paper is to present a complete designoriented steady-state analysis and small-signal model of the
self-oscillating flyback converter that can be used in the
optimization of this circuit. In addition, a step-by-step design
procedure of the control circuit is presented and verified on
an off-line, 5-V/2-A, stand-by power supply.
T1
NP
LF
NS1 i 1
CO1
i01
RL1
CF
Rd1
VO1
Rd2
RST
VIN
S1
NS2
VDS
ZD1
CO2
V2
VG i S1
RL2
VO2
D2
i2
i02
R ZCD
RS
V ZCD C ZCD
IC1
RF
Vd
RA
Q1
PWM
MOD
IK
VQbe
ie
RB
CEA2
CEA1
VKA
REA1
TL431
E/A
Steady-State Operation
In order to simplify the explanation of the converter shown
in
Fig. 1
during
steady-state
operation,
several
approximations have been made. The first approximation is
to neglect the leakage inductance of transformer T1. This
eliminates the need to consider the action of a voltage clamp
across primary winding NP which is implemented to protect
main switch S1 from voltage ringings. The second
approximation is to model error current ie as a constantcurrent source, i.e., to replace compensated error amplifier
TL431, opto-coupler IC1, capacitor CF, and resistors Rd1, Rd2,
RA, and RB with constant-current source ie. The final
approximation is to neglect the capacitance CGD between the
gate and drain terminals of main switch S1 and to model the
terminal capacitances between the gate and source CGS and
between drain and source CDS as input capacitance CISS and
output capacitance COSS respectively. In addition to these
approximations, it is assumed that CO1>>CO2, and RL1<<RL2.
The assumption CO1>>CO2 implies that the ripple voltage of
output VO2 is greater than the ripple voltage of main output
VO1. Another assumption is that time constant RSTCISS is
much greater than switching period TS, i.e., RSTCISS>>TS.
With this assumption, it is possible to ignore start-up resistor
RST during steady-state operation. Finally, it is assumed that
rectifiers D1 and D2 are ideal i.e., have zero forward voltage
drop while conducting.
To facilitate the explanation of the converter operation,
Fig. 2 shows eleven topological stages of the circuit in Fig. 1
during a switching cycle, including the reference directions of
currents and voltages, whereas Fig. 3 shows key waveforms
of the power and control stage.
Prior to t = t0, current iQce and voltage VCZCD is positive,
and switch S1 is turning off because charge is drawn from
input capacitance CISS of main switch S1 by transistor Q1. As
a result, drain-source voltage VDS increases towards
VIN + NVO. When, at t = t0, voltage VDS reaches VIN + NVO,
rectifiers D1 and D2 start conducting. During this stage, which
is shown in Fig. 2(a), magnetizing current iM is
instantaneously commutated from switch S1 to output
rectifiers D1 and D2 since it is assumed that leakage
inductance Llkg of the transformer is zero. In the presence of
winding resistances (not shown in Fig. 2), the selection of
output capacitors CO1>>CO2 causes voltage VO1 to be
approximately constant while voltage VO2 increases, which
results in a faster decrease of current i2 with respect to current
i1, as shown in waveforms (d) and (e) of Fig. 3. Because
during this topological stage rectifier D2 is conducting,
voltage VRZCD across resistor RZCD is equal to
(VGS + VS + VCZCD ) (VGS + VCZCD ) since VS << VGS + VCZCD . This
voltage induces current iZCD through resistor RZCD which
discharges capacitors CISS and CZCD. At the same time,
transistor Q1 is off and current ie flows through the loop
consisting of resistors RF, RS, and RL2. It should be noted that
T1
N S1
V1
NP
LM
VIN
iM
S1
V DS
R L2
D2
VRZCD
RZCD
VCZCD
CZCD
RF
iQb
NP
COSS
CISS
S
ie
VQbe
NP
S1 D
G
COSS
C ISS
RS
Dbc
D1 C
O1
RCO1
RL1
NP
C ISS
NP
ie
D1 CO1
RCO1
RL1
NP
NS2
CO2
RCO2
V IN
RL2
C ISS
Q1
ie
t9
D
S
RF
e
(j) t 8
S1
RS
C ISS
D1 C
O1
RCO1
NS1
RL2
(k) t 9
ie
t8
RL1
NP
D1 CO1
RCO1
RL1
CO2
RCO2
RL2
NS2
LM
V IN
S1
D
S
RF
b
ie
Q1 b
(i) t 7
RZCD
CZCD
c
RF
t7
CISS
RL2
RZCD
CZCD
NS2
CO2
RCO2
NS2
CO2
RCO2
Q1
RS
ie
LM
RL1
LM
Q1 b
D1 C
O1
RCO1
V IN
S1
V IN
RZCD
CZCD
NS1
RL2
ie
t5
RL1
NP
NS1
Q1 b
e
(f) t 4
RF
(h) t 6
LM
t6
NS1
ie
RZCD
CZCD
RS
RL2
RF
D1 C
O1
R CO1
CO2
RCO2
RZCD
CZCD
RS
t4
CISS
RL1
NS2
C ISS
NS2
D1 C
O1
RCO1
LM
RF
Q1 b
ie
V IN
CO2
R CO2
Q1 b
(g) t 5
RL2
RF
t2
S1 D
G
LM
S1
Q1 b
NS1
COSS
V IN
RF
RL2
RZCD
CZCD
S1 D
G
Dbc
NS1
NS2
CO2
RCO2
RS
RL1
RZCD
CZCD
(e) t 3
LM
RS
ie
V IN
RS
t3
NS1
COSS
CISS
Dbc
NP
V IN
RF
Q1 b
D1 C
O1
RCO1
NS2
S1 D
G
(c) t 1
CO2
RCO2
COSS
RS
t1
LM
RZCD
CZCD
(d) t 2
NP
RL2
C ISS
ie
t 10
RS
RL2
RZCD
CZCD
S1 D
G
COSS
Q1 b
NS1
NS2
V IN
S1
RL1
CO2
D2 RCO2
V IN
RF
RL1
NS2
LM
CZCD
(b) t 0
LM
RL2
D1 CO1
RCO1
NS1
NP
RS
CO2
RCO2
CO2
RCO2
RZCD D2
S1 D
G
D1 CO1
RCO1
RL1
NS2
V IN
(a)
NS1
D1 CO1
RCO1
LM
V02
iRf
VQbc
Q1
i2
VZCD
iQce
RS
CO2
NS1
V01
NP
V2
VGS
VS
R L1
NS2
VP
iS1
D1 i1 CO1
RZCD
CZCD
C ISS
Q1
RF
b
ie
e
(l) t 10
t 11
Fig. 2 (a) Simplified circuit diagram of self-oscillating flyback converter which contains voltage and current designators. (b) (l) Topological stages of
self-oscillating flyback converter.
turned on. After switch S1 is fully turned on at t = t7, drainsource current iS1 starts increasing linearly with slope
diS1 dt = VIN L M . As a result, voltage drop VS = iS1RS across
sensing resistor RS also increases with the same slope. This
t0
VGS
t1
t2
t3 t5
t4
t6
t7
t8
t 9 t11
t10
(a)
VTH
t
VIN +NVO1
VDS ,
VIN+NVO1
VIN
(b)
VDS
t
(c)
S1
t
(d)
1
t
(e)
t
VQbe
(f)
t
(g)
iRF
t
(h)
iQce
t
VCZCD
(i)
t
amplifier compensation requires knowledge of the smallsignal transfer functions in the control loop. Since the selfoscillating flyback converter operates with a variable
switching frequency, the small-signal block diagram model
differs from that of the conventional, constant-frequency type
PWM converter, as discussed in [3].
To facilitate the design optimization of the control loop, the
self-oscillating flyback circuit in Fig. 1 has been simplified to
include only circuit elements which plays a role in the
feedback control, as shown in Fig. 4. Zero-current-detect
components RZCD and CZCD, which are related to the
switching transitions, and zener diode ZD1, which clamps the
potential of the gate terminal of switch S1, are neglected.
Also, since small-signal error current ie is not a function of
output voltage VO2, but rather is a function of small-signal
error amplifier current iEA , auxiliary winding NS2, capacitor
CO2, resistor RL2, and rectifier D2 can be neglected. Smallsignal error current ie can, therefore, be represented as a
dependent current source, as shown in Fig. 4. Finally, start-up
resistor RST is neglected.
Based on this equivalent circuit, the small signal block
diagram is derived, as shown in Fig. 5. The block diagram
consists of control-to-output voltage transfer function
V
, output voltage sensing gain K = V
V
, error
G VeVo (s) = V
O
e
d
1
O
amplifier transfer function G EA (s) = VEA V1 , transconductance
gain G1 = iEA VB , opto-coupler gain G 2 = ie iEA , and
transresistance gain G 3 = Ve ie . The transfer function
expressions are summarized in Table 1. The block diagram is
further simplified by incorporating transfer function blocks
GVeVo(s), G1, G2, and G3 into block G VEA VO (s) = VO VEA to
form a single loop system, where
G VEA VO (s) =
V
G 1G 2 G 3 G VeVo (s)
TINNER
O
=
=
1
+
1
+
G
G
G
G
(
s
)
TINNER
V
1
2
3
VeVo
EA
N : 1
D1
LF
S1
Kd
CO1
CF IO
RCO1
RCF
Rd2
G1
^
VB
RS
RB
^
iEA
G3
RF
GEA(s)
Q1
^
ie
Small-Signal Model
Rd1
VO
Gvevo (s)
R LF
LM
VIN
, (1)
VQbe
^
V
=^
EA VKA
CEA2
CEA1
REA1
TL431
i e = iEA
^
Ve = (RS + RF )^i e
G2
Fig. 4 Simplified circuit diagram of self-oscillating flyback converter for
small-signal modeling and analysis
GV
(s)
EAVO
^
VO
GVEVO (s)
^
Ve
Kd
^
V1
TINNER
G3
^i
e
G2
G1
^i
EA
^
VB
+
_
A.
GEA(s)
^
VEA
G 1G 2 G 3 M dc
(s s z1 + 1)(s s z2 + 1)
1 + G 1G 2 G 3 M dc s s *p1 + 1 s 2 2O + s QO + 1
) , (2)
)(
(3)
Steady-State Considerations
To achieve good output voltage regulation during steadystate operation, ramp voltage iS1RS summed with dc voltage
ie(RF+RS) must fit within the regulation window throughout
the line and load range, as illustrated in Fig. 6. The upper
limit of the regulation window is the cut-off voltage V of
transistor Q1, which is inherent to the transistor selected,
whereas the lower limit of the regulation window is defined
by the full load current. To achieve output voltage regulation,
resistors RB, RS, and RF must be carefully selected to limit the
error current within this regulation window.
Maximum error current iemax occurs at minimum load, as
shown in Fig. 6. At minimum load, less energy is needed to
maintain the output voltage which is why the on time of
switch S1 is very short. Conversely, minimum error current
occurs at full load because a longer on time is needed to store
the required energy. It should be noted that unlike the
standard PWM, whose on time is determined at the moment
the ramp voltage reaches the control voltage, the on time of
this control circuit is determined once sufficient charge is
removed from input capacitance CISS by transistor Q1, which
is turned on the moment base voltage VQbe reaches its
intrinsic cut-off voltage V.
The design constraints for the selection of the control
circuit components for steady state operation are based on the
operating range of the circuit as well as on component
ratings. Specifically, cathode-anode voltage VKA and cathode
current IK of error amplifier TL431 are limited to
VREF<VKA<36 V and 1 mA<IK<100 mA. Voltage VKA can be
expressed as
TABLE 1
SMALL-SIGNAL TRANSFER FUNCTIONS
G VeVo (s)
sz2
M dc
1
C F R CF
1 RB
(s s z1 + 1)(s s z2 + 1)
p1
)(
+ 1 s 2 2O + s QO + 1
sp1
LF
G1
(s s
Kr
C O1 + C F
Mdc
O
VIN
2R S I O
L F (1 C O1 + 1 C F )
1
C F + C O1
G2
GEA(s)
A s s zcomp1 + 1
s s s pcomp 2 + 1
R d1 + R d 2
R d1R d 2 (C EA1 + C EA 2 )
1
CO1R Co1
sz1
Kr
IO N
VIN (1 + N VO VIN )
Kd
R d2
R d1 + R d 2
G3
R F + RS
*
s p1
(1+G1G2G3Mdc)sp1
szcomp1
1
R EA1C EA1
spcomp2
1 C EA1 + 1 C EA 2
R EA1
TABLE 2
STEP-BY-STEP DESIGN PROCEDURE
I1
Imax
1
I1min
REGULATION
WINDOW
VQbe
i emax RF
i eminRF
t
S1
ON
OFF
(4)
VKA = VO Vd I K R B .
Since at minimum load, current IK is maximum, as seen from
Fig. 5, where IK = ie/, and, therefore, voltage VKA is at a
minimum. Resistor RB can be expressed as
RB <
min
VO Vd VKA
max
IK
(5)
max
0.001 PIN
i pk D max 3
S1
(6)
(8)
where i
=V D
L f
.
Finally, error current ie is related to cathode current IK
through dc current transfer ratio of optocoupler IC1,
(9)
ie = IK .
The design procedure for the selection of the control circuit
components RF, RS, and RB for steady state operation can be
broken down to five design steps, summarized in Table 2. It
should be noted that resistor RB, whose value also affects the
voltage loop dc gain, should be chosen as low as possible
while adhering to step 5 in order to maximize the loop gain.
Generally, a 20- resistor serves as a good first iteration for
output voltage VO1 less than 35-V. Later, when system
stability is considered, the value of resistor RB will be reevaluated.
The design of components RA, CZCD, and RZCD can be
determined independently from steps 1-7 of Table 2. For
example, the role of resistor RA is to reduce power loss PIC1
of the phototransistor within optocoupler IC1, where PIC1 is
PIC1 = VCE i emax = (VO 2 i emax R A VQbe )i emax < device power rating (10)
pk (max)
S1
max
IN
max
min
M S
Step 1
Choose I max
based on TL431 current limits
K
Step 2
Step 3
Step 4
Step 5
Step 6
Check I min
from Eq. 8 to ensure within TL431 limits
K
Step 7
max
using Eq. 4 at i K = i min
Check VKA
K
The role of capacitor CZCD is to block dc current during startup, allowing charge to be delivered from the input voltage
through start-up resistor RST until switch S1 turns on for the
first time. Otherwise, capacitor CZCD merely delays the full
turn-on of switch S1 by increasing the length of time spent by
switch S1 in the constant-current region, which is undesirable
from a power conversion efficiency point of view. Therefore,
it is recommended that capacitor CZCD be set ten times greater
than input capacitance CISS. Since capacitors CZCD and CISS
form a voltage divider at the gate of switch S1, steps should
be taken to clamp the gate voltage with zener diode ZD1 to
avoid exceeding the terminal voltage rating. The role of
resistor RZCD is to limit power PZD1 dissipated by zener diode
ZD1,
R ZCD =
max
VIN
(NS2 N P ) VZD1 V .
ZD1
PZD1
(11)
Compensation Calculations
(13)
C EA 2 = C EA1 10 .
(14)
The small-signal block diagram model was verified by
comparing it to measurements made on a 5-V, 2-A selfoscillating flyback converter operating from a 400-V nominal
dc voltage under full load conditions, as shown in Fig. 7. As
can be seen, both the measured and calculated Bode plots
show an excellent agreement up to one-tenth of the minimum
switching frequency, i.e., up to 4 kHz, where the minimum
switching frequency is equal to 40 kHz. Beyond one-tenth of
the switching frequency, the compared phase plots are shown
to diverge, possibly due to a right-half-plane RHP zero which
is not described by either the small-signal model presented in
Table 1, or by the small-signal model presented in [3].
30
III. SUMMARY
20
10
Gain [dB]
10
20
30
40
50
10
100
3
1 .10
frequency [Hz]
1 .10
1 .10
1 .10
1 .10
Calculated Gain
Measured Gain
Breaking the Loop at T1
200
150
phase [deg]
100
50
50
100
10
100
1 .10
frequency [Hz]
Calculated Phase
Measured Phase
Fig. 7 Calculated and measured Bode plots of loop gain T1 of off-line, 5V/ 2-A self-oscillating flyback converter