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6-1
CHUNG-YU WU

Chapter 6 Frequency Response of MOS Amplifiers

6-1 Single-Stage Amplifier
6-1.1 Source follower
High-frequency small-signal equivalent circuit
Cgd1
Ii RS

+VDD
RS
M1
Vi

Vi

Cgs1

Vo

CX

gds1

-gmb1 Vo

gm1(Vi-Vo)

Zi
Vo
gds2

Cdb2

Csb1

CL
Zo

M2
VBIAS
-VSS
AV(s)

Vo(s)
=
Vi(s)

Rs(C gs 1 CL eq

sC gs1 + g m1
g
+ Cgs1 Cgd 1 + Cgd 1C Leq )s 2 + ( m1 RsC gd1 + C Leq + C gs1 )s + g m1 / 1 + G Leq
1

where GLeq=gds1 +gds2 , CLeq=CL+Csb1 +Cdb2

* Left-Half-Plane (LHP) pole: fp =

G Leq + g m1 / 1
2( Cgs1 + C Leq )

LHP zero: fz =
In general,
* If

fpfz

gm1
2C gs1

CLeqCgs1

C Leq
G
1
= ( 1) + Leq , we have
Cgs1
1
gm1
fp = fz and Av(s)

C gs1
1 indep. of s.
Cgs1 + CLeq

>Better high frequency response.

How to achieve this?
Adding an extra capacitor Cx such that

1
Cx+Cgs1 =CLeq
G Leq
1
( 1) + g
1
m1

Zi(s)

6-2

CHUNG-YU WU

Cgs1 s + g m1

Vi (s ) 1
=
+
(C gd1 s)
Ii( s) C gs1s Cgs1 s( G Leq + g mb 1 + sC Leq )

||

* If gmb1 +GLeq<< CLeqS and Cgd1 is neglected,

1
1
g m1
Zi(s)
+
+
Cgs1 S C LeqS C gs1 CLeqS 2
The input impedance consists of the series connected
Cgs1 , CLeq, and the negative resistance
gm1

C gs1 C Leq2
Thus oscillation is possible.
* If gmb1 +GLeq is neglected, the equivalent input capacitances

||

Cin=Cgd1 Cin'

Cin' CLeq
C
g
Leq + 1 + m1
C
C gs1s
gs1
For large gm1, Cin 'CLeq
The large load capacitance CL is well blocked or buffered from the preceding stage.
Zo(s)

Vo(s )
Io(s )

|Vi=0 =

G Leq + g mb 1 + sC Leq + ( sC gs1 + g m1 )

* If s = 0, Zo = Ro =

1
g m1 + g mb 1

If s, Zo'(without CLeq) Rs for Rs

Since usually Rs

R s Cgd 1s + 1
R s ( C gd1s + Cgs1 s) + 1

1
, we have
g m1 + g mb 1

1
and Cgs1 >>Cgd1
G Leq + g m1

6-3
CHUNG-YU WU

|Zo|
Rs

1 /gm1

> Zo > Inductive load

Zo(s)

R s C gs1 s + 1
g m 1 / 1 + C gs1 s

R1 =Rs

L
R1

1
g m1

Zo
R2

1
g m1
C

L= gs1 1 (Rs 1 )
g m1
g m1
R2 =

L and CL causes output signal ringing.

* Two source followers in cascade might cause oscillation because
First SF L in Zo 1
Second SF -R and Cin Z i 2
6-1.2 Enhancementload NMOS common-source gain stage
+VDD

RS

Vo
RS
M1

gmb2 Vo
gm2Vo

Cgs2

M2

V1

+
CL V_i

Cgd1
Cgs1

gm1V1

Cdb1

Csb2

Vi
-VSS

RS

V1

Cgd1
Vo

+
V
_i

Cgs1

gm1V1

GLeq

CLeq

CL

gds2
Vo
gds1

6-4
CHUNG-YU WU

GLeq=gds1 +gds2 +gm2+gmb2

CLeq=Cdb1 +Cgs2 +Csb2 +CL
Applying the Miller's theorem, we have
V1

Vo

RS
Vin

GLeq

Cin
(gm1-sC gd1 )V1

Cin =Cgs1 +Cgd1 (1+gm1/GLeq)

>Av(s)

Gs (sC gd1 g m1 )
(sC in + Gs )[s(C Leq + Cgd 1 ) + C Leq ]

* Right-Half-Plane ZeroSz = gm1/Cgd1

* Left-Half-Plane Poles Sp1 =Gs/Cin (input pole)
Sp2 =GLeq/(C Leq+Cgd1 ) (output pole).
If Cgd1 and CLeq are small >Sp1 is the dominant pole.
* If CL is large, the dominate pole is Sp2 (gm2+gmb2 )/C L
* The input impedance can be approximated by
Zin

1
)Cgd 1 s
Cgs1 + (1 + g m1
G Leq

near the upper 3dB frequency.

* The exact Zin is

1

1+
(C gd1 + C Leq )s

G Leq

Zin Cgs1 s
1
1
C (1 + g
+
C Leqs)
m
gd1s

G Leq G Leq

||

If

1
1
1
( Cgd1 + CLeq )s <<1 and
Cgds1 s (1+gm
),
G Leq
G Leq
G Leq

Zin can be approximated by the previous formula.

CLeq+Cgd1

6-5
CHUNG-YU WU

6-1.3 Cascode amplifer stage

Cdb2

+VDD
V1 Cgd1

RS
M3

Vin
Vo

VBIAS

M2

CL

RS

Vin

M1

Cdb1

gm1V1

Cgs1

RS

-gm2V2
Cgs2 +
Csb2

rds1

V1
C2
(gm1-sCgd1)V1

1/g2

gm2V2

rds2 , rds3 , gmb2 , gmb3 are neglected.

1
rds1

gm1
) Cgd1
g m2
C 2 = C gd1 + C db1 + C gs2 + C sb 2
C 2 = Cgs1 + (1 +

C Leq = C L + Cgd 2 + C db 2 + Csb 3 + C gs 3

A v ( s) =

Gs g m 2 ( sC gd 1 g m 1 )
(sC 1 + G s )(sC 2 + g 2 )( sC Leq + g m 3 )

RHP Zero: Sz =

g m1
Cgd1

gm3
Gs
g
; Sp 2 = 2 ; Sp 3 =
C Leq
C1
C2
usually is the dominant pole.

LHP Pole : Sp 1 =
Sp 1

f 3 dB

S p1
2

gm3V3

Cgd2

Csb3

CL

Vo

Vo

Vin

g2 = gm2 +

Cgs3

V2

C1

-VSS

+
V
_3

Gs
2C1

* Typically, g m 1 = g m 2 ,then C1 = C gs1 + 2Cgd 1

CLeq

1/gm3

6-6

6-1.4 CMOS gain stage

+VDD

CHUNG-YU WU

V1

Cgd2
gm2V1

gds2

Cgs2
M2

RS

RS

Vo

V1
Vin

M1

CL

Cdb2

Cgd1

Vo
gm1V1

Vin
Cgs1

gds1

Cdb1

-VSS
RS

Cgd1 + Cgd2
Vo
(gm1+ gm2)V1

Vin

Cgs1 + Cgs2

RS

GLeq

CLeq

V1

Vo

[g m 1+ g m 2-s(C gd1+Cgd2)]V1

Vin

GLeq

Cin

G Leq = g ds1 + g ds 2
Cin = Cgs1 + C gs 2 + (1 +
Av (s)

CLeq+Cgd1 +Cgd2

C Leq = Cdb 1 + C db 2 + C L

g m1 + g m 2
)( Cgd 1 + Cgd 2 )
G Leq

G s [s( Cgd 1 + Cgd 2 ) ( g m 2 + g m 2 )]

[ s( Cgd1 + Cgd 2 + C Leq ) + G Leq ]( sC in + G s )

RHP Zero: Sz =

gm1 + gm2
Cgd 1 + Cgd 2

LHP Poleo: Sp 1 =
Sp 2 =

Gs
Cin
G Leq
C gd1 + C gd 2 + C Leq

If R s is large enough ( R s is the output resistance of the preceding stage),

S p1 << S p 2
Sp 1 is the dominant pole.

CL

6-7

6-1.5 CMOS differential amplifier

1.Differential-mode half circuit

CHUNG-YU WU

Cgd1
+
1
V Cgs1
2 id

1
g V
2 m1 id

rds4 ||rds1 +
1
Vod
2
_

CLeq

_
CLeq CL + Cdb 4 + Cdb 1
+VDD

+VDD

M4

M3

VBIAS

VBIAS1

M4

1
V
2 id

CL

1
V
2 od

CL

M2

M1

M1

VBIAS2
-VSS
-VSS

Ad =

Vod
g m1
= H (s ) =
Vid
g ds 4 + g ds1
RHP Zero: f z =

Cgd 1

gm1

C Leq + Cgd1

1 + ( g + g )s

ds 4
ds1

gm1
2 Cgd1

fz >fp

|Ad|
-60db/Octave

g ds4 + g ds1
LHP Pole: f p =
2( Cdb 4 + Cdb1 + C L + C gd1 )
f u A0f p =

gm1
2 ( C db 4 + C db1 + C L + C gd1 )

fu fz
fp

2.Common-mode half circuit:

( g ds 4 + sC M ) Voc + g ds1 ( Voc Vs ) + g m 1 ( Vic Vs ) + C gd1 s( Voc Vic ) = 0

6-8
CHUNG-YU WU

g ds 1 ( Vs Voc ) + Vs (
Vs [

C + Cdb 5 + Csb1
1
+ gd 5
s) g m1 ( Vic Vs ) Cgs1 s( Vic Vs ) = 0
2 rds5
2

1
1
+ ( Cgd 5 + C db5 + C sb1 )s + C gs1s ] = [ g ds 4 + sC M + sC gd1 ]Voc + (C gs1 s + C gd1 s) Vic
2 rds 5 2

Vs =

[ g ds4 + sC M + sC gd 1 ]Voc ( Cgs1 s + C gd1 s) Vic

C gd 5 + C db5 + Csb1
1

s + C gs1s
2r +
2
ds 5

+VDD
Vic

Cgd1

Voc

M4

VBIAS1

gm1(Vic-Vs)

Voc

gds1

gds4

CM

CL

M1

Vic

Cgs1
VS

VS

(C sb1 +Cgd5 +Cdb5 )/2

VBIAS2

2/gds5

2M5
CM=CL+Cdb4 +Cdb1
gmb1 is neglected

-VSS
C gd1 (

+ Cgs1 )s 2 + [(

Cgd 5 + Cdb 5 + C sb1

+ C gs1 ) g m1
Voc
2
2
=
Cgd 5 + Cdb 5 + Csb1
C gd 5 + Cdb 5 + Csb1
Vic
(
+ Cgs1 )( C M + Cgd 1 )s 2 + [(
+ Cgs1 )
2
2
1
1

Cgd 1 ( g ds1 + g m 1 )( Cgs1 + Cgd1 )]s +

g m1
2rds 5
2 rds5
C + C gd1
g + g ds1
+ g ds1 ) + M
+ (C M + Cgd 1 )( g ds1 + g m1 )]s + ds 4
+ ( g ds1 + g m1 ) g ds 4
2 rds5
2 rds 5

A c ( s) =

( g ds 4

C gd 5 + C db5 + Csb1

Solve the pole-zero position : 1 RHP zero, 1 LHP zero,2 LHP poles
fZR
fZL
fp1 fp2
dB Ad
fZR >> fZL
CM
(C gd5 +Cdb5 +Csb1 )/2
Ac
fp1

fZL

fp1 < fp2

fp2
Load pole

CMRR
CMRR

degradation region

tail pole

6-9
CHUNG-YU WU

6-1.6 CMOS differential-input-to-single-ended output converter

Vi
Vo

Vi = Vid + Vic Vo = Vod + Voc

+VDD

The hail-circuit method cannot be used in

the high frequency analysis.
Two unequal signal paths to the output
Load path and tail path
Both Cs and C E appears in the Ad(s)
expression.
There are two dominate poleo in Ad.
g + g ds 4
Output pole Wp 1 ds1
CLeq
Mirror pole Wp 2
Tail path: A1 (s ) =

M4
E

M3

CE
Load
M1

Vin

M2
Tail

Ro

g m 34
CE

Io

CS

-VSS

A0
s
1+
Wp1

Load path: A2 ( s) =

A0
(1 +

s
s
)(1 +
)
Wp 1
Wp 2

s
)
Wp 2
Ad ( s) = A1 (s ) As ( s) =
s
s
(1 +
)(1 +
)
Wp1
Wp 2
A0 ( 2 +

LHP zero: Wz1

2 g m 34
= 2Wp 2
CE

Approximate analysis:
The dominant pole of Ad ( s) is Sp 1 =
Ad ( s)

sC Leq

g m1
+ ( g ds1 + g ds 4 )

g ds1 + g ds 4
(output pole)
CLeq

Vo
CLeq

The A c ( s) can be written as Ac ( s)

The dominant pole of A c ( s) is Sp 1 =
But the left-half-plane zero is SzL =
The CMRR (

g ds1
2g m 4

6 - 10

1
( ) + sC s
R0
sC Leq + ( g ds1 + g ds 4 )

CHUNG-YU WU

g ds1 + g ds 4
CLeq

1 1
( )
R 0 Cs

Ad
) is degradated by 20dB/decade at high frequency.
Ac

6-2 Frequency Compensations

+VDD

Ml1

M l2

M g1
V1

Cd

M s1

gdsl+gdsi

CC

M i1
~

Mi2

vi1

gdsgl+gdsg2
V2

vi2

CL

M g2
M s2

VBIAS

-VSS

Without CC
SP 1 =

1
( g dsl + g dsi ) ,
Cd

SP 2 =

1
( g dsg1 + g dsg 2 )
CL
V2
V1

equivalent
circuit

g mi(vi1 -v i2)
=gmivd

CC
Cd

g dsl+gdsi

CL

g dsg1+gdsg2

gmg1+gmg2

vd vi 1 vi 2

6 - 11
CHUNG-YU WU

v2
vi1 vi 2

H(s ) =

+ g mi ( g mg1 + g mg 2 )R d Ro ( 1
=

sC C
)
g mg1 + g mg 2

1 + s [( C L + CC )RO + ( CC + C d )R d + CC ( g mg1 + g mg 2 )RO Rd ] + ( C C C L + CC C d + C d C L )RO R d s 2

where Ro
Sp1

1
g dsg1 + gdsg 2
1

'

Sz
'

Rd

Sp2
'

( g mg1 + gmg 2 ) RO Rd CC

gmg 1 + g mg 2
CC

1
g dsl + g dsi
CC ( g mg1 + g mg 2 )
CO CL + Cd C L + Cd CC

RHP Zero

gain
dB

RHP zero
f p1

'

fz

'

'

f p2

log(f)

phase
0

- 45 o
- 135 o

180 o

Phase margin is not

large enough
log(f)

Feedforward effect on CC
How to solve this problem ?
If I C = ( gmg 1 + g mg 2 )Vd ,
C

I o = 0 and V2 = 0

A zero is formed.

IC

V1

V2
CC

Ro

Io

(gmg1+gmg2)v

6 - 12
CHUNG-YU WU

6-2.1 Using a unity-gain buffer in the feedback path

Unity Gain
Buffer
CC
V1

V2

CC

+
~ V
2
-

V1

V2

Isolate node 1 from node 2 to prevent feedforward.

Keep the Miller effect unchanged.
Source follower can act as a unity gain buffer.
g miVd +

(g

mg 1

V1
+ Cd sV1 + ( V1 V2 )Cc s = 0
Rd

+ gmg 2 )V1 +

H( s ) =
=

Sp2
'

1
V2 + CL sV2 = 0
Ro

--------- (2)

V2
Vd
g mi( g mg1 + g mg 2 )
1 + s[RoCc + Rd ( Cd + Cc ) + Cc ( g mg1 + g mg2 )Ro Rd ] + ( Cc CL + Cd C L )Ro Rd s

S p1
'

--------- (1)

(g

mg 1

+ g mg 2 )Ro Rd Cc

Cc ( gmg 1 + gmg 2 )
C cC L + C d C L

(unchanged)

RHP Zero has be eliminated.

6 - 13
CHUNG-YU WU

Actual Circuits :
1

VDD

M1

VBIAS

M1

CC

CC

M2

V1

VDD

V2

M2

V1

V2

VBIAS or
connected to the
output

-VSS

-VSS
Cgs1
CC

V1

Rout

V2

Cout
CL+Cgd1
+
-

V2
-

Cgs1 may introduce a RHP zero. But usually this RHP zero is large.
Cgs1 is very small.
Rout (
g miVd +

If

1 1
)
g m1 gm 2

V1
1
1
+ Cd sV1 + ( V1 V2 )(
+
) 1 = 0
1
Rd
Cc s
+ Couts
Rout

1
Cout s
Rout
1

1
1
Cc s

+
Cc s

1
C c Rout s + 1
+
C
s
out

Rout

6 - 14
CHUNG-YU WU

The numerator of H ( s ) =

LHP Zero :

V2 ( s )
Vd ( s )

is g mi ( gmg 1 + g mg 2 )( Cc Rout s + 1 )

1
Cc Rout

If Rout is large , LHP Zero may form a pole-zero doublet with Sp1 or Sp2
very slow slew rate !!
If Rout is small , too large gm1 or gm2 is required.
(large area ,large power)
large Cout.

Freq. Resp.

Somehow difficult to design.

Also the power dissipation of the buffer is large. (additional power

dissipation)

6-2.2 Adding Rc in series with Cc.

H( s ) =

v2
can be solved.
vd

CC

V1

Low frequency gain : Adm = g mi (gmg 1 + g mg 2 )Ro Rd

LHP Poles : SP 1

(g

mg 1

SP 2
SP 3

1
(unchanged)
+ g mg2 )Ro Rd Cc

(g

mg 1

+ g mg 2 )Cc

Cd CL + Cc C L + Cd Cc
Cd Cc + Cd CL + Cc CL
RC Cd CL Cc

g mg1 + g mg 2
LHP

Zero : SZ =
Cc [Rc (g mg1 + g mg 2 ) 1]
RHP

(unchanged)

RC

V2

6 - 15
CHUNG-YU WU

1. If RC =

1
1
or RC =
g mg1 + gmg 2
g m2

S Z

g m 2 : second-stage transconductance

No effect on the frequency response of the OP.

S P 1 dominant pole Ad (s )

For >> S P1

Ad ( j ) =

Adm
A S
= do P1
s
+ 1 s + SP 1
S P1

Adm SP 1
A S
, Ad ( j ) = dm P1
j

At u , Ad ( j u ) = 1 u = Adm S P1 =
Large CL S P 2

gmg 1 + g mg 2
CL
SP2
C g + g mg 2
2 ~ 4, c mg 1
=2~4
u
CL
g mi

For phase margin 450 ~ 600

If

g mi
Cc

g mi
2 ~ 4 , C L C c stable
gmg 1 + gmg 2
Gain
dB
-6 dB/octave

1) NMOS Realization :

fu

0 dB

f p1

VDD
CC

MC

f p2

log(f)
-12 dB/octave

-VSS
V1

V2

phase
0o
- 45 o
- 90 o

log(f)

- 135 o

- 180 o

I DS

C W
2
= n ox
2( VDD V2 VTH )VDS VDS
2 L

I
RC = DS
VDS

=
V DS =0

6 - 16
CHUNG-YU WU

1
n Cox W
[2( VDD V2 VTH )]
2 L

V2 VTH body effect

( RC )o =

RC

g mg 1

1
+ g mg 2

RCmax

RCmin

Nonlinear Rc

V2min
(negative)

0V

V2max

Design Rc : (1) Design Rc, s.t. ( Rc )V =0V =

2

V2

1
1
(
)
gm 2 g mg1 + gmg 2

(2) At Rc= Rcmax or Rcmin ,

Sz must be large enough ! Otherwise, frequency
performance will be degradated.
1) CMOS Realizations :
VDD

a.

b.

CC

c.
CC

CC

M cn
M cp

V2

V1

V1

-VSS

V2

V1

-VSS

Consider the case in c.:

I DSn =
R cn =

nCox Wn
2
[ 2( VDD V2 VTHn )VDS VDS ]
2 Ln
1

n C ox W n
[ 2 ( V DD V 2 V THn )]
2
Ln

V2

C W
2
I DSp = p ox p [ 2( V2 + VSS VTHp )VDS VDS ]
2 Lp
Rcp =

pCox Wp
[ 2( V2 + VSS VTHp )]
2 Lp

Rc = ( Rcn // Rcp )1 = Rcn + Rcp

1

If

6 - 17
CHUNG-YU WU

p C ox W p
n C ox Wn
[ 2(V DD V2 VTHn )] +
[ 2( V2 + VSS VTHp )]
2 Ln
2 Lp

nCox Wn pCox W p
=
=
2 Ln
2 Lp
Rc = [ 2VDD 2VTHn + 2VSS 2VTHp ] nearly indep. Of V2
1

Rc

1
V 2 =0 V

= g mg1 + gmg 2

Rc-1

Rcn-1

V2min

2. If Rc =

Rcp-1

0V

V2max

V2

1 + ( Cd + CL ) / CC
g mg1 + gmg 2

Sz = Sp2 and pole-zero cancellation occurs.

Sp3 >> Sp1 AdmSp1 < Sp3 stable
However, if the cancellation is not complete
pole-zero doublet occurs ! slow slew rate.

6 - 18
CHUNG-YU WU

6-2.2 Feedforward compensation

Av3 is the gain of the source follower
A V3

Vin

Vout

+
-A V2

Av 3 ( 0 )( 1 +
Av 3 =

(1 +

s
)
z3

s
)
P3

s
s
)( 1 + )
z1
z2
s
s
( 1 + )( 1 + )
P1
P2

Av 2 ( 0 )( 1
Av 2 =

1 LHP zero
1 LHP pole

2 LHP poles
1 RHP zero (C C)
1 LHP zero

z3 & z2 are generated from the Cgs of the source follower.

Vout
= AVTOT ( s ) = AV 2 ( s ) + AV 3 ( s )
Vin
s
s
s
( 1+
)( 1 +
)( 1 +
)
z1'
z2'
z3'
= [ AV 2 ( 0 ) + AV 3 ( 0 )]
s
s
s
( 1 + )( 1 +
)( 1 + )
p1
p2
p3
p1' : dominant pole
z 1' , z 2 ' , z3 ' : LHP Zeros

Design consideration : Any zeros below the unity-gain frequency must be

placed as close as possible to their matching poles.
This prevents the formation of any doublet !
z 1' = p 2 by adding CB1 and CB2(3.8pF) to control Cgs 9 + Cgs11

6 - 19
CHUNG-YU WU

Ref:IEEE JSSC , col SC-14, no.6 pp.1070-1077 , DEC.1979

Feedfoward +Miller(direct)
Ref:IEEE JSSC , col SC-15, no.6 pp.921-928 , DEC.1980
Feedfoward +Unity gain buffer + Miller
6-3 Settling Behavior
Vo

0. 1%V or 0.01%V

V
V Io g m1

TS
Slewing
Period

TP

TSET

Settling
Period

Slewing Period (Ts): Vo from 0V to V-Io/g m1 under voltage follower

connection and worse case loading.(nonlinear operation)
Settling Period (TSET -Ts):
Vo from (V-Io/g m1) to 0.1% V or 0.01% V (quasi-linear operation)
Settling Time (TSET ): Ts +( TSET -Ts) = slewing period + settling period.
6-3.1 Single-pole case
CC

+ Input
- Stage

Io
differential-input
to single-ended
output converter

Gain
Stage

Vo

6 - 20

Slew rate:

CHUNG-YU WU

SR

dVo
I
|max = o
dt
Cc

u =

gmi
single-pole case
Cc

SR =

I o u
Io
= u
uC W
gmi
2 ox ( )i
2 L

6-3.1 Two-pole case

RefIEEE JSSC vol.SC-17, no.1 pp.74-80, Feb. 1982
Ts =

g
I
1
ln[ 1 m 1 ( V o )
1
I o ao
g m1

Fig.2

approximation e T 1 1TS => eq.(19) conventional expression

1 S

After Ts Vo= V-Io/g m1

Input voltage = V-( V-Io/g m1) = Io/g m1

=> enter the linear (or quasi-linear) region

Feedback Function for unity-gain voltage-follower connection

=> A( s ) =

a( s )
1 + a( s )

eq.(20)-(23)

two poles S = n 2 1 n

eq.(24)

(double negative real poles)

1 + 2
2n

damping ratio

= 1 critically damped
< 1 underdamped
(complex conjugate poles)
=

gm 2 / c2
2
2
1 + 2

=
=
2 n
2 ao1 2 u 2 g m 1 / cc

> 1 overdamped
(real and negative pole)
(CC, C2 >> C1)

6 - 21
CHUNG-YU WU

=> CC

4(

g m1
)C2
gm 2

(CC, C2 >> C1)

2 < 4 u
2 > 4 u

4 u 2 = 2 ~ 4
u

=> 2

(1) Underdamped: TS eq. (14) or (19)

TP eq. (35), (33)
(2) Critically Damped

max.overshoot: eq.(36)
settling time: eq.(40),(39)

Vo(t): eq.(41)
TSET : eq.(43)
V
0.001

TS

(3) Overdamped

underdamped
overdamped

TSET

TSET : eq.(47)

Simulation & Calculation : Fig.7, Fig.8

V

Further references:
(1) IEEE JSSC, vol. SC-18, pp.389-394, Aug. 1983
(2) IEEE JSSC, vol. SC-21, pp.478-483, June. 1986

6 - 22
CHUNG-YU WU

6-4 Slew rate of CMOS OP AMPs

6-4.1 Two-stage OP AMPs
Two poles: S p1 , S p 2 , S p 1 << S p 2
If S p1 << u << S p 2 ,Vout ( s ) = g miVin ( s ) / sCc
Vout ( jw )
g
= m
Vin ( jw ) jwCc
At = u ,
u =

CC

Vout
=1
Vin

gm1Vin

Vout

CL

gmi
or CC = g mi / u
CC

The slew rate SR = dVout

dt

max

= I o / CC =

IC u
Io
= u
gmi
2uC ox( W / L )i

u , I o ,( W / L )i SR
* I o / C L I o / CC or CL

dVout
dV
CC out ( = I o )
dt
dt

Slew rate enhancement and degradation

Vin
V1

Vo
Vin
V1

degradation

enhancement

Vo

6 - 23
CHUNG-YU WU

(1) Positive step

+ VDD
M3

off
M4

off

Io + iw
Io + iw

CC
-

vout

off

on
vw

M1

M2

Cw

Io

iw

CL

+
+
vin
-

V1
0

- VSS

i ( t ) = C

dv ( t )
dv ( t )
C in
dt
dt
t

1
I
C
vout ( t ) =
( I o + i )dt = o t +
CC 0
CC
CC

dvin
dt
dt

Io
C
t + V1u( t )
CC
CC

(2) Negative step

+ VDD
M4
on

M3
on

Io + iw

Io - i w

CC

Io- iw

on
vw

M1
Cw
iw

off

+
M2

Io
- VSS

+
vin
-

V1

vout

6 - 24
vout v

CHUNG-YU WU

d
I i
dv
i
vout = o = =
dt
CC
dt
C
dvout
Io
=
dt
CC + C

i =

I oC
( CC + C )

slew degradation

6-4.2 Single-stage OP AMPs

SR =

Io
CL

Different phase margins

CL

Vi

different settling behavior.

Vo

I o First-stage bias current

SR of the folded cascode OP AMPs

+ VDD
Ip

M6

M5

Io

Ip

VX

M1

off
M2

VY

Ip-Io

VBIAS2

M3

Ip

M4

V
Vs

VBIAS1

Io
Ip-Io

M7

M8

Io

VB
M9

M 10
- VSS

SR =

Io
CL

* If Ip=Io, we can keep M5, M1 and Io current source in saturation.

Vout
CL

6 - 25
CHUNG-YU WU

The change of Vx is not significant because the gain of the

common-source amplifier M1 is nearly equal to 1. When M2 is
turned on, the recovery time of Vx is very short.
* If Ip < Io, the current source Io is forced to linear region and Vs
Vx . The decrease of Vx is large. Thus the recovery time of Vx
when M2 is turned on is very long, The settling is slow down.
How to solve this problem?
(1) Keep Ip = Io as the optimal design.
(2) Add clamping devices between VDD and Vx(VY)
+ VDD

VBIAS1

M 11

VBIAS1

M12

In normal operation, M11 and M12 are turned off by setting

VDD-Vx < VTH11 ,VTH12.
6-5 Power supply rejection ratio (PSRR)
6-5.1 Low frequency analysis for integrators
+ VDD
M3

M4
CC

Cgd
Vin

gain
stage

M1

M2

Cgs
Io
- VSS

CI

Vout

6 - 26
CHUNG-YU WU

Vout Cgs I o 1
V C
1 I o

+ GS 1 + gd

VSS CI VSS 2 gm1 VSS CI 2 gm3 VSS

Io
-

-VSS

C
Vout
gd
CI
VDD

CI
Cgs

I o
1 C gs 1 I o
1 V 2 g + C 2 g
DD m3
I
m1 V DD

CI
VDD

M3

Cgd

Ref. : IEEE , JSSC , vol.SC-15 , pp.929-938 , Dec. 1980.

* Cgs / CI and Cgd / CI have a strong effect on PSRR+ and PSRR-.
* Small CI chip area but PSRR.

6-5.2 High frequency analysis for OP AMPs

Ref. : IEEE JSSC , vol. sc-19 , pp. 919-925 , Dec. 1984.
+ VDD
M3

M4

M6
CC

V1
Vi +

VBIAS

M1

M2

Vo

Rz
Vi -

M5

M7

- VSS

6 - 27
CHUNG-YU WU

Vo
Vi

* PSRR+

Vo
VDD

How to calculate

Vo
Vi

V
= io
VDD

Vo = 0

Vo
VDD V

Vo =0

=0

Vio

VDD

VDD
~ Vi
Vio

Vio
VSS

CC

V1

Rz =1/gm2

Go1
gm1Vio

Vio
Go2

gm2(V1-Vi )

C1

~
PSRR+ ( s )

Vi( from VDD )

s + Go 1Go 2 /( g m2 Cc )
s + g m1 / Cc

where Go1=go4 ( go2 is connected to the drain of M5 which is

open-circuited, i.e. rds5 )
Go2=go6 (rds7 )
Go1Go2/(g m2Cc) < gm1/Cc
Low-frequency LHP zero degrades the PSRR .

6 - 28
CHUNG-YU WU

* To improve PSRR, Cc must be decoupled from the gate of M6 to

eliminate the LHP zero .




 

   
 


 






  
 
 


 
 

  

 





 
 




 




  




 





 
 



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8-1
CHUNG-YU WU

Chapter 8 Advanced Design Techniques and Recent

Design Examples of CMOS OP AMPs
8-1 Advanced Design Techniques of CMOS OP AMPs
8-1.1 Improved PSRR and frequency compensation
Vout C gs I o 1
V C
1 I o

+ GS1 + gd

V ss
C I V ss 2 g m1
Vss C I 2 g m3 V ss

P.6-26

Vout C gd
I o
1 C gs 1 I o

+
1
V DD
C I V DD 2 g m3 C I 2 g m1 V DD
If I o

Where I o represents the input stage bias current.

is independent of V ss and V DD

and the input devices have no body effect.

C gd
Vout
Vout
0

==>
CI
V ss
V DD
Ref.: IEEE JSSC, vol. SC-15, pp.929-938, Dec. 1980
BIAS GENERATOR

OP AMP

+VDD

M9

M3

IREF

V+

V-

M10

M6

M4

M1

Vo

M2
Io

M8

M11
M12

M5
VBIAS
-VSS

* I REF is generated by using the power supply independent current source.

*V BIAS is nearly independent of V DD and V ss .
*It is better to use separate p-wells for M 1 and M 2 to avoid the body effect.

M7

8-2
CHUNG-YU WU

*Tracking RC compensation
Conceptual circuits :
+VDD
+
VIN2
-

gm1VIN

+
Vos2

MB(M6)

Voltage
source

Mc
(M10)

CC

CL

MA (M8)
(RC)
KI

I
-VSS
In the quiescent case ,Vin2=VOS2

If (W / L) A [(W / L) B (W / L)C K ]1/ 2

=> RdsA

Cc
Cc + CL

Cc + CL
Rc
gm 2Cc

The requires Rc is Rc = 1 / g m2 [1 + (C d + C L ) / Cc ] 1 / g m 2 [(Cc + C L ) / CC ]

Thus LHP zero=LHP pole P2
and P3 becomes the second pole.
The stability considerations,
P3 Ado P1
or

Cc

g m1
c 1c L
gm 2

allows a smaller gm2 and larger C L

* RdsA Rc indep of temperature, process , and supply variations.
=>Tracking design to make sure that z=P2
=>No pole-zero doublet problem!

8-3
CHUNG-YU WU

CMOS Design
+VDD
M1

M3
M5
VBIAS

M13

M8

M15

M9

M11

Vout

M6

Cc
M17

M2

M16

M7
M10

M14

M12

M4
-VSS
* M17,Cc : Tracking RC compensation.
* M9,M11:Sharing the separate n-well.
* VBIAS is not strictly independent of VDD and VSS.
8-1.2 Improved frequency compensation technique.
Ref.: IEEE JSSC ,vol.sc-18, pp 629-633, Dec.1983
Grounded gate cascode compensation
+VDD
M11

M5
2x

M12

M9
3x

VBIAS1

MB
+

M13
IBIAS

M1

VBIAS2

MC1

M16

M14

M15

M2
MC2

M4

M3

VBIAS1

M7

M8
3x
M10
3x

Cc
5pF

Vo

M6

8-4
CHUNG-YU WU

MB,Cgs7:low pass filter for high frequency noises.

M8,M9,M10:new compensation circuit.
M11~M16:Bias generator.
Conceptual circuits:
+VDD
CS1

2Io

Cc

I1
A

_
gm1

-gm2

Vo

Vi

+
R1

CS2

R2

I1

-VSS
Net current in CC (C c

d
V ) enters the second stage.
dt o

The input voltage Vi cant reach the node A

* Better PSRR ( no low-freq. zero ) , especially PSRR
* Allow larger capacitive loads.
* Slight increase in complexity , random offset and noise.
8-1.3 Improved cascode structure
1. To improve gain:
Ref: IEEE JSSC , vol. SC-17, pp. 969-982, Dec. 1982
+VDD

M2

M1
M9

Vo
Rc

M1A

Cc

M2A
M7
M4A

M6

M3A
M4
M3
-VSS

M8

8-5
CHUNG-YU WU

* Substantial reduction in input-stage common-mode range.

* Improved wilson current source is used as the load to improve the balance of the
first stage.
+VDD
2. Single-stage push-pull class AB CMOS OP AMP
M5
Ref: IEEE JSSC , vol.sc-17, pp.969-982, Dec. 1982
* Inverting mode only. (+ grounded)
* Capable of high current driving and
M2 M4
BIAS
IN
high voltage gain.
* Not a differential-amplifier-based
OP AMP.

M6
M7
OUT

Cc

M1 M3

M8

_
+

M9

M10
3. Cascoded CMOS OP AMP with high ac PSRR
Ref: (1) IEEE JSSC , vol. SC-19, pp.55-61, Feb. 1984
(2) IEEE JSSC , vol SC-19, pp. 919-925, Dec. 1984
1) Original version
+VDD
200/10

200/10

25/10

Mp3

Mp2

-VSS

Mp4
1125/10

A
Mp7

50/10

IBIAS

50/10

MN1

MN2

Mp5

100/10

Cc

Mp5

Vout

100/10

CL

5A
100/10

MN9

MN5

200/10

MN3

100/10

100/10

MN4

42.5/10
MN6

-VSS
Chrarcteristics:
VDD=VSS=2.5V
Input offset voltage
Supply current
Output voltage range
Input common mode range
CMRR @ 1KHz
Unity-gain frequency
Slew rate

5mV
100A
-VSS~VDD
-VSS+1.47V ~ VDD
99dB
1.0MHz
1.8 V/sec

42.5/10

MN8

MN7

500/10

8-6
CHUNG-YU WU

* Better input common-mode range.

* Vic VDSN4 IDSN4 VA MN8 is turned on Vout-VSS
voltage spike at Vout.
* The possible spike in the settling period.
2) Improved version
+VDD
M7

VBIAS1

M12

M6
M5

VBIAS2

M8

M3

M4

M13
-

Vout
+

Cc

M2

M1

VBIAS3
M14

M9

M11

M10
-VSS

* M 12 , M 13 and M 14 : Let the drain bias currents of M 10 and M 11 follow

the change of I D7 under positive input common mode voltage.
No voltage spike at Vout
Also serves as CMFB
* Better PSRR and input common-mode range.
* C c is decoupled from the gate of the driver M 8 .
4.Simple cascoded CMOS OP AMP
Ref.:IEEE JSSC , vol.SC-19 , pp.919~925 , Dec. 1984
+VDD

VBIAS1

M8

M6

M5
M3

Vout

M4
Cc

M1
VBIAS2

M2
M5

-VSS

+
M9

* Good PSRR
* Reduced input common
range.
restrict its applications
to those which use a virtual
ground.

8-7
5.Single-stage cascode OTA
Ref.: IEEE JSSC , vol. SC-20 , pp.657~665 , June 1985

CHUNG-YU WU

+
T6

T2

T14

T8

T4

T12

In-

In+
T1

T3

T10
Out
CL

Io

T5

T9

T7
IBIAS
T11

T13

T15

T17
-

T9 ,T10 : Cascode structure

* Output conductance without any noise penalty and with only a very small
reduction of phase margin.
Gain no any compensation is necessary.
* Maximum output swing
8-2 Advanced Design Techniques on High-frequency Non-differential-type CMOS
OP AMPs
1. Single-ended push-pull CMOS OP AMP
*Current-gain-based design

8-8
+VDD
M8

CHUNG-YU WU

M9

M5

M6
M13

M14

M7

M15

OUTPUT
M1

M2

M16

CL

M12

INPUT
IB1
M3

M11
M4

M10

-Vcc

TABLE I
Parameter

Measured Value

DC-Open Circuit Gain

69dB
Unity0Gain Bandwidth
70MHz
Phase Margin
40o
200 V / sec
Slew Rate
PSRR (DC+)
68dB
PSRR (DC )
66dB
Input Offset Voltage
10mV
CMRR (DC)
62dB
Output Voltage Swing
1.5VP
Output Resistance
3 M
Input Referred Noise (@1KHz)
0.54 V / Hz
DC-Power Dissipation
1.1mWatt
V DD = +3V ; VCC = 3V ; I B1 = 50 A ; CL=1pF
TABLE II
Bias Current

Unity-Gain
Bandwidth

DC-Open Circuit
Voltage Gain

DC-Power
Dissipation

25 A
50 A
100 A

50MHz
70MHz
100MHz

70dB
69dB
66dB

0.55mW
1.1mW
2.2mW

8-9
CHUNG-YU WU

V DD = +3V ; VCC = 3V ; CL=1pF

2.Low output resistance CMOS OP AMP
* C L is a compensation capacitor
*For low-resistance load
*Smaller maximum output voltage swing.
* I B1 = 50 A, C L = 1 pF , f u = 60MHz

+VDD
M8

M9
M6

M5

M17
M22

M13

M14

M18
M15

M7

M1

OUTPUT
CL

M2

M16

M12

INPUT

M19
IB1

M21

M11

M3
M4

M10

M20
-Vcc

8-3 Advanced Design Techniques on High-drive MOS Power or Buffer OP AMPs

8-3.1 Efficient Output Stages.
A. CMOS output stage using a biplar emitter follower and a low-threshold PMOS
source follower.

+ VDD
VBIAS

Vout

Vin

- VSS

8 - 10
CHUNG-YU WU

B. Complementary class B output stage using compound devices with

common-source output MOS.
+ VDD

MP
A

Vout

Vi
A

MN

- VSS

8-3.2 High-drive power or buffer CMOS OP AMPs

1. Large swing CMOS power amplifier (National Semiconductor)
+ V DD
M6

M16

C0

M8

M17

V OUT

M8A

M10

VBIASN

M9

A1

V IN

A2

M13

VBIASN

M12
M6A

-VSS

M11

8 - 11
*

CHUNG-YU WU

Noninverting unity gain amplifier

Vout
+

Vi

A1

M6

~
+ V DD

Vin V out
M 6 provides the negative feedback
A1 , M 6 and A2 , M 6 A form a class AB push-pull output stage.

Full swing from + VDD to V SS

M 9 , M 10 , M 11 , and M 12 form a current feedback to stablize the bias current

of M 6 and M 6 A .
Offset in A1 ,e.g. VinA1 VoutA1 I DM 6 and I DM 9 I DM 11
and

I DM12 VGSM 8 A

VinA 2 +

and

Vout ,

i.e.

VinA1 + Vout VinA1 (virtual short between + and -) VinA 2

througt M 8 All the bias voltage and current are restored to the normal
values and the offset is absorbed by M 8 A .
Since the current feedback is not unity gain ,some current variation in
transistors M 6 and M 6 A still exists.

VCC
M4

M3

M6
MPC
CC

VIN
M1

VSS

M2

VBIASN
M5
VSS

VOUT

8 - 12
CHUNG-YU WU

Large positive common mode range allows M 6 to source large amount of

current to the load. (because Vin V out )
The maximum VGS 6 which M 1 and M 2 still in the saturation region is

VGS 6 max = ( VDD ( VIN VGS 1 + VDSAT 1 )) = ( VCC VIN + VTH 1 )

VTH 1 VGS 6 max I DM 6
(1). Threshold implant to increase

VTHO1

(2). Negative substrate bias V SS to increase

VTH 1

+ VCC
MP3A

M3H
M4H
VIN

M16

M3

MP5

M4
MP3

C0

M9

M6
M8A

MRC
CC

M1

MRF

CF

M2

MP4A

M10

MN4
M5

M2A

M1A

MN3A

M8

M17

V BIASP

M5A

MP4

MN3

M5A
M13

M12 M11

MN5A
MN4A

M4A
M4HA

M3A
M3HA

V BIASN
- VSS
V OUT

The input stage is not shown in the diagram.

M 16 , M 8 , M 17 form the second stage with C D the Miller compensation

capacitor.

If Vout V SS , VDSM 5 0 and I DSM 5 0.

M 1 , M 2 , M 3 and M 4 are off
M 3 H and M 4 H are still on to keep VGS 6 0V .
Otherwise , M 6 will be turned on.
Similarly, M 3HA and M 4 HA turn off M 6 A in the positive voltage swing

M P 3 , M N 3 , M N 4 , M P 4 and M P 5 are output short-circuit protection circuitry.

Normally, M P 5 is off.

88- -13
14
CHUNG-YU
CHUNG-YU
WU
WU

When I DM 6 60mA, I DMP3 I DMN 4 VGSMP5 .

I DM 6 is limited to approximately 60 mA.
Table I
POWER AMPLIFIER PREFORMANCE
Parameter

Simulation

Power dissipation( 5V )
Avol
Fu
Voffset
PSRR+(dc)
(1KHz)
PSRR-(dc)
(1KHz)
THD VIN=3.3Vp RL=300
CL=1000 pF
VIN=4.0Vp RL=15 k
CL=200 pF
Tsettling (0.1%)
Slew rate
1/f noise at 1KHz
Broad-band noise
Die area

7.0mW
82dB
500KHz
0.4mV
85dB
81dB
104dB
98dB
0.03%
0.08%
0.05%
0.16%
3.0us
0.8V/us
N/A
N/A

TABLE II
COMPONENT SIZES ( m, pF )

Measured
Results
5.0mW
83dB
420KHz
1mV
86dB
80dB
106dB
98dB
0.13%(1KHz)
0.32%(4KHz)
0.13%(1KHz)
0.20%(4KHz)
<5.0us
0.6V/us
130nV/Hz
49nV/Hz
1500mils2

MI6
MI7
M8
M1,M2
M3,M4
M3H,M4H
M5
M6
MRC
CC
M1A,M2A
M3A,M4A
M3HA,M4HA
M5A
M6A
MRF
CF

184/9
66/12
184/6
36/10
194/6
16/12
145/12
2647/6
48/10
11.0
88/12
196/6
10/12
229/12
2420/6
25/12
10.0

M8A
M13
M9
M10
M11
M12
MP3
MN3
MP4
MN4
MP5
MN3A
MP3A
MN4A
MP4A
MN5A

481/6
66/12
27/6
6/22
14/6
140/6
8/6
244/6
43/12
12/6
6/6
6/6
337/6
24/12
20/12
6/6

Maximum loads : 300 and 1000pF to ground.

Ref.:IEEE JSSC , vol.SC-18 , pp.624-629 , Dec.1983
2. High-performance CMOS power amplifier (Siemens AG)
(1). New input stage : 3 gain stages.
+ VDD
BIAS

M5

M10

M11
M13

M1

M2

M8

M9
CC
M7

M3

M4

M6

M12

- VSS

Cc is connected to the source of M9 to improve PSRR

8 - 15
*

CHUNG-YU WU

Three poles and one zero :

Z=

2 g m 6 g m8 g m13
C c g m6 g m13 + C 1 g m8 g m12

P1

g ds10 g o
g m13C c

LHP.

2
g g
g m8 (C O + C C )
g m8 (C c + C O )
m8 m13

P2 , P3
j

2C O C c
2
C
C
C O C1

O c

where

g o g ds12 + g ds13
C O = C L + C db12 + C db13
C1 = C gs13 + C db11 + C db 9 + C gd 9

Design guidelines for stability :

g m8 large , g m13 >> g m 6
(2).

Output stage
+ VDD
VBIAS

Vout

Vin

- VSS

Class AB source follower

*

One pole and one zero at high frequencies.

Not full swing

1/ 2

8 - 16
8 - 17WU
CHUNG-YU
CHUNG-YU WU
+ V DD
A1

M1

Vin

Vout

A
- 2

M2

- VSS

Pseudo source follower

*

The quiescent current in M1 and M2 will vary widely with variations in

Vos1 and Vos2.

Suitable common-mode range of the two amplifiers A1 and A2 are

required.

Large phase shift at high frequencies due to A1 and A2 stability

problem.

Combined output stage:

*

M1 and M2 are turned off in the quiescent state by building a small offset
voltage into A1 and A2 M3-M6 control the output quiescent currents.

M2 (M1) sinks (sources) approximately 95% of the required currents.

M1 and M2 provide a high-frequency feed-forward path.

+ VDD
BIAS
Vos

-AMP 1

M15

+
error amp.

M3

M5

M4

M6
Vos

VIN

+
AMP 2

M17

error amp.

- VSS

Still has a smaller swing limited by M5, M6 .

8 - 18
CHUNG-YU WU
+ VDD
M4

M6
M15

M13

M1

Vout

M2

M7

M14

M15

CC
M8

M5
- VSS

M13, M14 and M15 form a circuit to turn off M15 when Vout < VTP13
(negative)

Cc : compensation.

Three poles and one zeros.

Z1

P1

g m7 + g mbs 7
Cc + Cgs 7
gL

C L + CC

g m15
g ds 6
1

2
g m 7 g ds6 (C L + Cc m15 )
2

g (C + C L )
g (C + CL )
g ds 6

j
m 7 c
P2 , P3 m 7 c
2Cc C L
C cC L C1
2C cC L

C1 = C gs 9 + Cdb 6 + Cdb 7 + C gd 7

where

8 - 19
+ V DD

CHUNG-YU WU
M L7

ML3

BIAS4

C C3

M5
M10

M L10

M11

ML11
M L6

BIAS3

M12

M H4

MH5

M15
M1

M2

M14
M L1

M L9
M8

M9

ML2

MH8

CC1
M H9

MH1

M H2
ML8

M16

M 17

M7
MH10
M3

M4

M6

MH6

BIAS2

M 13

MH11

BIAS1

M H3
- VSS

C C2
MH7

ML4

ML5

TABLE I Component Sizes

M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17

400/15
400/15
150/10
150/10
100/15
150/10
150/10
300/5
300/5
300/10
300/10
1200/10
600/10
200/5
200/5
600/6
600/6

MH1
MH2
MH3
MH4
MH5
MH6
MH7
MH8
MH9
MH10
MH11
Cc1
Cc2
Cc3

48/10
50/10
500/15
300/6
300/6
200/5
250/15
700/6
15/6
10/15
20/15
20pf
4pf
4pf

ML1
ML2
ML3
ML4
ML5
ML6
ML7
ML8
ML9
ML10
ML11

48/6
50/6
300/15
150/5
100/5
300/6
100/15
400/5
5/5
5/15
15/15

8 - 20
TABLE II
POWER AMPLIFIER PERFORMANCE SUMMARY
(First Revision)
parameter

Measured Results

Supplies

5V

Open-Loop Gain

93dB

Bandwidth

1.2MHz

Power Dissipation

12.7 mW
1.76mW

Output Swing (RL=200)

3.1V

PSRR+ at DC

93dB

PSRR-

kHz

91dB

10

kHz

76dB

100

kHz

60dB

at DC

102dB

kHz

89dB

10

kHz

75dB

100

kHz

53dB

Slew Rate
Input Common Mode Range

1.5V/s
+3.3V
-5.5V

Die Area (5m CMOS)

1000 mils2

Harmonic Distortion (3 kHz)

Vin=3 Vp
RL=200
HD2

-73dB

HD3

-78dB

Maximum Loads : 1000pF and 200 to ground.

Ref.: IEEE JSSC , vol. sc-20, pp.1200-1205, Dec. 1985.

CHUNG-YU WU

8 - 21
CHUNG-YU WU

3. Efficient Unity-gain CMOS buffer for driving large CL.

High-drive OTA buffer

Bias stage
+ V DD

VDD
MX5

MA1 M A4

MX1

MB1
A

V B1
Vin+

MA2 MA3

Vout

Vin-

M A5

M B2

VB1

M X2
MR1

V B2
V B3

MX7

MX3

CL
MX8

MR1
V B2

M B3
VB3

MX6

MB4

MX4

- VSS

V SS

TABLE I
TRANSISTORS DIMENSIONS
TRANSISTOR
MX1, MX5

W (m)
225

L (m)
3

MX2
MX3
MX4, MX6
MR1
MA1, MA4
MA2, MA3
MA5
MX7
MX8

75
30
90
6
45
450
36
600
240

3
3
3
21
3
3
3
3
3

MR1 has a low W/L and is operated in the linear region

like a linear resistor.

MX2 and MX3

Quiescent operation:
MX2 and MX3 are on.

Keep VGSMX7 and VGSMX8 low to reduce dc power.

8 - 22
Provide a low-impedance level at node A and B. CHUNG-YU WU
The low-order poles created by the Miller cap. of MX7 and MX8 can be
avoid
*

If Vin << 0
MX3-MX6 are turned off and MX1 and MX2 are on
Node A has a high voltage MX7 off.
VB = VA because of MR1 MX8 on.

In the bias circuit, MR2 MR1, MB1 MX1, MB2 MX2, MB3 MX3, MB4
MX4.
In the quiescent case, VGSMX1 VGSMX7 and VGSMX4 VGSMX8
The current in MB1 and MB4 controls that in MX1 and MX4 and MX7 and MX8.

RBIAS controls the current through MB2 and MB3.

i.e. the current through MX2 and MX3.

Characteristics:
3 m CMOS area: 100mils2.
CL 100pF and RL 10 k

: stable.

CL=5000pF f 100kHz.

TABLE II
BUFFERS PERFORMANCE
PARAMETER

MEASURED VALUE

SPICE

Supply Voltage

2.5 V

2.5 V

Supply Current
Voffset
Voltage Gain
F3dB (CL=100pF)
Gain Peaking
RoCL
CMRR
Input CM Range
SR (CL=5nF)

285 A
< 10 mV
+ 1.00 V/V
6 MHz
0.4 dB

270 A
5 mV
+ 1.00 V/V
8 MHz
0

330
80 dB

270
84 dB

1.8 V
0.9 V/s

1.7 V
1.0 V/s

Tsettling (to 1%)

3.9 s

4 s

8 - 23
CHUNG-YU WU

Input Noise Density

F = 1 kHz

NA

270 V / H Z

F = 50 kHz

NA

70 V / H Z

Ref.: IEEE JSSC, vol. sc-21, pp.464-469, June 1986.

8-4 Advanced Design Techniques on Fully differential type CMOS OP AMPs

1.

Low-noise chopper-stabilized OP AMP

Techniques for the reduction of 1/f noise:
1) Use large device geometries.
Possibly too large chip area.
2) Use buried channel devices
Not a standard technology.
3) Transform the noise to a higher frequency range
So that it does not contarninate the signal.
a. The correlated double sampling (CDS) method
b. The chopper stabilization method

a. CDS method

VIN

Vn 2

Vn2
+

VOUT

S/H
f
V neq12
VIN

V neq12

VOUT

Noise reduction

b. Chopper stabilization method

8 - 24
CHUNG-YU WU

Vn2

SIN

+1
f

-1

f
Vn2
+

VIN

a1

a2

VOUT

Signal
f

Noise

Vneq 2
+

VIN

a1

a2

VOUT

Vneq 2

If the chopper frequency is much higher than the signal bandwidth, the 1/f
noise in the signal band will be greatly reduced.

Example: Fully differential class AB chopper stabilized OP AMP with DCMFB circuit.
Major advantage of fully differential OP AMPs:
1. Improvement of PSRR
2. Improvement of dynamic range
3. double the output swing
4. Reduction on the sensitivity to clock and supply noise.

Disadvantage:

1. Larger area, mainly due to interconnection

2. Additional design complexity
3. Increase power dissipation.
+ V DD
Vcm+

M29

M9

M13

M25

M17
V+

M14

M10

M22

M21

M5

M43

M1

M2

M30

M18

M26

M44

M6

M46

M45
V-

Vo+

M7

M33

M3

M4

Vo-

M8
M48

M47

M39

M49

M35

M50

M53

C3

C2

M56

M55
M19

M41

M37

C4

M20

M28

M27

M24

M23
M31

M36

M54

C1

Vcm-

M40

M52

M51
V df

M34

M15

M16

M11 M12

M32

M38

M42

- VSS

M43-M46, M47-M54: the input chopper and the output chopper.

M29-M42, C1-C4 : DCMFB circuit

Device

W(um)

L(um)

Device

W(um)

L(um)

M1

25

M19

3.5

M2

25

M20

3.5

M3
M4

25
25

3
3

M21
M22

17.5
17.5

3.5
3.5

M5

25

M23

3.5

M6

25

M24

3.5

8 - 25
CHUNG-YU WU

M7

25

M25

3.5

3.5

M8

25

M26

3.5

3.5

8 - 26
CHUNG-YU WU

M9

10

3.5

M27

M10

10

3.5

M28

M11

3.5

M29

12

3.5

M12

3.5

M30

12

3.5

M13

17.5

3.5

M31

16

3.5

M14

17.5

3.5

M32

18

3.5

M15

3.5

M33-M34

M16

3.5

M55

M17

17.5

3.5

M56

M18

17.5

3.5

Ref: IEEE JSSC vol.sc-21, pp.57-64 Feb.1986

2.

Fully differential folded cascode amplifier(National Semiconductor)

For internal OP AMPs, high output impedance is O.K.
simple 2-stage or single-stage OP AMP.

+VDD
IO

IO

IO

CC
M2

Vin

+VDD

VBIAS

V
+ O
CL
-

CGS
Vin

M1
-VSS

CL

M2

M1

CP

-VSS

TWO-STAGE

SINGLE-STAGE
CASCODE

DOMINANT AND NONDOMINANT POLE LOCATIONS

FOR THE TWO-AND SINGLE-STAGE AMPLIFIERS
Dominant
pole location
Two-stage
amplifier
One-stage
amplifier

1
ro C c g m ro
1
ro C L g m ro

Nondominant
pole location
gm
CL
gm
Cp

In general, the higher the 2nd pole frequency, the faster the settling response.
Single-stage cascode amp. has a faster settling behavior.

+VDD

VBIAS

+
Vin

-V
out +

CL

CL

CMFB

-V SS
CMFB: Common-mode feedback circuitry

3.

High-performance micropower fully differential OP AMP.

Simplified schematic of the class AB amplifier:
A
M12

+VDD
M11

M17
M20

M14
BIAS3

BIAS1
M5

M1

M2

M6

Iin(+)

I in(-)

OUT(+)

OUT(-)
M7

M19
M18

M16

BIAS4

M8
M3

I1 I2

M4
I

I
M10

M9
A

BIAS2

M15
M13

-VSS

8 - 27
CHUNG-YU WU

+V DD
M17

M12
BIAS3

M20

I2

M5
M1

Iin(+)

M6

Iin (-)
OUT(-)

OUT(+)
4A

M4

M7

class AB

3A

class A

1A
-200

BIAS2

I2

2A

-400

M8

200mV 400mV

I
M9

V in

1A

M15
M13

2A

-VSS
Active portion of the amplifier for a positive input signal.

Detailed schematic of the entire amplifier without CMFB:

+V DD
M11
M23

M14

M12

M17
M20

M22

M27
M26
M5

M1

M2

Iin(+)

OUT(+)

M19

OUT(-)

M8

I2 I1
M3

M24

M6
Iin(-)

M7

M16

M4
M30

M15

M 60A
M18

M25
M10
M21

M13
M9
-VSS

8 - 28
CHUNG-YU WU

NMOS dynamically biased current mirror:

OUT

I30
M30

M 15
40
10

10
10

I9
M9

M 13

40
10

40
10

- VSS
If I 9 = I 30 , VGS 9 = VGS13 = VGS15
V DS13 = VGS 30 V GS9
Set VDG13 = VTH VGS 30 = 2VGS 9 VTH
Design (

W
)30 , such that VGS 30 = 2VGS 9 VTH
L

M 13 is always sat. at the edge of the linear region.

Output swing
*

Dynamic CMFB is used.

AMPLIFIER DEVICE SIZES

DEVICE

Z(m)

L(m)

M1

180

M2

180

M3

140

M4
M5

140
150

6
6

M6

150

M7

200

M8

200

M9

22

10

M10

22

10

8 - 29
CHUNG-YU WU

M11

29

M12

29

M13

22

10

M14

29

M15

22

M16

29

M17

29

M18

22

10

M19

22

M20

29

M21

20

M22

12

M23

28

M24

14

M25

20

M26

12

M27

28

M30

14

AMPLIFIER SPECIFICATIONS
CORE AMPLIFIER SPECIFICATIONS
(0-5 Volts Supply)
100W Quiescent Power Dissipation
DIFFERENTIAL GAIN

>10.000

UNITY GAIN FREQUENCY

2 MHz

NOISE
OUTPUT SWING

140 nV/ Hz 1KHz

50 nV/ Hz white
0.5 Volts from Supply

AREA

300 mils 2

inferred from filter measurement

Ref: IEEE JSSC, vol. SC-20, pp.1122-1132, Dec. 1985

8 - 30
CHUNG-YU WU

4.

Fully differential class AB OP AMP with CMFB circuit

+ VDD
M18

100A

M16

Vin -

MC1 MC2
Vout+

BIAS
M2

M8

MC5

M6

BIAS

MC7

M19
MC12 MC11
Vout-

M5
M3

M14

100A

Vin+

M1
M7

BIAS

MC6

M17

BIAS

M20

MC4

M15

5 A
M10

MC15 MC14

M4

BIAS
5 A

M9

M12

BIAS

M13
MC17

M11

- VSS

Characteristics:
Technology

: 5um, P-well CMOS, double-poly cap.

Open loop gian

: 1180

unity-gain freq

CMRR

: 61db

power consumption : 2.3mw

Area

: 290 mils2

power supply

Ref: IEEE JSSC ,vol.sc-20 , pp.1103-1112 , Ddec,1985

: 10Mhez

: 5V

MC16

8 - 31
CHUNG-YU WU

8-5 Recent Design Examples of CMOS OP AMPs

8-5.1 Fast-settling CMOS OP AMP for SC Circuit with 90-dB DC Gain
Reference : IEEE JSSC, vol.25, no.6, pp.1379-1384, Dec 1990.
1.Gain boosting
1)
Cascode gain stage with gain enhancement
+VDD

Vo
Vref

+
Aadd

Vi

Cload

M2

M1

-VSS
Rout = [g m 2 ro2 ( Aadd + 1) + 1]ro1 + ro 2
Atot = g m1ro1 [g m 2 ro 2 ( Aadd + 1) + 1]
Aorig = g m1 g m2 ro1ro 2
2) Repetitive implementation of gain enhancement
+VDD

Vo
M2

M1

M6

M4

M5

M3

Vi
-VSS
2.High-frequency behavior

M8

M7

8 - 32
CHUNG-YU WU

gain (log)
3 : Upper 3-dB frequency of Aorig

Atot

5 : Unity-gain frequency of Atot

2 : Upper 3-dB frequency of Aadd
4 : Unity-gain frequency of Aadd
1 : Upper 3-dB frequency of Atot

gain enhancement
= Aadd(0) +1

Aadd
Aorig

(log)
6
3 4

1 2

We want 5

Aorig

= 5

5 : Unity-gain frequency of Aorig

Atot

2 > 1 => The bandwidth is determined by 1, i.e. Rout and Cload.

=> 4 > 3
But 4 < 5 for easy design of Aadd.
Aadd and M2 forms a close loop with the dominant pole of 2 and the second pole at the
source of M2, i.e. 6
The stability consideration requires 4 < 6
=>The safe range of 4 is
3 < 4 < 6
* The repetitive usage of the gain-enhancement techniques yields a decoupling of the
op-amp gain and unity-gain frequency fu. That is:gain without fu .
3.Settling behavior
1. Total output impedance Ztot
Ztot= Z load // Z out
Zload: impedance of Cload
Zout: output impedance of the amplifier
Z load
g m1
Z tot
g m1

Zout Zorig (Add+1)

Normalized impedance
(log)

Z out
g m1

Z orig
g m1
Pole-zero
doublet

1 2

(log)

3 4 5

8 - 33
CHUNG-YU WU
2 : Upper-3dB freq. Of Aadd

the same for Z out

4 : Unity-gain freq. Of Aadd

For >

4 , Aadd < 1 Z out Z orig

A zero is formed at

4 for Z out

Z total = Z load || Z out A pole-zero doublet is formed around

The same doublet of Atotal

3. Design technique for fast settling
The time constant of the doublet,
constant,

1
, must be smaller than the main close-loop time
PZ

1
. where is the feedback factor.
unity

The safe range for the

4 .

gain (log)

Aaddd

1/

Aclosed-loop

4 5 6
(log)

Safe range for 4

5 < 4 < 6
doublet

4. CMOS OP AMP circuit

8 - 34
CHUNG-YU WU

+VDD

Vbp1

Vbp1

Vcm
Vin-

Vin+

Ib
Vout+

Vbn1

Vout-

Vbn1

-VSS
MAIN CHARACTERISTICS OF THE OP AMP
Gain enh.

on

Off

DC-gain
Unity-gain freq.
Load cap.
Phase margin
Power cons.
Output-swing
Supply voltage
Settling time
0.1% , V o = 1V

90dB
116MHz
16pF
64deg.
52mW
4.2V
5.0V
61.5ns

46dB
120MHz
16pF
63deg
45mW
4.2V
5.0V
-

8-5.2 1V Rail-to-Rail CMOS OP AMPs

Ref.: IEEE JSSC vol.35, no.1, pp.33-44 Jan. 2000

8 - 35
CHUNG-YU WU

1. Typical input stage for rail-to-rail amplifiers

* Parallel-connected complementary
* Operating zones for low VDD/VSS
differential pairs.

* Operating zones for extremely low

VDD/VSS

Dead region.
Both pairs are off.

2. Dynamic level-shifting current generator

Vi,n,cm=Vi,cm+IR
Vi,p,cm=Vi,cmi-IR

* The input resistance over the entire voltage range is infinite and no loading effect or
input current over the previous stage.
Usually mismatches cause negligible input current.
* The symmetrical topology ensures very high CMRR
1 R Gm 1
CMRR =
(
+
)
RG m R
Gm
where Gm = I / Vi ,cm

8 - 36
CHUNG-YU WU

Circuit implementation

3. Rail-to-rail very LV CMOS OP AMP with input dynamic level-shifting circuit

MAIN TRANSISTOR ASPECT RATIOS (IN m) AND ELEMENT VALUES OF THE

AMPLIFIER BASED ON COMPLEMENTARY PAIRS
M1A,M1B
M2A,M2B
M1,M2
M3,M4
M5-M8
M9-M12

400/5
200/5
400/2
200/2
400/5
500/5

M15
R1-R4
RM
CM

700/2
30 K
5 K
10pF

I bn = I bp

10A
40A

Io

8 - 37
CHUNG-YU WU

4. Input CM adapter

Vx = A[2Vref - (Vi,p + Vi,p )]

-

= 2A(Vref Vi,p,cm )
I = G m Vx
=> Vi,p,cm Vref +

Vi,cm
2RGmA

Vi,p,dm = Vi,dm

*Vi ,cm is degraded by A and Vi , p ,cm V ref

Circuit implementation:

5. Very LV CMOS OP AMP with a single differential pair and the input CM adapter.

8 - 38
CHUNG-YU WU

Main transistor ratios(in m) and element values of the amplifier based on a single input pair
M1A M1B
1000/6
M6
1600/2
M2A M2B

600/4

M7-M10

300/4

MA1-MA4

50/2

M11

700/2

MA5-MA6

300/4

R1-R2

15K

M2D

150/2

RM

M1,M2
M3-M5

200/2
400/2

CM
Is=Ir/2

5K
5pF
10A

6.Measured results
Experimental performance of amplifiers(Vsupply=1V,technology:1.2m CMOS, CL=15pF)
Parameter
Dynamic-shifting amp
CM adapater amp
Ido(supply current)

0.81mm 2
410uA

0.26 mm 2
208uA

DC gain
unity-gain frequency

87dB
1.9Mhz

70.5dB
2.1Mhz

Phase margin

61

73

SR+
SR-

0.8V/us
1V/us

0.9V/us
1.7V/us

THD(0.5Vpp@1kHz)
THD(0.5Vpp@40kHz

-54dB
-32dB

-77dB
-57dB

Vni(@1KHz)
Vni(@10KHz)
Vni(@1MHz)

267nV/ Hz
91nV/ Hz
74nV/ Hz
62dB
-54.4dB
-52.1dB

359nV/ Hz
171nV/ Hz
82nV/ Hz
58dB
-56.7dB
-51.5dB

Active die area

CMRR
PSRR+
PSRR-

8-5.3 1.5V High Drive Capability CMOS OP AMP

Ref.: IEEE JSSC vol.34, no.2, pp. 248-252, Feb. 1999

8 - 39
CHUNG-YU WU

+VDD
1. Folded-mirror differential input stage

VCM VGS 6, 7 + VTHn = 2VTHn + V6, 7

VBIAS2

M3

M4
OUT

VCM VDSsat 5 + VGS 1, 2 = 2VTHn + V5 + V1, 2

CMR = VTHn V5
V : overdrive voltage.

IN+

M1

M2

IN-

VBIAS1

M7
M5
M6
CMR is independent of supply voltage.
For VDD=1.5V , CMR=0.6 ~ 0.7V
-VSS
CMR of the conventional NMOS-input differential pair is 0.3-0.5V
2. Output Stage
+VDD

IB1

M6A M8A

M1A M3A

IB2

OUT

IN

M4A

M5A M7A

M2A

-VSS
Input section : M1A-M4A , IB1 , IB2
Output section: M5A-M6A and M7A-M8A
M5A, M8A sat
M6A, M7A off.
For low input levels , M6A and M7A off Class A operation.
For large positive input signals,
ID1A=IB1 M3A and M5A OFF
VA -VSS
M6A is turned on to supply most of the output current.
But M7A remains cutoff.
The current of M8A is increased.
For large negative input signals, M7A supplies most of the output current.
(W/L) 5A,8A << (W/L) 6A,7A for low dc power dissipation and high drive.

8 - 40
CHUNG-YU WU

3. Overall LV CMOS OP AMP.

+VDD
M15

IBIAS

M3

M6

M7

M6A M8A

M18

M12

M4A M11

M8

INM14

CC3A

M1 M2

M4

M5

M9

M16

CC3B

CC1

MC CC2

IN+

OUT

M5A M7A

M1A

M13

M2A

M3A

-VSS

Dominant pole : Wp1

1
ro5,7{(gm8 ro8,9 )2[gm5A,8A(ro5A || ro8A )]}Cc

Gain-bandwidth product: WGBW

g m1, 2
C c1

Hybrid nested Miller compensation: CC1, CC2, CC3A,B

The inner amplifier M8,M9,M1A~M8A contributes the nondominant poles.
* The two-stage OP AMP M1~M9 has a gain-bandwidth product of
g m1,2

and the gain of

g m1,2
sCc 1

sCc 2

g m1, 2
Cc 2

at high frequency. The gain of M1-M7 at high frequency is

. Thus the gain of the gain stage M8 and M9 is approximately equal to

* The open-loop gain of the inner amplifier is

C g
Ain C 1 m1 A, 2 A 2 g m 5 A, 8 A (ro 5 A ro8 A )
CC 2 g m3 A , 4 A
Dominant pole : P1in
Second pole : P 2in

g m3 A ,4 A
g m5 A,8 A (ro 5 A || ro8 A )C C 3 A, B

2 g m5 A, 8 A
CL

CC1
.
CC 2

8 - 41
CHUNG-YU WU

C g
Gain-bandwidth product : GBWin 2 C1 m1A , 2 A
C C 2 C C 3 A, B
or the second pole of the
whole amplifier
Design consideration :
To obtain a maximally flat Butterworth response without gain peaking, we have the
unity-gain frequency equal to one half of the second-pole frequency.
GBWin = uin =

1
P 2 in
2

1
1
GBW = u = uin = GBWin
2
2
Reference : IEEE JSSC, vol.27, pp.1709-1716, Dec. 1992.
Setting 2C C 3 A, B = C C 2 , we have
C C1 = 2

g m1, 2
g m5 A,8 A

CL

C C 2 = 2C C 3 A, B = 2 g m1, 2 g m1 A, 2 A

CL
g m5 A,8 A

Component values :
M1,M2,M3,M9,M1A,M2A,M10

60/2

M4,M5,M11,M12,M13

20/2

M6,M7

15/2

M8
M3A

90/2
5/1.2

M4A

15/1.2

M5A

30/1.2

M7A

120/1.2

M6A

360/1.2

M8A
M14,M16

90/1.2
10/1.2

M15,MC

30/2

CC1

4pF

CC2

6pF

CC3A,CC3B

2pF

IBIAS
VTH

5uA
0.8V

8 - 42
CHUNG-YU WU

Experimental results:
MEASURED MAIN PERFORMANCE
Open-Loop Gain

68dB

GBW

1MHz

Phase Margin

65o
16dB
400ns
1 V/s

Gain Margin
Settling Time(0.1%), V = 200mV

Slew Rate
THD@1kHz Vout = 0.5V RL=500 -57dB
Closed-Loop Gain=20dB
PSRR+@1kHz

75dB

PSRR- @1kHz

75dB

CMRR @1kHz
Offset

95dB
< 8mv
280W

Power Dissipation
Technology

0.08 mm 2
1.2m CMOS

Loading

50pF || 500

Die Size

9-1
CHUNG-YU WU

Chapter 9 Passive Components and Switches

9-1 Resistors
1. Source/Drain diffused resistor
Thermal oxide

Metal

n+
p

* Compatible with NMOS and CMOS. metal-gate and Si-gate

techniologies.
* R = 20 ~ 100 / ( 100K max)
* Temperature Coefficient of Resistance (TCR) = 500~1500
ppm/oC.
Voltage Coefficient of Resistance (VCR)=100~500ppm/ oC
Tolerance= 20% (Absolute)
* High parasitic capacitance (n+-p junction cap.)
Piezoresistance error. (Because of shallow junction)
2. P-well (N-well) diffused resistor (Well or tub resistor)
Thermal oxide

p+

n+

Metal

p+

p
n

* Compatible with CMOS metal-gate or Si-gate technology.

* R= 1K ~ 5K /
Large VCR

9-2
Tolarance= 40% (absolute)
* Large depth and lateral
spreading narrow resistors are impossible.
3. Implanted resistor

CHUNG-YU WU

( metal-gate technology )
CVD SiO2

SiO2
n+

n+
Implanted N+
p-sub

* Compatible with NMOS and CMOS, metal-gate and Si-gate

technologies.
* Need an additional masking step.
* R> 500 ~ 1000 / ; can be accurately controlled.
* Higher VCR ; smaller tolerance.
* Difficult to eliminate the piezoresistance effect.
* The resistor implant can be combined with the depletion
implant.
4. Poly-Si resistor
Vapor-deposited oxide
Poly Si I or II

Metal

Field oxide

* Realizable by NMOS and CMOS Si-gate technologies.

* R = 30 ~ 200 / (doped with the source/drain
diffusion)
* TCR 500~1500 ppm/oC ; Tolerance= 40%

9-3
CHUNG-YU WU

* Can be trimmed by laser or poly fuse.

* Fully isolated with smaller parasitic capacitance.

Version I :Poly-I resistor

Version II:Poly-II resistor

Version III :Poly-I and Poly-II distributed RC structure
(please see the structure shown in poly to poly
capacitor)
5. Switched-capacitor simulated resistor
* Realizable by NMOS and CMOS , metal-gate and Sigate
technologies.
* High frequency operation?

i
V1

i=

R
V1 V2
R

V2

V1

V2

f C is the clock frequency of or

i=

C (V1 V2 )
,
T

R=

T
1
=
C fC C

6. Thin-film resistor
* Realizable by NMOS and CMOS, metal-gate and Si-gate
technologies.
* Need additional process steps.
* Si-Chromium resistor or Mo resistor.
* Laser trimming is possible.
* Non-conventional material may be involved.
9-2 Capacitors
1. PN junction capacitor
* Well known and understood.
* Nonlinear capacitance with a large VCR.

9-4
CHUNG-YU WU

* Compatible with all MOS technologies.

2. MOS capacitor
metal

thin oxide
p+
P-sub

* Realizable only by NMOS and

technology.
* TC=25 ppm/oC
Tolerance=15%
VC=25ppm/V
* Voltage-dependent capacitance
accumulation
depletion
Co
(Co-1 Cd-1)-1
3. Poly (or metal ) to bulk silicon capacitor
Poly Si

CMOS

metal-gate

Metal

n+

n+
Heavy n+ implant

Thin thermal oxide

P

* Realizable by NMOS and CMOS poly-Si-gate (metal-gate )

technologies.
* Need an extra mask to define the heavy n+ implant as the
bottom plate.
* Can be trimmed by laser on poly-fuse.
( Poly-fuse : blown with 10-20mA )
* Bottom plate pn junction parasitic capacitance ( 15% 30% )
* VC of the capacitor -10ppm/V

9-5
o

* TC 20-50 ppm/ C
* Tolerance 15%
4. Poly to field implant region capacitor

CHUNG-YU WU

poly-Si

field oxide
p+

n+

substrate
p-sub

* Realizable only by NMOS and CMOS Si-gate technologies

with the field implant.
* Smaller oxide capacitance per unit area
Thick field oxide
* The capacitors bottom plate must be always connected to
the substrate.
* Low quality dielectric oxide.
5. Metal to poly capacitor
metal
poly oxide

poly

CThick

CB

Thick oxide

P-sub

*
*
*
*
*

Realizable by NMOS and CMOS Si-gate technologies.

Interdielectric is poly-oxide.
Extra mask to define the ploy-oxide pattern.
Poly fuse trimming is possible.
CVD oxide is not good as capacitor dielectric

9-6
CHUNG-YU WU

hysteresis in Q-V due to dielectric changing and

relaxation.
* For reliability consideration, the
top metal layer must be larger than
the poly oxide layer.
CThick exists
parasitic capacitance
* VC=100ppm/v, TC=100ppm/oC
6. poly to poly capacitor
Vapor

deposited
oxides

Poly 1

Co

CThick
CB
poly to substrate
parasitic cap.

Thin thermal
oxide
Poly 2

Field oxide
P

* Realizable by NMOS and CMOS double-poly technologies.

* VC=100ppm/v
TC=100ppm/ oC
* Double-poly
EPROM or E 2 PROM are available
may be applied in trimming
* The poly2 area may be smaller than the poly-oxide area
small CThick
General Reference: D. J. Allstot and W. C Black, Jr., IEEE Proc.
vol-71, pp967-986, 1983.
9-3 Tolerance Considerations.
Resistors : Absolute tolerance 20% ~ 40%
Matching or ratio tolerance 0.1% ~ 10%
Capacitors: Absolute tolerance 15%

Co
CB

9-7
Matching or ratio tolerance 0.01% ~ 1%

CHUNG-YU WU

Resistors :
L
R L Rs L W
,
=

W
R
L
Rs
L
W
L
R W
If L is large
0

L
R
W
R = Rs

1/ 2

2 L 2 W 2 Xt 2
L
+ +
R=
, R =
+

Xt W
L W Xt
W
=
for
long
resistor
W
* Long resistor pattern is recommended in precise resistors.
Capacitors:

C W L si02 t ox
C = sio 2 WL
=
+
+

t ox
C
W
L
sio 2
t ox
edge effect Oxide effect
CASE I : Absolute tolerance
C W L
=
+
(if W and L are small or sio 2 and tox are
C
W
L
neglible)
If W and L are independent with l = w = l
C = l
C

1
1
+
(random variation)
W 2 L2

Assume L=W=d , C =
C

C
C

square( L=W )

2 l
is minimum
d

< C

non square( W L )

For the same WL ,minimum perimeter leads to minimum

telerance.
Circular shape?
CASEII : Ratio or Matching tolerance under geometry random
variation

9-8

C1 W1 L1
d dC1 dC2
=
,
=

C2 W2 L2

C1
C2

d = dc + dc
2

c1

2
2

c2

For W2=L2=d, d

=2

min

= l

= l
d

CHUNG-YU WU

1
1
1
1
2 +
2 +
2 +
2
L1 W1
L2 W2
L + W1
2+ 1
( d )2
2

l
if L1 = W1 = d
d

(1)

square versus square

CASE III : Ratio tolerance under the uniform undercut effect
Uniform undercut is not a random variation.

L2=d

W2=d

W1
L1

actual =

C1 W1 L1
= 2
C2
d

W1 L1 P1x + 4x 2 W1 L1 P1x
2
d 2 P2 x + 4 x2
d P2 x

x
P
2 ( P2 1 )

P
2( W1 + L1 )
IF P2 = 1 0 i.e. 4d =

So

2( W1 + L1 ) = 4 d

W1 L1 = d 2

W1 = d( 2 ) L1 = d ( + 2 )
d =

l
2 >>1 l
6

6
d

If = 1 , both conditions(1) and (2) can be satisfied

Ratio tolerance

(2)

9-9
CASE IV : Ratio tolerance under edge and oxide effects
Take = 1 unit capacitor array
D

CHUNG-YU WU

C1
=4
C2

D
C2

D
D

C1
D

: Dummy capacitor
pattern

* Centralized structure to avoid the oxide effect.

* Dummy capacitor may be omitted to save area.
* Ratio tolerance can be 0.06 %
Similarly, for resistors, we have

R1
dummy
resistor

R2

R1

R2
dummy
resistor

* Ratio tolerance can be 0.25 %

9-4 The MOS Switch
1. The NMOS switch
1) If VV1+VTHN , MN on V2=V1 full transimission

9 - 10
CHUNG-YU WU

V
Mn
1
V1

2
V2
VBS

Example:
V1= 0V, V= 3V V2= 0
V1= 5V, V= 8V, VTN =1.5V V2= 5V
2) If V1 + VTHN > V > VTHN , M N on
V 2 = V VTHN
Example: V = 5V , V1 = 5V , VTHN = 1.5V (under substrate
bias), VBS = 0V
V2 = 3.5V
3) If V < VTHN , M N off
Node 1 or 2 may be floating
V1 or V2 will be gradually charged or discharged by the
leakage current in MOS or PN junctions.
V

n+
A

If V = 0V for a very long time, V A 0V by the n + p

junction leakage current Not allowable in circuit design
* When the switch is turned on or off, the charging or
discharging current is nonlinear Nonlinear resistor
Capacitance feedthrough effect:

9 - 11
CHUNG-YU WU

Cgs

Cgd

C1

C2

Vout

V : VDD 0
V1 f V1i VDD

Cgs
Cgs + C1

V2 f V2 i VDD

C gd
Cgd + C1

error voltage
Example: C gd 0.02PF, C 2 = 2 PF, VDD = 10V , error voltage 0.1V
Compensation circuit:

1
2. The PMOS switch

V
1

VDD

* Can pass high voltage without offset.

Example: V = 0V , VDD = 5V = V1
V2 = 5V Q 1 = source and

VGS = 5V

9 - 12
* Cant pass low voltage completely.

CHUNG-YU WU

Example: V = 0V , V 2 i = 5V , V1 = 0V , VTP = 1.5V

V2 f 1.5V 0V
3. The CMOS switch
V

VDD

* Full transmission
* The clock feedthrough effect can be greatly compensated, if
the delay between V and V is zero.

* Nonlinear Cgs and Cgd and the delay between V and

V make the compensation of the feedthrough effect quite

complicated.
* If V1 = 5V = V ,V = 0V ,VDD = 5V ,VTN =| VTP |= 1.5V
_

V 2 = 0V V2 = 5V 1.5V = 3.5V : NMOS and PMOS

V2 = 3.5V V2 = 5V : Only PMOS
If V1=0V, V2i=5V
V2 = 5V V 2 = 1 .5V : NMOS and PMOS

V 2 = 1.5V V 2 = 0V : Only NMOS

10 - 1
CHUNG-YU WU

Chapter 10 CMOS Bandgap References

10-1 Basic Principles of Bandgap References (BGR)
VBE ( on ) = mV therm ln( I1 / I S )
I S = qAn i 2 Dn / QB

I S : Reverse saturation current of a BJT

= Bn i 2 D

A : Area of a BJT

= B ' ni 2T

QB : Base minority carrier charges

where B and B ' are

constants, indep. of T.

D : Average diffusivity of carriers

= CT n

C:Constant, indep. of T.
n:Temp. exponent.

ni 2 = ET 3 exp( VGO / Vtherm )

E : Constant, indep. of T.
VGO : Energy gap.

VBE ( on) = mV therm ln[ I 1T F exp(VGO / Vtherm )]

F : Constant , indep. of T.
=4n
I1 = GT

where I1 is the collector current and

G is a temp.-indep. constant.

V BE (on ) = VGO Vtherm [( ) ln T ln( FG )]

In general, the output voltage Vout is a sum of V BE (on ) , and KVtherm with a
weighting factor K such that Vout is nearly indep. of T.
V BE (on ) + KV therm = V out = VGO mV therm ( ) ln T + mV therm [ K + ln( FG )] (1)

dVout
dT

=0=
T =TO

mV thermo
[K + ln( FG )] mVthermo ( ) ln TO mVthermo ( ) + d VGO
TO
TO
TO
dT

TO
d

K + ln( FG ) = ( ) ln TO + ( )
VGO
..(2)
dT
mVthermo
Substituting (2) into (1) , we have

Vout

10 - 2

T
d
= V GO + mVtherm ( )(1 + ln O ) T
V GO
T
dT

CHUNG-YU WU

7.02 10 4 T 2
T + 1108

VGO = 1.16

14.04 10 4 TO (TO + 1108) 7.02 10 4 TO 2

d
V
=
dT GO T =T
(TO + 1108) 2
O

14.04 10 4 TO 7.02 10 4 TO
=
+
TO + 1108
(TO + 1108) 2

7.02 10 4 T 2
TO
) + 1.16

T
T + 1108
14.04 10 4 TOT 7.02 10 4 TO2 T
+
(TO + 1108) 2
TO + 1108

Vout = mV therm ( )(1 + ln

If = 3.2, m = 1, = 1, TO = 25 O C
Vout (T ) T =25

= 1.16 + 2.2(0.0259)

21.06 10 4 (298) 2 7.02 10 4 (298) 2

+
298 + 1108
( 298 + 1108) 2

= 1.093V

10-2 Bipolar Bandgap Reference

Widlar bandgap reference
*Feedback element Q4 is used to force Q3 on.

+Vcc

* Q4 also serves as a start-up circuit.

*Vout = I 2 R2 + V BE 3
I2 = I3
if I B 2 = I B 3

Q4

I3 =

I
I
V BE 1 V BE 2
1
=
mVtherm ln( 1 ) + ln( S 2 )
R3
R3
I S1
I2

R1 I2

I1

R2>>R1
+

I
+ ln S 2

I S1

Vtherm

+
-

VBE1

I1 / I 2 = R2 / R1 If V BE1 = V BE 3
Adjust R2 / R3 , R2 / R1 and I S 2 / I S 1 to give a suitable K
And Keep I I 2 to obtain I B 2 I B 3 and

Q3 Vout

Q2 VBE3-

Q1
R R
Vout = V BE 3 + 2 mln 2
R3 R1

R2

VBE2
-

R3

I3

I S 3 I3
=
to obtain V BE1 = V BE 3 .
I S1 I 1

10 - 3
CHUNG-YU WU

V2
R2>> R1

R1

R2
VBE(on)

V1

+
Q1

Q2

3
ON State

V2
Cut-in State

R3
-

The operating point 4 is the

V1

desired operating point

=>Need a start-up circuit.

10-3

CMOS Real Bandgap Reference (BGR)

10-3.1 CMOS BGR via BJTs and Resistors

Version 1:
N-well CMOS, positive VREF

R1

I2
R2
- Vos+

I1

Version 2:
N-well CMOS, Negative VREF

R1

I1

I2

R2

-Vos +

+
CMOS

R3

VREF
R3

VREF
+

Q1

Q1

Q2

Q2
-Vss

-Vss

Q1,Q2:Substrage-well-source/drain parasitic vertical BJTs

I
V BE = mVtherm ln E
IS
V REF = {VBE 1 +

+
CMOS
OP AMP

OP AMP

R2
R
I
R + R2
Vtherm (ln 2 + ln s2 ) + VOS [ 3
]}
R3
R1
I s1
R3

10 - 4

Typical design values:

I1=80A
I2=8A
R2

CHUNG-YU WU

0.6V
R
60mV
= 75 K, R1 = 2 = 7.5K, R3 =
= 7.5K
8A
10
8A
Large resistanceuse well resistors
R1,R2,R3:
n+/p+ diffusion resistors
n+ - poly resistors
well resistors

Both transistors are in the active region

VBE +
I1

Error analysis:
1. Error due to base resistances
I
1
rI
VBE 1 = Vtherm ln 1 + Vtherm ln
+ b 1
1
IS
A1
1+
1

VBE = Vtherm ln A + Vtherm ln

I2
+ Vtherm
I1

1
Q1

rb/A

I2

rb

2
Q2

-Vss
1
1
I
I
+ rb ( 2 1 )
ln
1
2 A1
1+
2

1+

If 1, 2 are not large enough or rb is too large,

V BE due to rb and is large.

V REF = {VBE 1 + VOS (

R3 + R 2
R
R
I
) + 2 Vtherm (ln 2 + ln s 2
R3
R3
R1
I s1

1
1
R
I
I
) + 2 rb ( 2 1 )}
+ ln
1
R3 2 A1
1+
2
1+

2.Error due to input offset voltage Vos

R
Vos =10mV, VOS (1 + 2 ) 10VOS = 100mV
R3
TC error due to

VOS :

1
VREF

d
VREF =
dT

R2
)VOS
R1
10 10mV
=
= 264 ppm / o C
VREF T0
1.26V 300 o K

(1 +

3.Error due to Bias current variation

VBE 1 = Vtherm ln

I1
V
ln A
= VThrem ln therm
(R3=R1)
I S1
R I S1

V
ln A
R (T )
= V therm ln therm
+ Vtherm ln 1 O
R1 (TO ) I S1
R1 (T )
If R1 is indep. of T V BE = V therm ln
If R1 depends on T V BE = V therm ln
V BE = V BE

ideal

1 dR
Vtherm
R dT

TO

TO

I1 = I 2

Vtherm ln A
R1 (TO ) I S1

V therm ln A
R (T )
+ Vtherm ln 1 O
R1 (TO ) I S1
R1 (T )

(T TO ) Vtherm 1 d R

2 R dT 2 T

PTAT 2
1 dR
+ V therm 2
2 R dT

10 - 5
CHUNG-YU WU

(T T )2
O

PTAT 3

PTAT

PTAT

(T TO )2 ......

PTAT 3

PTAT

If R is only linearly dependent on T, we still have PTAT 2 term

The PTAT 2 term can be cancelled via curvature compensations.
4.TC Error due to Base Resistance
I
V BE = rb 2
2
TC error = (1 +

R2 rb I 2
)
R1 Vref 2

1 drb 1 dI 2 1 d2

rb dT I 2 dT 2 dT

Example : rb = 2 K , TC of rb = 1000 ppm / O C , I 2 = 30A , = 150 ,

TC of = 7000 ppm / O C
TC = 8.6 ppm / O C
5.Error due to base current
Base current cancellation technique
*To compensate for the different between the collector, emitter, or base current

10 - 6
Version 1:

Version2:
+VDD

+VDD

IE

IB

I1

CHUNG-YU WU

IB
I1

IB
IB

IB

IB
-VSS

-VSS

Ref:1.IEEE J .Solid-State Circuits, vol.SC-18, pp634-640, DEC. 1983

2. IEEE J .Solid-State Circuits, vol.SC-19, pp1014-1021, DEC. 1984
The circuit to obtain VREF from a BGR
+VDD
Q1

Q2
R3

VBGR

+
+
R1

VREF=VBGR(1+R4/R5)

R2
R5

R4

10-3.2 Improved structure

1.

VBIAS

N
M1

M2

Vo=VR1 +VR2 +VBE3

*Better matching

KT
VR1 = VBE1-VBE2=
ln( )
q
KT
Vo=VBE3+
[ln( )] (1+R/R) =>Bandgap Reference
q

10 - 7
CHUNG-YU WU

2.

VBIAS
M4

M3

M2

M1

3.

M110

10 - 8

4.

CHUNG-YU WU

M110

+VDD
M105

M104
M111

M103

M109

M108
M110

M106 M107

M101 M102

M3
M1
-Vss

M2

M6
M4

M5

M112

10 - 9
CHUNG-YU WU

5.Low Power Supply Circuit:

M101
M102

-Vss
*Low driving capability
Power supply limits:
Low Possible
Bandgap reference
Topology

Voltage

T=25C

PMOS Inputs

NMOS Inputs

VTP 1.0V

VTN 1.0V

1
2

1.5v
1.95v

2.2v
2.95v

1.90v

2.5v

1.5v

10-3.3 CMOS BGR via lateral Transistor

Ref:IEEE J .Solid-State Circuits, vol. SC-20, pp.1151-1157, DEC. 1985
Structure of a lateral BJT in CMOS:

10 - 10

A.

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sub
B.
metal

sub

Symbol:

Voltage reference via LBJT:

Conceptual circuit

Q2
Q1

A:Current comparator
VCC:Voltage-controlled current source
G:A negative voltage is applied to cause
accumulation.

Advantages:(1)The offset of the amplifier A has a negligible effect on VREF

(2)Simple structure.
Purpose of VCC : To provide a current path for IR1>>IB1,IB2

10 - 11
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+VDD

+VDD

+
+

1:A

Vref

Vref

_
-Vss

-Vss
* High supply voltage.
* Two source follwers+one emitter follower
in(A) current amp.=>higher current gain

* Low supply voltage

* Low current gain in A
* R2 is trimmable

R4,R3,T3:VCC
R3: To keep T3 from quasi-saturation
R4:To sense the output voltage and transform it into the collector current of T3.
* All resistor are polyresistors
* Low output impedance.
Measured results:
VREF mean :1.2285V ;
Minimal supply voltage
Supply current

standard deviation :150V

2.2V
79A

Noise spectra

316nV

PSRR(100Hz)
Load regulation (Vout/Iout)
Chip area

60dB
3.6V/A
0.42 mm2

Hz

( white) ; 560nV

1
,1KHz )
Hz f
(

10 - 12

High PSRR BGR:

* R1,R2 may be p-well resistors and PSRR still high.
Experimental results:
VREF
1.2281V (mean)
350V ()
Minimal Supply
1.7V
Supply Current
20A
Noise Spectra

500nV
Hz
1V

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+VDD

( white)

1
( ,1KHz)
Hz f

PSRR(100Hz)
77dB
-Vss
Load Regulation
4.1mv/A
(Vout/Iout)
Chip area
0.18 mm2
Curvature-Compensated BGR:
Ref: IEEE J. Solid-State Circuits, vol. sc-20, pp.1283-1285, Dec. 1985

10-4

High-Precision Curvature-Compensated CMOS Bandgap

Voltage References (BVR)

Ref: Int. J. of Analog ICs and Signal Processing, Kluwer, pp. 207-215, 1992
1. Type A structure
The circuit stricture of the proposed BVR (Type A)

10 - 13
Vout = VBE 3 + I 3 R2 = VBE 3 + r3

R2 kT
( ln A* + Vsg )
R1 q

2. Type A structure

Cst

3. Type B structure

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10 - 14
4. Type C structure
The cascode structure of BVR (Type C):

The variation of Vsg versus temperature

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10 - 15
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The simulated output voltages versus temperature in Type A and Type A BVR

The variation of Vsg versus MOS channel length in Type A BVR

10 - 16
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The Spice simulated output voltages versus temperature in Type C BVR

The measured output voltages versus temperature in the fabricared cascaded-structure

BVR(Type C)[ 3.5 m CMOS technology , R1=1K(external),R2=25.9K(external)]

10 - 17
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* Average temperature drift

5.5 ppm/ oC
-60 oC ~ +150 oC
5V~15V
* At 25 oC, average voltage drift 25V/V
Vout=1.1963V
~
1.1965V
5V
~
15V
2
* 2 mil , 0.8 mW at 5V

10-5 CMOS Bandgap Reference with Sub-1-V Operation

Ref.: IEEE JSSC, vol.34, pp.670~674, May 1999
Concept: * Convertional BGR V ref = 1.25V
Cant be operated below 1V supply.
* The built-in voltage V f of the diode the current I 2b
The thermal voltage Vtherm the current I 2 a
( I 2 a + I 2b ) R V ref < 1V
1.Schematic of the proposed BGR

I1
R3

Vf1

I2a
Vf2

I1a
I1b

I3

I2

R1

Native NMOS VTHI = 0.2V

NMOS VTHN = +0.7V
PMOS VTHP = 1.0V

R2
I2b R4

10 - 18
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*The diode is realized by the parasitic P + / n well / P substract BJT as

* C1 and C 2 are used to stabilized the circuit.

*The control signal PONRST is used to initialize the BGR circuit when the power
is turned on.
* R1 = R2
V a = Vb
I1 = I 2 = I 3 and I1a = I 2 a , I1b = I 2 b
dV f = V f 1 V f 2 = Vtherm ln( N ) , N = 100
I 2a =
I 2b =

dV f
R3
Vf 1

V therm

Vf
R2
I 3 = I 2 = I 2a + I 2b

V ref = R 4 I 3 =

R
R4
V f 1 + 4 dV f
R3
R2

2. Simulated V ref characteristics

VDD

10 - 19
*V ref = 1.25V

conventional BGR

*V ref = 0.84V

proposed BGR

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3.Minimum V DD
min V1 V s Vb VTHI V f + VTHI V DD + VTHP = min V DD VTHP
min V DD = V f + VTHI + VTHP 0.8 ~ 1.0V
0.54

-0.2

-0.3

4.Measured results:

VDD

VDD
* TC 60 ppm / O C
27 O ~ 125 O C
Voltage drift (average) 600V /V

2.2V~4V

11-1
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CH 11 Digital-to-Analog Converters (DACs) in CMOS

Technology
11-1 Introduction
1. Block diagram

Analog Signal
( Video, Audio,
Sensor.....)

Filtering
and A/D
Conversion

Digital
Processing

Analog
Output

D/A
Conversion
and Filtering

Control
Analog World

Digital World

Analog World

(Digital signal processing has better noise immunity than analog signal processing.)

Fig. 11.1 A block diagram of a typical signal processing system

Digital
Data
Input

Data
Latches

D/A
Converter

Output
Sample
and Hold

Control

Fig. 11.2

Functional block diagram of a D/A converte

Analog
Output

11-2
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2. Ideal DAC:
Vout = Vref (b12-1+b22-2+ ---- +bN2-N)

Analog output signal

Vref: analog reference signal

b1 . b N : N-bit digital data input
The signal change when one LSB changes is VLSB
VLSB V ref
2N

If in LSB unit, 1LSB=

1
2N

3. DAC performance specifications

(1) Resolution: The number of distinct analog levels corresponding to the
different digital words.
N-bit resolution 2Ndistinct analog levels.
(2) Offset error:
E off (DAC)

Vout
VLSB

0.... 0

( LSB)

(3) Gain error:

E gain (DAC) [

Vout
VLSB

1.... 1

Vout
VLSB

0..... 0 ] (2

N 1)

(LSB)

Vout
VLSB

Ideal transfer
response

(LSB)

Gain error

Actual transfer
response

Offset
error o
0......0

Actual transfer response with

Eoff(DAC)set to zero
1......1

Digital Data
Input Bin

11-3
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(4) Accuracy
absolute accuracy: The difference between the expected and actual
transfer response. It includes the offset, gain, and
linearity errors.
relative accuracy:

The accuracy after the offset and gain errors have

been removed.
maximum integrated nonlinearity (INL) error

*Accuracy units:

% of full-scale value.
effective number of bits
fraction of an LSB

*12-bit accuracy all errors1 LSB (

Vout
)
212

(5) Integral nonlinearity (INL) error

Definition: The deviation of actual transfer response from a straight
line.
INL error (best-fit) and INL error (endpoint)
Usually, INL error is referred to as the maximum INL error.

Vout
VLSB
(LSB)

Best-fit
straight line
(maximum) INL error
(best-fit)

Transfer response
without gain and
offset errors

Endpoint straight line

(maximum)
INL error
(endpoint)
0......0

1......1

Bin

11-4
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(6) Differential nonlinearity (DNL) error

Definition: The variation in analog step sizes away from 1 LSB.
( usually, gain and offset errors have been removed)
(7) Monotonicity: The output signal magnitude always increases as the input
digital code increases.
* Maximum DNL error 0.5 LSB monotonicity
* Many monotonic DAC may have a maximum DNL error0.5 LSB
* Maximum INL error 0.5 LSB monotonicity
(8) Settling time
The time it takes for the DAC to settle to within some specified
amount of the final value (usually 0.5 LSB)
(9) Sampling rate
The rate at which sample can be continuously converted.
(Typically the sampling rate is equal to the inverse of the settling time)

4. Types of DACs
(1) Decoder-based DAC
(2) Binary-weighted DAC
(3) Thermometer-code DAC
(4) Hybrid DAC
(5) Oversampling DAC

11-5
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11-2 Decoder-Based DAC

11-2.1 Resistor-String DAC
1. Conceptual 8-bit resistor-string DAC.

REF+
S256
R

S255

255 RESISTORS R

S254

S253

+
_

DAC OUT

S4
R

S3

256 OUTPUTS

R
S2
R
S1

8 To 256
DECODER

REF0 1 2 3 4 5 6 7
(DAC INPUTS)

2. Practical realization
R0-R15 : To divide VREF + to VREF- into 16 voltage intervals
H0-H15
L0-L15: To divide each of those intervals into 16
a-p

subintervals

* To insure maximum uniformity of step size, i.e. linearity, the resistance

of the transmission gates should be made as large as possible minimal
loading.
* For 8-bit DAC, the error due to loading can be held to less than 1 LSB.
if

16RT 2N Ri ( Ri = 200 , RT 3.2K )

11-6
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8-bit Resistor-String DAC (Multiple Resistor-String DAC)

REF+

H15

0
1
4:16
2
3

L0
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15

H14

H13

H12

H11

H10

H9

H8

0
1
4:16
2
3

H0
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15

H7

H6

H5

H4

n15
R15
n14
R14
n13
R13
n12
R12
n11
R11
n10
R10
n9
R9
n8
R8
n7
R7
n6
R6
n5
R5
n4

H15

p15
o

H14

p14

L0

L15
n

H13

H12

H11

H10

H9

H8

H7

H6

H5

p13

p12

p11

p10

p9

p8

p7

L14

L13

L12

L11

L10

L9

L8

DAC OUT

p6

L7

p5

L6

p4

L5

p3

L4

p2

L3

p1

L2

R4
H3

H2

H1

H0

n3
R3
n2
R2
n1
R1
n0

H4

H3

H2

H1

R0
H0
REF-

p0

L0+L1

11-7
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Subinterval Generation:
14R T's
o

Lo

L15
n

Transmissiongate resistor

L14

L13

L12

L11

L10

Hi

RT

L9

L8

L7

DAC OUT

Ri+1
Ri

200

RT

L6

L5

Ri-1
Hi

R T=3.2K

L4

L3

L2

L0+L1

* Transmission gate size: 24 /12 3.2k = R T

* The raw speed of the DAC is limited by the resistance of transmission
gates a-p and the capacitance of the output node, also by the
operating speed of the output buffer.
* VDD = +5V, -VSS = -5V, Vout : 2.5V
Maximum conversion rate

0 full scale : 2.5MHz.

* For 8-bit DAC, the jump in step size can be held to less than 1 LSB if
16R T R i
Ri
R i
R i +16R T
Ri
=
=
1N
16RT 2NRi.
Ri
Ri
R i +16 R T 2
2N R i 16R T occurs when L1=1

11-8
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11-2.2 Folded Multiple Resistor-String DAC

11-9
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11-10
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11-11
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11-3 Binary-Weighted DAC

11-3.1 Charge-Redistribution DAC
1. Multiplying DAC
* All top plates are connected to
the OP AMP input
To reduce substrate noise

voltage injection.
* Switched-induced errors are
large.
* offset cancellation

2. Multiplying DAC with bipolar input

LSB
MSB

sign bit

If

bo = 0

the signal Vin is positive

the same as 1.

11-12
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If

b0 = 1

the signal Vin is negative.

1, 2 positions are exchanged.

n

Vout = -Vin bi 2 i
i =1

3. General characteristics or features of charge-redistribution DAC:

(1) The auto-calibration cycle can be performed to remove the effects of
component ratio errors.
(2) Good linearity and stability due to good linear capacitors.
(3) Too large capacitance ratio is required for high-bit DAC.
(4) Suitable for medium-speed DAC with 6-bit resolution or below.

11-3.2 Weighted-Current-Source DAC (Current-Mode BinaryWeighted DAC)

Conceptual circuit:

1. Conventional structure
* Simple circuit structure without
decoding logic.
* At the mid-code transition 011---1
10---0, the MSB current source
needs to be matched to the sum of
all the other current sources to
within 0.5 LSB.
difficult for large bit number.
not guaranteed monotonic.
* Low-accuracy matching causes
inaccurate bit transition
typical DNL plot as shown
* The errors caused by the dynamic
behavior of the switches, such as
charge injection and clock feedthrough,
result in glitches which is most severe at the
midcode transition, as all switches are
switching simultaneously.
contains highly nonlinear signal
components
manifest itself as spurs in the frequency
domain.

maximum

Midcode glitches

Transfer
response

Reference: IEEE Journal of Solid-State Circuits, vol.33, pp.1948-1958, Dec.1998.

11-13
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Conventional Weighted-Current-Source D/A Converter

2.

11-13

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11-14
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Improved Structure

The Proposed 10-bit D/A Converter

Reference: IEEE JSSC, PP.635-639, June 1989.

1. Using Two-Stage Architecture:

32 master & 32 slave current sources
(Occupied small chip area but cause tight matching requirement
among master current sources.)

2. Using Threshold-Voltage Compensated Current Sources

to satisify tight matching requirement.

Only need local match &

11-14

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do not need global match.

11-15
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Two-Stage Weighted Current Array D/A Converter

11-15

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11-16
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I1 = K (W/L)(Va-Vth1)2

IN = K (W/L)(Va-VthN)2
(VthN-Vth1) may be as large as 80 mV
due to the oxide thinning effect.

11-16

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Conventional switched current source.

11-17
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I 2 = K W (Va Vth 2 )2
L
= K W ( VR1 + Vth c Vth 2 + LcIc ) 2
L
KWc
1. I2IC
2. M2 and MC are locally matched

VR1

I 2 K W VR1
L

11-17

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Switched current source with threshold-voltage compensation.

11-18
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Spice Monte-Carlo simulation results for (a) Conventional

weighted current sources; (b) current sources with
threshold-voltage compensation.

11-19
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To Coax

YB

Y
D1

Driver

D5

YB

Vdd
Vdd

Vdd

VR2

VR2

VR2

Vb

Vb

Vb

VR3

ILSB
x1

VR3

x1

VR3

Vdd

Vdd

VB

To Dummy Load

ILSB
x16

Driver

Driver

D6

YB

Vdd

YB

IMSB-5
D10

Driver

Vdd

VB
VR2

VR2
c

Va
IMSB
Gnd

VR1

Va

IMSB-1
x16

VR2
Va

IMSB-4
x1

VR1

x1

VR1

11-19

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Two-stage weighted-current-source D/A converter with threshold-voltage

compensated current sources.

11-20
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CKs
D

Din
VB1

DB
VB1
Vdd

out
in

out

in

VB1

VB1

Vss

(a)

(b)
(a) The circuit; (b) The SPICE simulated output waveforms
of the input driver with high logic-threshold.

11-21
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16I

8I

4I

2I

I I

Symmetrical layout configuration of each 5-bit current array.

Compact

Symmetry

M2
M2

M2

M2

Mc
M2

Mc
M2

Different layout arrangement for the devices M2 and Mc in

each current source: (a) 4-cell unit; (b) 5-cell unit.

M2

11-22
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Differential linearity error of the D/A converter

Integral linearity error of the D/A converter.

11-23
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Differential and Integral linearity distribution of two

kinds of layout methods for each current source.
Linearity Error

4-Cell Unit(%)

5-Cell Unit(%)

1/2 LSB

28.6

21.4

1 LSB

82.1

67.9

2 LSB

93.9

89.3

Characteristics of the D/A converter.

Resolution
Differential Nonlinearity
Integral Nonlinearity
Conversion rate
Settling Time (1/2 LSB)
Rise/Fall time (10-90%)
Glitch Energy
Power Dissipation
Supply Voltage
Process
Chip Size (without pads)

10 bits
0.21 LSB
0.23 LSB
125 MS/s
8 ns
3 ns
40 psV
150 mWatts
5V
0.8um CMOS
1.8mm1.0mm

SUMMARY
1. Using threshold-voltage compensated current sources.
2. Two-step weighted current array 32 master, 32 slave unit current
sources.
3. 10 bits, 125MHz, INL0.21 LSB, DNL0.23 LSB,
150mW.
4. Few analog components & good performance.

11-24
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11-4 Thermometer-Code DAC

Current-mode thermometer-coded DAC; Current-cell-matrix DAC
1. Thermometer code (3 bit)
b2 b1 b0
d6 d5 d4 d3 d2 d1 d0
0 0 0

0 0 0 0 0 0 0
0 0 1

0 0 0 0 0 0 1
0 1 0

0 0 0 0 0 1 1
.
.
.
.
1 1 0

0 1 1 1 1 1 1
1 1 1

1 1 1 1 1 1 1
2. Conceptual circuit of thermometer-coded DAC
V DD

Vout,p

Binary
input

Vout,n

1024
Binary-to-thermometer decoder

10

+50%
Tolerance
-50%

4X

4 LSB

one step
1 LSB
1 SWITCH

4 SWITCHES

Advantages:
(1) Monotonicity is guaranteed.
(2) The matching requirement is much relaxed .
e.g. 50% matchingDNL0.5 LSB
(3) At the midcode transition the glitch is greatly reduced.
only 1 LSB current source is switched.

11-25
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(4) Glitches do not contribute much to nonlinearity.

Glitches switched LSB
Glitch/LSB constant
Good linearity.

Disadvantage: Area consuming

Every LSB needs a current source, a switch, a decoding circuit,
and the binary to thermometer decoder.
3. 8-bit current-mode thermometer-coded DAC
Conceptual architecture
Vdd

R
Vout

4LSB

LSB

2LSB

* The two LSB bits D0 and D1 are fed to two parallel three-stage pipelined
latches directly.
* The six MSB bits are fed to the decoders. (D2, -----, D7)

11-26
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Segmented decoding structure of the DAC

D2

D4

D3

Two-stage decoding of low bits

Cell

D7

D6

Two-stage decoding of high bist

D5

Decoding scheme:
Column
D4
D3
D2
D4+D3+D2 = C1
D4+D3 = C2
D4+D4D3+D3D2+D4D2 = C3
D4 = C4
D4D3+D4D2 = C5
D4D3 = C5
D4D3D2 = C7

Row
D7
D6
D5
D7+D6+D5 = R1
D7+D6 = R2
D7+D7D6+D7D5+D6D5 = R3
D7 = R4
D7D6+D7D5 = R5
D7D6 = R6
D7D6D5 = R7

Decoding of current-source matrix:

R1
R2
R3
R4
R5
R6
R7

R1+C1
R2+R1C1
R3+R2C1
R4+R3C1
R5+R4C1
R6+R5C1
R7+R6C1
R7C1

R1+C2
R2+R1C2
R3+R2C2
R4+R3C2
R5+R4C2
R6+R5C2
R7+R6C2
R7C2

R1+C3
R2+R1C3
R3+R2C3
R4+R3C3
R5+R4C4
R6+R5C4
R7+R6C4
R7C3

R1+C4
R2+R1C4
R3+R2C4
R4+R3C4
R5+R4C4
R6+R5C4
R7+R6C4
R7C4

R1+C5
R2+R1C5
R3+R2C5
R4+R3C5
R5+R4C5
R6+R5C5
R7+R6C5
R7C5

R1+C6
R2+R1C6
R3+R2C6
R4+R3C6
R5+R4C6
R6+R5C6
R7+R6C6
R7C6

R1+C7
R2+R1C7
R3+R2C7
R4+R3C7
R5+R4C7
R6+R5C7
R7+R6C7
R7C7

11-27
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Logic diagram of the segmented row decoder

* Clocked CMOS gates
* Pipelined structure with two stages.

Buffers

Buffers

D5
D7

D5
D7

D7
D6

D7

D7
D6

master slave
First stage

Second stage

Logic diagram of the segmented column decoder is similar to that of the row
decoder.
Current cell circuit
Ci
Ri

Ri+1

Third stage

* The third stage of the pipelined circuit.

11-28
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Symmetrical switching sequence to reduce the gradient effect.

Switching order

Switching order
C1 C3 C5 C7 C6 C4 C2
R1
R3
R5
R6

1
3
5

6
6
4
2
7

R4
R2
R7

Switching order

Switching order

Current source and current switch

Vdd
Vdd
Ir
Vcomp

Vcomp

M1

Vref

Vp
M2

Vref

Vp

M3
C

B
1 LSB current source

2 LSB current source

Vdd

Vcomp

Vref

Vp

4 LSB current source

11-29
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General characteristics/features of current-mode thermometer-coded DAC:

(1) No resistor or capacitor are used.
(2) Require special layout arrangement and complicated switching sequence to
reduce the mismatches among current cells in the matrix complicated
decoder
(3) Logic circuits and long delay.
(4) Complicated wiring
(5) Large chip area worse matching problem.
(6) Suitable for high-speed (video) and high-resolution (10-bit) CMOS DAC.
Current switching and better matching than resistors.

11-30
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11-5 Hybrid DAC

Combined architecture: Resistor-string + charge-redistribution DAC
Weighted-current-source + current-mode thermometercoded DAC

11-6 Case study

Ref.: IEEE JSSC, vol.33, PP.1948-1958, Dec.1998
10-bit 500-MS/s CMOS DAC:
Chip area comparison between weighted-current-source DAC and thermometercoded DAC
TABLE I
AREA R EOUIREMENT FOR BINARY-WEIGHTED AND THERMOMETER-CODED DAC
Requirement
Binary Weighted
Thermometer Coded
INL (10-bit)
16
(0.5 1024 ) = 16
DNL (10-bit)

1024 = 32
Area (INL=0.5-lsb)
Area (INL=1-lsb)
Area (DNL=0.5-lsb)

256*Aunit
64*Aunit
1024*Aunit

256*Aunit
64*Aunit
Aunit

: standard deviation of current sources.

Aunit: minimum required area to obtain a DNL = 0.5 LSB for the
thermometer-coded architecture.
Chip area 12

Normalized required chip versus

percentage of segmentation and
THD versus percentage of
segmentation

Optimal point
Adigital = AINL = 1.0 lsb
THD

binary

segmentation [%]

thermometer

11-31
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Block diagram: 8+2 segmentation

Cell circuit
Digital: decoding logic + latch
Analog: differential switch +
cascoded current source.

Biasing scheme
Global biasing: common-centroid
layout
Local biasing: 4 quadrants
without direct connection between any two quadrants
DNL and INL

11-32
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Sinewave spectrum for Fs=300MS/s and Fsig=100MHz . SFDR=60dB

SFDR versus Fsig/Fs

SFDR
73dB
60dB
51dB

Fs(MS/s)
100
300
500

Fsig(MHz)
8
100
240

11-33
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Summary

DNL

0.1 LSB

INL

0.2 LSB

2. Definition of SFDR (Spurious-Free Dynamic Range)

SFDR: The signal-to-noise ratio when the power of the third-order
intermodulation products equals the noise power.
SFDR = ID1* - ID3* = ID1* - N0

(dB)

ID1 curve has a slope=1

SFDR=

A I D3= N0 AN 0 ID1= N

11-34
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11-7 Summary

[16]

[15]

[14]
[9] [10]
[7] [6]

[13]

[12]

[3] [2]

[8] [5]

[11]

[14]

[4]

[1]

1. Kuang K. Chi et al, "A CMOS triple 100-Mbit/s video D/A converter with shift
register and color map," IEEE J. Solid-State Circuits, Dec. 1986, pp. 989-995.
2. T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80MHz 8-bit CMOS D/A converter," IEEE J. solid-State Circuits, pp. 983-988, Dec.
1986.
3. L. Lteham, B.K. Ahuja, K.N. Quader, R.J. Mayer, R.E. Larsen and G.R. Canepa,
" A high-performance CMOS 70-MHz palette/DAC," IEEE J. Soulid-State
Circuits, pp. 1041-1047, Dec. 1987.
4. A. Cremonesi, F. Maloberti, and G. Polito, " A 100-MHz CMOS DAC for videographic systems, " IEEE J. Solid-State Circuits, June 1989, pp. 635-639.
5. N. Kumazawa, N. Fukushima, N. Ono, and N. Sakamoto, "An 8 bit 150 MHz
CMOS D/A converter with 2 Vp-p wide range output," 1990 Symposium on

11-35
CHUNG-YU WU

6.

7.

8.

9.
10.

11.

12.

13.

14.

15.

16.

VLSI Circuits, pp. 55-56.

Marcel Pelgrom, " A 50MHz 10-bit CMOS digital-to-analog converter with 75
buffer," Proc. of IEEE International Solid-State Circuits Conference, pp. 200-201,
1990.
C. A. A. Bastiaansen, D. W. J Greoeneveld, H. J. Schouwenaars, and H. A. H
Termeer, " A 10-b 40-MHz 0.8-m CMOS current-output D/A converter," IEEE J.
Solid-State Circuits, pp. 917-921, July 1991.
J.M. Fourier and P. Senn, " A 130-MHz 8-b CMOS Video DAC for HDTV
Applications, " IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 1073-1077, July
1991.
Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, " A 10-b 70-MS/s
CMOS D/A converter, " IEEE J. Solid-State Circuits, Apr. 1991, pp. 637-642.
H. Takakura, M. Yokoyam, and A. Yamaquchi, " A 10 bit 80MHz glitchless
CMOS D/A converter, " 1991 IEEE Custom Integrated Circuits Conference, pp.
26.5.1-26.5.4.
D. Reynolds, " A 320 MHz CMOS triple 8-bit DAC with on-chip pll and
hardware cursor, " IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1545-1551
DEC. 1994.
Shu-Yuan Chin and Chung-Yu Wu, " A 10-b 125-MHz CMOS Digital-to-Analog
Converter (DAC) with Threshold-Voltage Compensated Current Sources, " IEEE
Journal of Solid Circuits, vol.29, no. 11, pp. 1374-1380, Nov. 1994.
Chi-Hung Lin and Klass Bult, "A 10-b, 500-Msample/s CMOS DAC in 0.6
mm2," IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec.
1998.
Jose Bastos, Augusto M. Marques, Michel S. J. Steyaert, Willy Sansen, "A 12-Bit
Intrinsic Accuracy High-Speed CMOS DAC," IEEE Journal of Solid-State
Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
Greet A. M. Van der Olas, Jan Vandenbussche, Willy Sansen, Michel S. J.
Steyaert, and Georges G. E. Gielen, "A 14-bit Intrinsic Accuracy Q2 Random
Walk CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 34, no. 12,
pp.1708-1718, Dec. 1999.
Alex R. Bugeja, Member, IEEE, Bang-Sup Song, Fellow, IEEE, Patrick L. Rakers,
Member, IEEE, and Steven F. Gilling, Member, IEEE "A 14-b, 100-MS/s CMOS
DAC Designed for Spectral Performance," IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL. 34, NO. 12, DECEMBER 1999.

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CH 12 CMOS Analog Comparators

12-1 General Considerations
Purpose of Comparators: To compare two input voltages and produce a very
large output voltage with an appropriate sign to
indicate which of the two is large.
Types of MOS Comparators:
A. Differential-input OP AMP
_

Latch

Vout

+
or

Vout

The latch provides a large and fast output signal, whose amplitude
and waveform are independent of those of the input signal. Well
suited for the logic circuits usually following the latch.
If no latch:

-1mV +1mV input =-5V+5V output

Gain5000, 74 dB

If use latch: The output voltage of A must be larger than the

combined offset and threshold voltage of the latch,
which is about 0.2V
Gain = 200
(1) Static configurations
(2) Dynamic configurations
B. Cascaded inverter stages
Vin

-A1

-A2

* Mostly dynamic

-A3

Vout

-An

Latch

or

Vout

12-2
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12-2 Differential-Input OP AMP Comparators

12-2.1 Static Configurations without Latches
1.
+VDD
M3

M9

M4

M8
Vbias

M15
M12

M11

M1

M2

Vout

M10

M6

M5
M13

M7

M14

-VSS

* High Speed Comparator

* Open loop gain: ~80dB
* Output Swing: 5V
* Propagation Delay (10mV Vin ): ~1.2s~2.4s (15PF Load)
* Generally, compensation circuit is not needed since there is no feedback
connection.
* Power Dissipation: ~10 mW
2. General-purpose comparators
* Propagation delay:

(10mV, 15PF)

* Power Dissipation:

~ 4mW

1.0s~2.8s

12-3
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+VDD
M4

M3
M7
Vbias

M10
M8
-

+
M1

Vout

M2

M5
M9

M6

M11

-VSS

3. Comparator with level shift.

+VDD
M3

M4

M14

M7
M11

Vbias
M
8

M12

+
M1

Vout

M2
M9
M10
M5

M6

M13
M15

-VSS

* Open loop gain: 60-80dB

* Output Swing: +5V0V
* Propagation delay (10mV, 15 PF): 1.0s~0.8s

12-4
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* Power Dissipation: ~1.5mW

4. CMOS Voltage Comparator MC 14574 (Motorola)
V+

Q5
Q6

Q8
Q10

input+

Q12

I
Q

Vo

inputQ1

Q2

Iset
Q11

Q9
Rext Q3

Q7

Q4

External
resistor
V-

* Quad comparators
* Open loop gain (IsetIQ50A): 96dB
* Propagation delay: ~1s
5. Fully differential OP-AMP Comparators.

12-2.2 Dynamic Configurations without Latches.

(1) Dynamic OP-AMP
type comparator
* Compensated by C2

1=1
Vin

- Vos +
C2

C1

Gain Stage

+V in -

* Vc1=Vin-Vos

+
_

* offset memorization
2=1

+V in -

* No compensation

C2
+

Vref

*Vc1Vref-Vin

Vout

Vos

C1

Vc1
+
_
Vos

* offset cancellation
1 , 2 :nonoverlapping
clocks

Gain Stage
+

Vout

12-5
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+VDD

C1

Vin
S1

Vout
+
_

S4

C2

2
Vbias
Vref
-Vss
S3

1a
* Practically, 1a must go low first in advance of 1 to avoid the clock
feedthrough effect of S1 by 1.
(2) Dynamic fully differential comparator
+V DD

Vin+

VinVbias1

1a

1a

+ Vout S1

C1

Vs

Vs

S2

2
C2

1
Vbias2
VinVin+
-V SS

C1, C2: Autozeroing capacitors

1 1
Vc1Vin- - Vs,
VC2 Vin+ - Vs
2 1
Vc1Vin+ - Vin-, VC2Vin- - Vin+
* S1 and S2 generate feedthrough voltages at A and B
common-mode voltage
* CMRR can be promoted by using negative common-mode feedback circuit.

12-6
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12-2.3 Dynamic Configuration with Latches

Preamplifier-latch combination
+VDD
VBIAS1
Q3

Q4
VC

S7

Vout

S8
Q1
Vin-

Q2

VB

C2

C1

S1

S5

Vin+

+
Q5

S4

Q6

Vin+
S6

S3

Vin-

Q7

VBIAS2
-Vss

* 2 1,

S5 short

Q1, Q2, Q3, Q4 and Q7 are differential amplifier.

2 1,

S6 short

Q3, Q4, Q5, Q6 and Q7 are a bistable latch.

Operating clock waveforms:

12-7
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12-3 Cascaded Inverter Stages

(1) Basic Structure

VT
VDD
Q2

VT

S3
VB

VA

Q1

-VSS

(a)

(b)
+VDD

Q2

C
+

Vin
A

S3

VB

2
VA

Q1
CA (stray)

-Vss

(a)
2 0,
CAC,
VA1Vin + VAo
VAVin
(2) CMOS Cascade Comparator.
* Q1 Q3, Q2 Q4

(b)
negligible feedthrough

12-8
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* The speed of the cascaded inverter stages is limited by the RC times

constants.

R = R 0 = rdsp rdsn

~ 100 k

CinCgs + Cgd(1+ A )

~0.5 pF

A ~ 10

VDD
Q2
1

Vin

S2

C2

VB
B

3
C VC
S8

C3 VD
Q5

Q1

6 (strobe)

Q6

S3
C1 VA

S1

Q4

LATCH
S5

Q3
5 (balance)
VSS

(a)

(b)

Vout

12-9
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(3) Fast comparators with two amplifiers and a single latch.

* Usually, the speed of a latch is faster than that of a amplifier.
Two amplifiers share one latch.
VDD

1
Vin

S1

A
SA

1
LATCH
VSS
VDD

SB
2
VSS

* Operating clock waveforms

12-10
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12-4 CMOS Dynamic Latches for Comparators

1. Direct-coupled latch with differential input signals
VDD
2

Vin +
C1

+
Vout

Vout

Vin -

C2

-VSS

* For single-ended inputs, Vin+ or Vin- may be replaced by a threshold voltage or

can be generated by self-biasing
2. Capacitively coupled latch with autozeroing input
V DD

C4

Q5

C3

Vout +

S3

S1

A
VA

VC

C1
3

Q6

D
S4

S5

Q1 Q2

VD
Q 3 Q4

S2

S6
B
VB

VinS8
S7

VSS
V in-

Vin +

(a)

C2
+

Vout

12-11
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* 21 inverters Q2-Q5 and Q3-Q6 are biased at their optimal points

C3 and C4 are also precharged such that any asymmetry between
the two inverters is compensated by the slightly different bias
voltages provided by C3 and C4.
loop gain of the latch1.
* Vin+ Vin- : VC

H,

VD

L.

Vin- Vin+ : VC

L,

VD

H.

12-12
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12-5 Case Studies

1. Differential-Input OP AMP Comparators with Dynamic Latches
Ref. IEEE JSSC, vol. 27, pp. 208-211, Feb. 1992

input stage

flip-flops

S-R latch

VDD
1:2
M13

M3
M10

M6

M2

M1

M11
Q

IB

Vinp1

M7

M8
Vinp2

a
VSS

M9
M12

M4

b
M5

t1~t2: M12 ON (2 1)
M10-M11 ON, M8-M9 OFF (10)
VaVb, Vc=Va, Q= Q
Vinp1 and Vinp2 settles
t2~t3: Va Vb established with some regeneration of M4 /M5, M12 OFF
t3-t4: 1 1, 20 M12 OFF, M10, M11 OFF, M8, M9 ON
strong regeneration Vc Va, Va=Vc, Vb=Vd Q, Q
established
for input sampling
V

2e

t1

t2

t3

t4

12-13
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Performance:
Technology

1.5 um CMOS

Die size

140 x 100 um2

Power supply

+2.5 / -2.5 V

Input dynamic range

2.5 V

Resolution

8 bits, 1LSB=9.8 mV

Sensitivity

10.6 mV ( < 7 bits)

Sampling rate

65MHz

Offset voltage

3.3 mV

Input capacitance

30 fF

13-1
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CH 13 CMOS Analog to Digital Converters (ADCs)

13-1 Introduction
1. Functional block diagram of a A/D converter

Analog
Input

Sample
and
Hold

A/D
Converter

Digital
Output

Output
Latch

Control Logic

2. Ideal A/D Converter (ADC)

Vin Vx = Vref ( b121 + b2 22 + +bN 2N )
Vref
(b12 N 1 + b2 2 N 2 + +b N 121 + bN 20 )
N
2
where Vin is the input analog voltage or current
Vref is the reference voltage or current
b1 .b N is the digital output
Vx is the tolerable input signal range
1 VLSB Vx 1 VLSB
2
2
2-bit ADC:
Input-output transfer curve:
equivalent DAC transfer response
Bout
1
1
Offset by VLSB ( LSB)
2
2
11
1
VLSB = Vref 1 LSB
4
10
VLSB 1
= 1 LSB
01
Vref 4
The input voltage or current 0 0
1/4
1/2
3/4
should remain less than 3/4 Vref +
V
V
V
V
V
V
1/8 Vref =7/8 Vref and greater than
V
V
0 - 1/8 Vref = -1/8 Vref .
=

01

10

11

ref

ref

ref

ij

ref

Vin
Vref

13-2
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Overloaded ADC: When Vin > Vin ideal + Vx or Vin < Vin ideal Vx , the
quantization error is greater than 1/2 VLSB.
3. Quantization noise
Quantization error Quantization noise.
V1 = Vin + VQ
V in

ADC

VQ = V1 - Vin

DAC

V1

Quantization noise modeling:

VQ

(1) Deterministic approach

VQ(rms) = 1
T

T/ 2

T /2

1/ 2

2
VQ

VLSB3 t 3

=
3 3
T

dt

=1
T

T /2

T /2

T /2

T/ 2

1/ 2

2
VLSB ( t )2
T

1/2

dt

VLSB
12

VQ

Vin
V1
+

1
VLSB
2
0
1
VLSB
2

V1

T
2

T
2

t
( time )

(2) Stochastic approach

VQ ( rms ) =

= 1 2
VLSB

2
x 2 f Q ( x ) dx

x 2 dx
VLSB /2

V LSB /2

High =

V LSB

1/ 2

fQ (x) (probability density

function)

f Q (x)

dx =1

1/2

VLSB
12

1
2

V LSB

1
2

V LSB

13-3
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4. Signal-to-Noise Ratio (SNR)

(1) Vin is a sawtooth of hight Vref (or a random signal uniformly distribut between
0 and Vref )
Vin ( rms )
SNR = 20 log
VQ ( rms )

V / 12

= 20 log ref
V / 12 = 20 log 2 = 6.02 N dB

LSB

(2) Vin is a sinusoidal waveform between 0 and Vref .

SNR = 20 log

Vin( rms )
V /2 2

= 20 log ref
= 20 log 3 2 N = 6.02 N +1.76dB
VQ ( rms )
VLSB / 12
2

The above SNR is the best possible SNR for an N-bit ADC
Vinpp = Vref ( 0dB) SNR = 6.02 N +1.76 dB
Vinpp 20 dB SNR = (6.02 N +1.76 )dB 20 dB
5. Performance specifications
(1) Missing codes (equivalent to monotonicity in DAC)
Maximum DNL < 0.5 LSB or maximum INL < 0.5 LSB

The ADC is guaranted not to have any missing code.

(2) Conversion time
The time taken for the ADC to complete a single measurement including
acquisition time of the input signal.
(3) Sampling rate
The speed at which samples can be continuously converted. Typically,
the sampling rate is equal to the inverse of the conversion time except in
the case of pipelining structure or multiplexing structure.
(4) Sampling-time uncertainty or aperture jitter
Due to the effective sampling time changing from one sampling instance
to the next.
Sinusoidal waveform case:
Vin =

Vref
sin (2 f in t )
2

13-4
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dV
dt in

max

= f in t

zero-crossing point

If V < 1 VLSB for some sampling-time uncertainty t ,

t <

VLSB
= N1
f in Vref 2 f in

examples: 8-bit ADC, 250 MHz

16-bit ADC, 1 MHz

f in t < 5 ps
f in t < 5 ps

(5) Dynamic range

Dynamic range
rms value of the maximum input (output) sinusoidal signal
rms value of the output noise plus the distortion when the same sinusoidal
is present at the output
It is also called the signal-to-noise-and-distortion ratio (SNDR).
* Can be expressed as effective number of bits using the SNR formula on
p. 13-3.
* Input frequency dependent.
6. Types of ADCs
Low-to-medium speed:

(1) Dual-slope or Integrating ADC

(2) Oversampling ADC
(3) Successive approximation ADC
(4) Algorithmic ADC

High speed:

(1) Flash ADC

(2) Two-step ADC
(3) Pipelined ADC
(4) Interpolating ADC
(5) Folding ADC
(6) Time-interleaved ADC

13-5
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13-2 Successive-Approximation (SA) ADC's

13-2.1 Resistor-string SA MOS ADC
Ref. : IEEE J. Solid-State Circuits, vol. Sc-13, pp. 785-791, Dec. 1978.
Conceptual 3-bit unipolar ADC

VREF
3R
2

B B

R
R
R
Comparator
_

Output

VIN

R
2

Typical performance of a 8-bit ADC:

p-type resistor

Resolution

100 /

Nonlinearity

Conversion time

8 bit
1 LSB
2
1 LSB
10
20 s

Input resistance

>1000 M

Stability (0o - 85o C)

<1/4 LSB

DNL

Error Sources:
1. Resistor matching accuracy.
* Dividing the string into several equal lengths and locating them in close
proximity.

13-6
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2. The reverse bias junction voltage of the diffused resistors causes nonlinearity.
Bit capacity /

3. The small on resistance of the switches can decrease the settling time and
reduce the feedthrough effect from the gate voltages. Similary, the switch
feedthrough only effects the settling time.
4. Major error source: The feedthrough in the switch transistor Q2.
1 MHz clock 2 mV error.
5. Comparator offset error.

13-2.2 Charge-Balancing SA MOS ADC

Ref. : IEEE J. Solid-State Circuits, pp. 912-920, Dec. 1979.
* Mixed resistor string and binary-weighed cap.
Vref
F

3rd
MSB

MSB Vin
2-bits +

A
E

T1

T1
T2

Sample
data
Comparator

T1
A

F
H

B
D

2 nd
MSB

T2

R/4

LSB

T2

R/4

R/4

D
R/8
R/8

T1

C/16

1/2 LSB
Shift
T2

8-bit ADC

C/16

C=20pF

Linearity

1/4LSB

Supply Voltage

4.5 - 6.3 V

Conversion Time

100 s

Current Drain

1.8mA

VREF Range

0-5V

Clock Freq. Range

100 - 800 KHz

640 KHz clock

Analog Input

0 - VDD

Components used: 8R's, 4C's, 32 switches.

13-7
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13-bit ADC with laser-cut programmable Si-Cr fuse PROM's.

Post-process triming

Linearity

1/2 LSB

Conversion Time

50 s

Analog input

Vss ~ Vcc

Clock freq. range

0.1 ~ 3MHz

Supply voltage

4.5 ~ 6.3V

Current drain

5mA

13-2.3 Charge-Redistribution SA MOS ADC (CRSA ADC)

1. 10-bit CRSA ADC
Ref: IEEE JSSC, vol. SC-10, pp. 371-379, 379-385, Dec.1975.
Operation Procedures
(a) Sample Mode:

(b) Hold Mode:

13-8
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(c) Redistribution (Approximation) Mode:

S1 Vref , Vx = -Vin + Vref /2

If Vx < 0,
logic 1 in MSB(b4),
If Vx > 0,
b4(MSB)=0,

Vin > Vref /2

Vin < Vref /2 and S1 ground

Final Configuration:

Vx = Vin + Vref ( +
Vx = Vin +

b 4 b 3 b 2 b1 b 0
+ + + + ) 0
21 2 2 2 3 2 4 2 5

Vref 4
( 2 b 4 + 2 3 b3 + 2 2 b 2 + 21 b1 + 2 0 b 0 ), Vin > 0
5
2

13-9
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Complete ADC block diagram:

Measured Results:
Resolution

10 bits

Gain error

0.05 %

Linearity

1 LSB
2

Sample mode
acquisition time

2.3s

Input Voltage

0-10 V

Total conversion
time

22.8 s

Input offset

2mV

13-10
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2. 12-bit modified CRSA ADC

Ref.: IEEE J. Solid-State Circuits, vol. sc-14, pp. 920-926, Dec. 1979.
VREF

R1
SF

R2
Ck+1

Ck

C3

2 k-1C 2 k-2C

R3

2C

C2 C1
C

+
Comparator
SA

R2 M-1
CLOCK
B
SB

R2M

SWITCH
CONTROL

VIN

SUCCESSIVE APPROX. REGISTER

+ SWITCH CONTROL LOGIC

(M+K) BIT OUTPUT OF A/D

START

* SAMPLE
* HOLD
* CHOOSE Vref

VREF
R1

S5

Vin

S4

Larger

Vref
4

Smaller

Vref
2

discharge

set-up

ON ON

redistribution 2

ON ON

3/4 V REF
R2

S3

S2
1/4 V REF

R4

SA
2
2
SB

S1

SB

S1

S2

S3

S4

ON ON

1/2 V REF
R3

Voltage A- SA
B

ON ON

ON

S5

13-11
CHUNG-YU WU

Implement:
16 R, 8 ratioed capacitor, 37 MOS
, 16 R= 9000

R: S/D diffusion, 18/

C: Unit capacitor, 400 m2, 0.1 pF

Measured data:
12,000 mil2

Resolution

12 Bits

Area

Monotonicity

12 Bits

Power dissipation (15V) 40 mW

Integral Linearity 6 Bits

DNL

1 LSB
2

Input. Offset

Total conversion time

50s

5 mV

Operational Principle:
Vref
SX

S5

R1

2k-1C
S4

R2

C
SLK

SL2

C
SL1

+
Vx
-

+
Comparator

1
SA

S3
R3

2
S2

R4

SB
S1

1
VIN

SA

SB

S1

S2

S3

S4

S5 SLK . SL2 SL1

Sample
Hold

Vin
1

ON OFF OFF OFF OFF

ON ON OFF OFF OFF

B
B

.
.

B
B

Choose Vref

OFF ON ON OFF OFF

Sx

Vx

B
B

ON
OFF

OFF V + Vref
in

-Vin

(0)

2
(Vref/4)

OFF OFF ON ON OFF

OFF OFF OFF ON OFF

ON OFF OFF OFF OFF

(Vref/2)

2
(3Vref/4)

Discharge

1
(0)

4
OFF V + 2Vref
in
4
OFF V + 3Vref
in
4

OFF

-Vin

13-12
CHUNG-YU WU

Set up

OFF OFF OFF ON ON

OFF

Vin +

-Vin+(3/4)Vref < Vx < -Vin + Vref

OFF OFF OFF ON ON A .
B

OFF

3V
Vin + ref
4
+ 1 Vref
8

(Vref) (3Vref/4)

Redistribution
1

* The last capacitor C is always connected to B.

3Vref
4

13-13
CHUNG-YU WU

13-3 Dual-Slope ( Integrating; Charge-Balancing ) MOS ADC's

4 1 Digit ADC (Modified structure)
2

LATCH, DECODER,
DISPLAY MULTIPLEXER

UP/DOWN RESULTS COUNTER

SEQUENCE COUNTER
/ DECODER

CONTROL
LOGIC

ANALOG
SECTION

CREF
REF HI
DE

REF LO
DE

INT1
IN HI

X10

CINT

RINT

C2
<10>

COMPARATOR 1
+

DE-

DE+

DE+

DE-

BUFFER

ZI , X10

COMMON
INT
IN LO
INT1,IN2,INT

REST

C3
INTEGRATOR
<100>

COMPARATOR 2
+

TO DIGITAL
SECTION

13-14
CHUNG-YU WU

Waveforms observed at the node A :

DE1

INT1

X10

RESET

DE2

V'

INT(ZI)

INT2

NOTE: ENCLOSED AREA GREATLY EXPENDED IN TIME AND AMPLITUDE

Operational principles:
1. INT1
REF HI

REF LO
CINT

CREF

RINT

IN HI

IN LO

Comparator 2

+
+

COMMON

Comparator 1

C3
100p

+
-

13-15
CHUNG-YU WU

2. DE1

REF HI

REF LO

+ -

R INT

CINT

+ -

COMMON

+
-

C3
100p

+
-

3. REST (INT2)
REF HI

REF LO
CREF
CINT

R INT

+V -

+
+

C3
100p

COMMON

V
+

+
-

IN LO

V Residual Voltage

4. 10 (INT2)
RINT

+
COMMON
IN LO

10 V
+
C INT

10 V
+
C2 10p

C3 100p

+
-

+
-

13-16
CHUNG-YU WU

5. DE2 (The same as DE1), V ' : residual voltage

6. INT(ZI)
R INT

C INT

C3
100p

+
-

+
-

IN LO

The final residual voltage V ' is effectively reduced to 1 of the original

10
residual voltage without amplification.
accuracy

13-17
CHUNG-YU WU

13-4 Algorithmic ADC

Refs: 1. IEEE ISSCC, Digest of Papers, pp. 96-97, 1977
* 2. IEEE JSSC, vol. 31, no. 8, pp. 1201-1207, Aug. 1996

Vin

Sample/Hold
Comparator
S/H

Comp.

V(i)

multiplier

B(i)

x2

+ Vref
- Vref

The conceptual block diagram of the algorithmic A/D converter

* The speed is limited by the settling time of OP AMPs used to implement

the multiplier.
* For audio ADC applications, it could reach low-power low-voltage
operation.
* Major error sources: (1) Capacitor ratio mismatches if SC circuits are used.
(2) Finite-gain error of OP amps.
(3) Offset voltage of OP amps.
(4) Capacitor feedthrough error by switches if SC
circuits are used.

13-18
CHUNG-YU WU

Complete circuit of the ratio-independent and gain-insensitive algorithmic

ADCs
1+2
1+2+3+4+5
2

3+4+6+7

C3

C7

S4

C2

8*1

S2
1+2

Vin

C1

(A)

(C)
Vref

OP1

3+4+5+6+7

+
4

C5

3+4+7

3+6

C6

3+7

6+7+1

Latch

S7

C8
(D)

7+1

S5

b8(1+2)

3+6

OP2

3+4+6+7

b8*1

S3 3+4+6+7

S1

C4
S6

(B)

1+2+3+4

comp.
+

bBit

Bit

switch

The complete circuit of the A/D converter

Clock waveforms:

13-19
CHUNG-YU WU

Operational principles:
Step 1:
C2
8*1
C1

C3

Vin

C7

C4
-

OP1

OP2
+

+
C5

b8*1

Vy(1)

C6

b8*1

13A + 27 Vx ( 3) 1 7 A + 8 + 7A + 9
Vy (1) 2 13A + 20
+
( A + 2) 2 ( A + 3) 2
2
( A + 3) 2
( A +2)

Vref

Step 2:
C2

C1

C3

Vin

C4

C7
-

OP1
+

OP2
+

Vx(2)
C5

C6

b8*2
to Comp.

Vx (2) Vin / (1+2/A)

Step 3:
C2

C4

C1

C3
-

C7
OP2

OP1
+

Vx(3)

+
C5

Vx (3) Vin [1-2/(A2 +3A+2)]

C6

Vy(2)

13-20
CHUNG-YU WU

Step 4:
C2

C4

C3

C7

C1

OP2

OP1
+

Vy(4)

+
C5

C6

Vref

Vy ( 4 ) C5 ( Vx ( 3) Vref )(1+ 3/ A )
C6
Step 5:
C2

C4

C1

C3

C7

OP1

OP2
+

Vref

+
C5

C6

Vy (5) C3 ( Vx ( 3) Vref )[1+ 6 /( A 2 + 5A )]

C4
Step 6:

C2

C4

C1

C3
-

C7
OP2

OP1
+

+
C5

C6

Vy(5)

13-21
CHUNG-YU WU

Step7:
C2

C4

C1

C3

C7

OP2

OP1
+

Vy(7)

+
C5

C6

( 2 2 ) Vx ( 3) (1 2 ) Vref
A +3
A+ 3
Vy ( 7 )
1+ 3 / A

Fully differential circuits:

Vin+

Latch
-+
OP1

+-

Vref+(-)
Vref-(+)

-+

-+

OP2

comp.

+-

+-

Vin-

The complete fully-differential circuit of the A/D converter

+ -

bBit

- +

Bit

13-22
CHUNG-YU WU

The folded-cascode fully-differential operational amplifier.

VDD
m12

m13

m4

m5

m6

m7

VB1

VB2

Vo+ VoVin-

Vin+
m1
m3

m8

m2

m9

m10

m11
m14 m15

VSS

Chip photograph of the A/D converter.

VB3

VB4

13-23
CHUNG-YU WU

A typical plot of the differential nonlinearity.

A typical plot of the integral nonlinearity.

13-24
CHUNG-YU WU

A typical FFT plot of the A/D converter.

Table I

The Experimental results of the proposed A/D converter.

Resolution

14 bits

Differential nonlinearity

1/2 LSB

Integral nonlinearity

1 LSB

Sampling frequency

10 KHz

Gain of op amp

60 dB

Power dissipation

50 mWatts

Supply voltage

2.5 V

Process

0.8 m CMOS

Chip active area

2.1mm 0.8mm

13-25
CHUNG-YU WU

Table II

Comparison of the proposed A/D converter with the

previous ratio-independent A/D converters [4.4]-[4.5].
A/D converters

Performance

[4.4]

[4.5]

This work

12

14

<= 1.5

<= 0.5

<= 1

92

84

60

6n

3n

7n

10

17

50

Resolution
(bits)
Absolute
INL (LSB)
OP amp dc
Gain (dB)
Clock cycles
for n bits
Sampling rate
(KHz)
Power dissipation
(mW)

13-26
CHUNG-YU WU

13-5 Full Flash (Parallel)

* Need 2N-1 comparators for N bits.
* Need 2N-1 Resister (R) tapes for N bits.
* S/H usually combined with comparators. (No op amp is required)
? Large no. of analog elements.
? Large chip area power consumption.
Full-flash A/D converter
VIN
VREF+

+
-

2N-1

2N-1

2N-2

2N-2

+
-

Encoder

2N-1 to N
binary code
+
2

+
comparator
VREF-

Latch

Output registor & buffer

Clock
generator

bN-1
bN-2
bN-3

b2
b1
b0

13-27
CHUNG-YU WU

13-5.1 MOS Flash ADC's

Ref.: IEEE JSSC, vol. sc-14, pp. 926-932, Dec. 1979.
CMOS/SOS 6 bit 20 MHz ADC.

6-BIT
BINARY
OUTPUT

Block diagram of A/D converter chip.

High speed autozeroed CMOS/SOS comparator.

13-28
CHUNG-YU WU

Discrete and distributed reference ladder models

Ccomp 0.05 pF, RTAP = 20
Z( w )
R TAP

50,000 (< 10,000, don't work)

Reference ladder leading as a function

of input voltage
(|Z|(W) /RTAP = 500)

Effect of loading ratio on reference

ladder output.

13-29
CHUNG-YU WU

Major source of error is the loading of the reference resistor ladder by the
comparator bank.
Resistor ladder loading errors are of two types:
(1) "Transient error" associated with instantaneous ladder loading during a
single measurement;
(2) Long-term "recovery error" associated with errors at a new input level
after the ladder has been loaded for a long period by inputs at another
level.
If the capacitor bypassing is performed at the externally accessable ladder
midpoint tap,
transient impedance by a factor of more than 4.
Worst-case static loading which can't be bypassed makes recovery errors
the significant error source.
* All the errors considered above are of this type.
Typical 6-bit A/D converter Performance:
Power dissipation at 15 MHz clock, 20 pF/output.
5V

8V

convert mode

50mW

145mW

Tracking mode

45mW

130mW

3.2V reference

9mW

9mW

Input Cap.

8 pF

8 pF

Recom. Vref

3.2V

6.4V

On-chip Zener Reference

3.2V

6.4V

Input voltage source resistance

75

75

Accuracy 15MHz

1 LSB
2

1 LSB
2

20MHz

---

1 LSB

25MHz

---

1.5 LSB

13-30
CHUNG-YU WU

13-5.2 7-Bit CMOS Flash ADC for Video Applications

Ref.: IEEE J. Solid-State Circuits, vol. sc-21, pp. 436-440, June, 1986
Overall schematic:

VREF
TOP

D-Type
Output
Latch

Comparator
R/2 Banks
Latches

Overflow

127
R

D6

D5
R
64
R/2
Mid
Decouple
Cext
Capacitor
Bypassing

R/2

128 to
7 bit
Encoder
Logic

D4

D3

D2

D1
R
0
VREF
Bottom

D0

R/2

Analog
Input

Clock Buffer

R: Polysilicon resistor, 10 / bit

2m Poly-gate VLSI CMOS
Overall ship area: 135142 mil2

13-31
CHUNG-YU WU

Comparator and the primary latch

+VDD
OUTPUT

Load
Bias

OUTPUT
Q10

Q11

Q12

Q 13
Q14

Q16
Q3

Vbias

Q4

Q5
Analog
Input

Vbias

Reference
Input

Q6

Q1

Q2

Latch
I2Bias

Latch

Q8

Q9
I2Bias

IBias
Q7

Q15

-VSS

Gain: 18dB
Bandwidth: 40 MHz

Q10, Q13: Operated in linear region

with on-chip low-power
OP AMP and reference
loop.
Ro, fu.

Q5,Q6: Positive feedback to

form latch.

Q11, Q12: To limit the output swing

and

enable

the

comparator to recover
much faster from the
latched state.
The secondary latch is of the hysteresis type, because
(1) it can convert the limited logic swing of the primary latch to correct
CMOS logic levels.
(2) it can reduce the amount of hysteresis to ~ 100mV by setting "Latch"

13-32
CHUNG-YU WU

signal to High. Thus the latch always experiences an overdrive of 100

mV.
Avoid ambiguous state and increase the resolution time of the
comparators.
Reduce metastability error probability
Performance characteristics:
7-bit inherently monotonic
Accuracy: differential and integral

0.5 LSB.
- 1 LSB 5 MHz
2
: > 22 MSPS, 30 MSPS typically
: 5V 0.5V
: 1.5V~3.5V
: 350 mW
: - 40 o C to + 85 o C

Analog bandwidth

: -3dB 42 MHz;

Maximum sample rate

VDD
Input range
Power consumption (25MSPS)
Temp. range

13-5.3 CMOS 20 MS/S (Maga Samples /sec) 7-bit Flash ADC

Ref.: ISSCC 84, PP. 56-57, 315.
Nonsampling amplifier:
1

VDD

1
S1

S5

VDD
A

CA

S7

LATCH

S2

Sampling
Clock

S6

VDD

VDD
B

S3

S8
S4

CB

* Higher operating. frequency

13-33
CHUNG-YU WU

13-5.4 Metastability error

Ref.: IEEE JSSC, vol. 31, pp. 1132-1140, Aug. 1996, 7-b 80-MHz flash ADC
Metastability error: occurs in ADCs when undefined comparator outputs pass
through the encoder to the converter output bits.

VA < V REFi+1 0
0
0 i+1
1 i
1
VA > V REF 1

Thermometer code with

valid comparator outputs

0
VA < V REFi+1
0
i+1 0
Metastable
i X
VA ~ V REFi
state
i-1 1
1 VA > V REFi-1

Thermometer code with

metastable comparator

* Metastability error rate is an

exponential function of the
sampling frequency.
* It is nearly independent of
the input frequency.
* At 70-MHz sampling
frequeny, the metastability
error rate is ~ 10-7
errors/cycle.
7 errors per second
* Can be improved to < 10-12 errors/cycle.

13-34
CHUNG-YU WU

13-6 Two-Step Flash or Subranging ADC

Conventional two-step A/D converter:

+
SAMPLE
&
HOLD

VIN

COARSE
FLASH
ADC

FINE
FLASH
ADC

DAC

ANALOG
ADDITION

LATCH

DIGITAL
OUTPUT

Two-step A/D converter with single resister ladder:

VIN

Vin

MSB'S
TGS2

COARSE
COMPARATOR
NO. 16
COARSE
COMPARATOR
NO. 15
COARSE
COMPARATOR
NO. 14

TGC16

VREF
15

TGC15

15
TGC14

R15
15

"COARSE"
DECODER
/ENCODER

COARSE
COMPARATOR
NO. 1

LSB'S

R16

R14

COARSE
COMPARATOR
NO. 2

SAMPLE

TGS

SAMPLE

TGC2

TGC1

FC #14

R3

15

R2

15

R1

FC #15

15

*FINE*
DECODER
/ENCODER

FC #2

CLEAR
FC #1

VREF
"FINE"
COMPARATOR

13-35
CHUNG-YU WU

Two-Step Flash ADCs or Subranging ADCs with:

(1) Two Resistor (R) Ladders
* Need 2(2N/2-1) comparators & R tapes.
* Need high-performance op amp.
Nonlinearity caused by the mismatch of the two resister ladder.
High-performance op amp is not easy to be achieved (especially for 3 V
Vdd).
(2) Single Resistor Ladder
* Need 2N-1 R tapes.
* Need 2(2N/2-1) comparators.
As many R tapes as full flash type.
No op amp is required.

13-36
CHUNG-YU WU

13-6.1 Subranging (Two-Step Flash) ADCs

8-bit 50MHz CMOS Subranging ADC with Pipelined Wide-Band S/H
Ref.: IEEE JSSC, pp. 1485-1491, Dec. 1989.
Conventional subranging A/D converter:

Trade-offs in Subranging and Flash 8-bit ADC

Flash

Subranging

256

31

Clock cycles/conversion

Relative speed

0.5

Relative input loading

0.12

Relative power dissipation

0.2

Relative die size

0.4

Total comparators

Typ. Differential Linearity Error

0.4 LSB

0.3 LSB

Typ. Integral Linearity Error

0.7 LSB

0.5 LSB

* High accuracy is required only for the S/H circuit and the D/A subconverter.
(S/H is to reduce the effect of signal delay differences in the large-area
chip.)
* Very difficult to develop a high-speed (video) and high-accuracy MOS S/H
circuit.

13-37
CHUNG-YU WU

* The conversion rate degrades. (Pipelined structure may be used)

* The linearity of the complete converter depends on the accuracy of the gain
matching among the first A/D, the D/A, and the second A/D subconverters.
New structure: (4-bit conceptual structure)

Subranging A/D converter using combined DAC/subtraction

technique: (a) block diagram and (b) subranging process
* Combined DAC/subtraction Technique
* No current flows through the switches No degradation in linearity in
DAC
* Amplifiors's settling time < 2 ns

13-38
CHUNG-YU WU

8bit actual ADC:

Block diagram of 8-bit subranging A/D converter

* The 2nd ADC has a fifth bit reserved for digital correction of nonlinearity
caused by both offset voltages of the second S/H circuit and the subtractor
and nonlinear errors in the first A/D subconverter.
* The two S/H circuits and two A/D subconverters operate in a pipelined
manner High conversion rate ( 2).
* The resistor string has more than 10-bit accuracy.
Gain Matching

Linearity degration caused by gain mismatches in pipelined S/H

13-39
CHUNG-YU WU

Conventional MOS S/H:

SF:
* The switch opening time is influenced by input voltages severe
distortion.
* Poor linearity.
Integrator-type S/H:
* The same switch closing time.
* Close loop configuration enhances the linearity.
* Difficult to obtain a fast-settling speed that ensures 8-bit accuracy.
Imposed by the relatively high output resistance of the amplifier and the clock
feedthrough error of the MOS switch.

Conventional MOS S/H: (a) source follower type S/H,

(b) waveform of clock and switch opening time
deviation for source follower S/H, and (c) integratortype S/H
New S/H:
* Bandwidth-enhanced integrator-type S/H
circuit.
* CMOS transmission gate with dummy
transistor (clock feedthrough )
* Compensation
R
R
R
CC = F C H (1+ SW + SW ) pole-zero
RI
R1
RF
cancellation. Bandwidth.

Bandwith-enhanced integrator-type S/H

* CH=1 pF, Cc=1.2 pF, RF = RI = 1K, RSW = 100 8-bit, 50 MHz.

Tsettling = 12 ns ~ 8.5 ns for 2V step.

13-40
CHUNG-YU WU

Block diagram of pipelined S/H and subtractor

* The output of the subtractor is set to analog ground by closing the switch for
the limiter.

High-speed operational-amplifier circuit diagram

13-41
CHUNG-YU WU

Simulated linearity characteristics for S/H circuits

Comparator for the second A/D subconverter

* Comparators for the second A/D subconverter have an inaccuracy 1 LSB.
4
(3 mV at 3V input)
(FS)
* 100 MHz with a 7-8 mW power dissipation.

13-42
CHUNG-YU WU

Timing diagram for pipelined subranging A/D converter

Experimental results:
1 m CMOS, 5V single power supply, sampling rate 50 MHz.

Effective bits and gain as a function of analog input frequency

13-43
CHUNG-YU WU

13-6.2 10-bit 5-MSPS CMOS Two-Step Flash ADC

Ref.: IEEE JSSC, vol. 24, no. 2, pp. 241-249, Apr. 1989.
1. Classical two-step flash ADC
* Limited by matching between the MSB ADC and DAC transitions
* Limited by op-amp settling time (conversion rate)

2. New structure
* No OP amps.
* No gain block

13-44
CHUNG-YU WU

3. Circuit implementation

* Shared binary weighted

capacitor array for the
MSB ADC and DAC and
the LSB ADC.
mismatches

13-45
CHUNG-YU WU

4. ADC Performance

13-46
CHUNG-YU WU

13-6.3 The Proposed A/D Converter

1. Parallel processing with two 8-bit subconverters. (Time-interleaved ADC)
2. Two-step structure with single resister ladder.
3. Using 31 dynamic coarse and 15 fine comparators for 3V Vdd design.
(No op amps is required)
4. 1-bit digital error correction.

The proposed A/D converter with parallel processing architecture.

13-47
CHUNG-YU WU

The proposed 8-bit A/D subconverter.

The timing diagram of a 8-bit A/D subconverter.

13-48
CHUNG-YU WU

The circuit of the coarse comparator.

Fine comparator and its clock sequences.

13-49
CHUNG-YU WU

Intermeshed resistor reference ladder.

13-50
CHUNG-YU WU

The layouts and their equivalent circuits (a) with and (b) without separated
unit resistors.

(a)

Experimental Results:
Chip photograph of the fabricated A/D converter.

(b)

13-51
CHUNG-YU WU

A typical plot of the differential nonlinearity.

A typical plot of the integral nonlinearity.

13-52
CHUNG-YU WU

The FFT spectrum for a 85 KHz sine-wave input signal

The effective bits versus input frequency characteristics.

13-53
CHUNG-YU WU

Table 1 Major characteristics of the A/D converter.

Process:
Resolution:
Differential nonlinearity:
Integral nonlinearity:
SNDR(for 85KHz input):
Sampling rate:
Input dynamic range:
Power supply:
Power dissipation:
Active area:

0.8m CMOS
8bits
-0.4 to + 0.4 LSB
-0.6 to + 1 LSB
46.8 dB
50 MHz
0.5V to 2.5V
3V
100 mW
4950 um 3790 m

13-54
CHUNG-YU WU

13-7 Pipelined (Multistage) ADC

u Need m(2N/m-1) comparators R tapes.
u Need m op amps for S/H subtractors.
High-performance op amp is not easy to be achieved (especially for 3V Vdd).
Block diagram of a pipelined A/D converter

13-55
CHUNG-YU WU

Pipelined ADCs
13-7.1 A Pipelined 5-Msps 9-bit ADC
Ref.: IEEE JSSC, vol. 22, no. 6, pp. 954-961, Dec. 1987.
1. General pipelined ADC

2. Two-stage pipelined ADC

3. Prototype

13-56
CHUNG-YU WU

13-57
CHUNG-YU WU

OP AMP:

13-58
CHUNG-YU WU

Comparators:

4. Measurement results:

13-59
CHUNG-YU WU

13-7.2 A Pipelined 9-Stage Video-Rate ADC

Ref.: IEEE 1991 Custom Integrated Circuits Conference (CICC). pp. 26.4.126.4.4

DAC + +

SHA MDAC

13-60
CHUNG-YU WU

13-61
CHUNG-YU WU

13-7.3 A Single-Ended 12-bit 20 MS/s Self-Calibrating Pipeline ADC

Ref.: IEEE JSSC vol. 33, pp. 1898-1903, Dec. 1998.
Advantages: concurrent processing of analog signals
optimal speed and power dissipation
high speed and low power
Disadvantage: * Inherent passive component matching problem
hard to control and yield
self-calibration and correction technique
* Latency acceptable in most applications
1. The pipeline architecture
* CMOS SC implementation
conversion stage speed
feedback factor
(interstage gain)-1
1-bit/stage for power and speed
optimization.
simple calibration.

* Transfer characteristic:
The output residue voltage Vout
Vout = 2Vin + D Vref
D = +1 for 0 < Vin < Vref
= -1 for -Vref < Vin < 0
* Digital correction technigue:
Very attractive for submicron
CMOS (small chip area)

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* The "radix = 2" overrange stage

To correct residues up to 1 Vref
2
outside the nominal Vref range for
Vin.

Transfer characteristic:
Vout = 2Vin + 2 D Vref
D = +1

1 Vref < Vin < Vref

2

=0

1 Vref < Vin < 1 Vref

2
2

= -1

Vref < Vin < 1 Vref

2

Lower feedback gain for the overrange stage

maximum operating frequency
* Overall architecture only 3
overrange stages are used for
digital correction.

2. Self-calibration and correction algorithm

* Starting from the eleventh pipeline stage and working toward the MSB stage.
The rest of the stages (12-15) are not calibrated.
* For each calibration stage, the calibration consists of
(1) forcing an analog input value of 0V (differential)
(2) forcing the digital decision to the left and to the right of the transition.

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* The calibration coefficient

Memi = code_l - code_h
Vout = Vref

Code_l=0

Vout = -Vref

Code_h=0

Memi = 2 Vout Vin

one coefficient for regular

stage.
two coefficients for overrange
stage.
All the correction coefficients
are stored in 15 registers.
* All the digital correction is
performed in 16 bits, and the last 4 LSB's are truncated for the final 12-bit output
code.
* Global offset and full-scale error can be calibrated.
3. Implementation of Analog Blocks.
* The single-ended to differential input S/H:

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* Input common-mode fb amp.

* op amp
(telescopic op amp)

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4. Measurement results
DNL:

INL:

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Spectrum:

SNR & THD

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13-8 Folding and Interpolating ADC

Ref.: Johns & Martin, Analog IC Design, pp. 516-523.

13-8.1 Interpolating ADC

* The number of input amplifiers (or comparators as in flash ADC) attached
to Vin can be significantly reduced by interpolating between adjacent output
of these amplifiers.
A 4-bit interpolating ADC with interpolating factor of 4

* Transfer response of V1, V2a, V2b, V2c , V2 vs. Vin: Logic 1 = 5V, Logic 0 = 0V
Gain of input amplifier = -10
Latch threshold = 2.5V
More reference levels between V1 and V2: V2a, V2b, V2c .

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Possible transfer responses for the input-comparator

output signals, V1 and V2, and their interpolated signals

* If V1 and V2 are accurately linear between their own thresholds,

i.e. 0.25V < Vin < 0.5V
correct crossing points of the latch threshold.
linearity .
And the rest of the interpolated signal responses are of secondary importance.
* For fast operation, the delays of latches must be equalized by adding series
resistors.
* Interpolation can be implemented by R string, current mirrors or capacitors.

Adding series resistors to equalize delay times to the latch comparators

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13-8.2 Folding ADC

A 4-bit folding ADC with a folding rate of 4.

* The use of a folding architecture to reduce significantly the number of latch

comparators (2N in interpolating ADC).
* The use of analog preprocessing to determine the LSB set directly.
* Folding rate the number of output transitions for a single folding block as
Vin is swept over its input range.

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A folding block with a folding-rate of four. (a) A possible single-ended circuit

realization; (b) input-output response.

* 4-bit folding ADC architecture:

MSB 2-bit: flash
LSB 2-bit:
folding
LSB: V1, V2, V3, and V4 produce a thermometer code for each of the four
MSB regions.
* Examples: Vin:
0 1/4 V
Thermometer code: 0000, 0001, 0011, 0111, 1111
Vin:
1/4 V 1/2 V
Thermometer code: 1110, 1100, 1000, 0000
* Total number of latches: 8
as compared to 16 in flash ADC.
* No S/H is required.
* Folding blocks realized by BJT cross-coupled differential pairs as an example.
* Large input capacitance seen by Vin.
* The output signal frequency = input signal frequency folding rate
limits the practical folding rate used in high-speed converter.

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13-8.3 Folding and Interpolating ADC

A 4-bit folding A/D converter with a folding rate of four and an interpolate-by-two. (The
MSB converter would usually be realized by combining some folding-block signals.)

* Folding rate: 4;

Interpolation: 2

* V4 is a new inverted signal from V4.

* Latch number
Input capacitance
* Capable of > 100 MHz operation.
* Can be implemented in CMOS.

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13-8.4 A 400-Ms/s 6-bit CMOS Folding and Interpolating ADC

Ref.: IEEE JSSC, vol. 33, no. 12, pp. 1932-1938, Dec.1998
1. The structure of a folder with differential outputs.
* A practical folder has
5 amplifiers.

2. A 3-bit folding converter and its cyclic code:

* Folding rate N, full-scale
sinusoid
Folded signal frequency
N frequency Fin
2

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3. The block diagram of the 6-bit converter

Fig. 5 Block diagram of the 6-bit converter

4. The folder structure:

* Folding rate: 4
Interpolation: 2
* 16 comparators and 16 folders cyclic thermometer 5 LSBs.
* 5 amplifiers are used
* Two stages higher gm.
* Resistor load better transient performance.
* Output current mode speed .

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5. Practical folders:

(a)

(b)

Fig. 7 (a) The contribution of the fifth amplifier goes unused.

(b) This redundancy is used to reduce the number of preamplifiers

* Vx1 and Vx2 are fixed voltages generated by a single preamplifier shared
by all folders.
* Power dissipation .
6. Interpolation with current-mode folder signals

Fig. 8. Interpolation can be used to eliminate half or more of the folder blocks

Fig. 9. Interpolation with current-mode folder signals. A current split-infour block is shown on the right.

* The number of folders . 16 8

* Problems:

(1) It adds an extra node to the signal path, reducing the

bandwidth of the folder circuit.
(2) It does not work readily at low power supply voltages.

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* Improved circuit:
Merge the current division within the folder.

Fig. 10. The folder is modified to include current division. The modified amplifier
is on the right. A block diagram for a modified folder is also shown.

* Fast operation and low-voltage operation.

7. Comparator design
(1) First stage:

Fig. 12. The comparator core (a) tracking and (b) latching.

* Current-input voltage-output comparator.

* Resistor load.

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* Advantages:
(a) Currents are summed to drive the latch (i.e. Iin L + Iin R) The input
signal has very little effect after latching begins.
(b) Iin L and Iin R always flow from tracking to latching The folders are
little disturbed.
* Need the second-stage buffer and latch.
(2) Second stage:

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(3) Third stage to reduce metastability errors:

SR
latch

8. Complete ADC block diagram

The sync block: To suppress the delay mismatch between the coarse ADC and
the rest of the circuitry (i.e. the fine converter)

Fig. 16. (a) ADC block diagram with detail of coarse ADC. (b) Coarse ADC
waveforms

* MSB-Lo and MSB-Hi are offset by 1 Fs at either side of the MSB

8
transition voltage.
* If MSB-1 = 0, MSB = MSB - Lo
If MSB-1 = 1, MSB = MSB - Hi
* Can tolerate a relative offset of up to 1 Fs.
8

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9. Measurement results:

Fig. 18. SNDR versus input frequency at 400 Msample/s

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Fig. 19. Die photo

13-81
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13-9 Summary

16
[7]

[5]
Resolution (Bits)

15

[8]

[4]

14

[3]

13
[2]
12
[6]

[9]

11
10
9
8

[1]
10

30

600

620

13-81

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320 330
210
190
Conversion Rate (KHz)
Resolution versus sampling frequency plot of
recently reported CMOS audio A/D converters
50

13-82
13

12

11

Resolution (bits)

(35mW) (135mW)
T3, [20] [18], T2

(85mW)
T3 & T6,
[21]

*
[35] (195mW),*T2
[36] [22]
T2, T2,
(75mW) (135mW)

[17]
(350mW,
T2)

: 3.3V
: 3V
: 2V
: 2.5v
(900mW)
[19], T3

*
(76mW, T6)
[11]

T4&T5
T5
(135mW) (80mW) (1.1W, T3)
[23]
[25] [10]

*
[13]
(250mW, T1)

*
[16]
(200mW, T2)

T1: Full Flash

T2: Two-step flash or Subranging
T3: Pipelining
T4: Interpolating
T5: Folding
T6: Parallel
T7: Over sampling

*: 5V

*[34] (250mW), T3

[24], T3
(135mW)

10

CHUNG-YU WU

* [30] (166mW), T3
(200mW, T2)
[15] [33] (335mW), T3

[14]
(600mW, T2)

*
T4
(160mW)
[27]

T1, [28]*
(307mW)

(225mW)
[29], T5

T1
(110mW)
[26]

*[12]

[31]
(200mW)
T4&T5

(400mW, T1)
5
10

20

30

40

50

60
70
80
Conversion Rate (MHz)

90

T1
T3&T7
(190mW) (225mW)
[32]
[37]

125

175

200

400

500

13-82

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Resolution versus sampling frequency plot of recently reported CMOS video A/D converters

300

13-83
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[1]

H. Ondera, T. Tateishi, and K. Tamaru, "A cyclic A/D converter that does not require ratiomatched components," IEEE J. Solid-State Circuits, vol. 23, pp. 152-158, Feb.1988.

[2]

P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, " A ratio-independent algorithmic analog-todigital conversion technique," IEEE J. Solid-state Circuits, vol. SC-19, pp.828-836, Dec.
1984.

[3]

H. S. Lee, " A 12-b 600Ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J.
Solid-Dtate Circuits, vol. 29, no. 4, pp. 509-515, Apr. 1994.

[4]

Shu-Yuan Chin and Chung-Yu Wu, "A ratio-independent and gain insensitive algorithmic
analog-to-digital converter," 1993 IEEE International Symp. on Circuits and Systems,
Chicago, U.S.A., pp.1200-1203, May 3-6, 1993.

[5]

M. de Wit, K. S. Tan, R. K. Hester, " A low-power 12-b analog-to-digital converter with onchip precision trimming," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 455-461, Apr. 1993.

[6]

G. Yin, F. Stubbe, and W. Sansen, " A16-b 320-KHz CMOS A/D converter using two-stage
thrid-order noise shaping," IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 640-647, June
1993.

[7]

B. Ginetti, P. G. A. Jespers and A. Vandemeulebroecke, " A CMOS 13-b cyclic RSD A/D
converter," J. Solid-State Circuits, vol.27, no. 7, pp.957-964, July 1992.

[8]

H. S. Lee, D. A. Hodeges, and P. R. Gray, " A self calibrating 15-bit CMOS A/D converter,"
IEEE J. Solid-State Circuits, vol. SC-19, pp.813-819, Dec. 1984.

[9]

T. Ritoniemi et al, " A stereo audio sigma-delta A/D converter," IEEE J. Solid-State Circuits,
vol. 29, no. 12, pp.1514-1523, Dec.1994.

[10] C. S. G. Conroy, D. W. Cline, and P. R. Gray, " An 8-b 85-Ms/s parallel pipeline A/D
converter in 1-um CMOS," IEEE J. Solid-State Circuits, vol.28, no. 4, pp.447-454, Apr. 1993.
[11] Shu-Yuan Chin and Chung-Yu Wu, "A 3 V 8-bit 50-Msample/s A/D Converter," submitted to
IEEE J. Solid-State Circuits.
[12] H. Reyhani and P. quinlan, " A 5V 6-b 80Ms/s BiCMOS flash ADC," IEEE J. Solid-State
Circuits, vol. IEEE J. Solid-State Circuits, vol. 29, no. 8, pp.873-878, Aug. 1994.
[13] M. J. M. Pelgrom, A. C. J. V. Rens, M. Vertreg, and M. B. Dijkstra, " A 25-Ms/s 8-bit CMOS
A/D converter for embedded application," IEEE J. Solid-State Circuits, vol.29, no. 8, pp.879886, Aug. 1994.

13-84
CHUNG-YU WU
[14] M. Ishikawa and T. Tsukahaara, "An 8-bit 50-Mhz CMOS A/D converter," IEEE J. SolidState Circuits, vol. 24, no. 12, pp. 1485-1491, Dec. 1989.
[15] B. Razavi and B. A. Wolley, "A 12-b 5-Msample/s two-step A/D converter," IEEE J. SolidState Circuits, vol. 29, no. 12, pp.1667-1678, Dec. 1992.
[16] A. G. F. Dingwall and V. Zazzu, " An 8-MHz CMOS subranging 8-bit A/D converter," IEEE J.
Solid-State Circuits, vol. Sc-20, no. 6, pp. 1138-1143, Dec.1985.
[17] J. Doernberg, P. R. Gray and D. A. Hodges, " A 10-bit 5-Msample/s CMOS two-step flash
ADC," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 241-249, Apr.1989.
[18] M. Ito et al., " A 10bit 20 Ms/s 3V supply CMOS A/D converter," IEEE J. Solid-State
Circuits, vol. 29, no. 12, pp.1531-1536, Dec. 1994.
[19] M. Yotsuyanagi, T. Etoh, and K. Hirata, " A 10-b 50-MHz pipelined CMOS A/D converter
with S/H," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 292-300, Mar. 1993.
[20] T. B. Cho, P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipelined A/D converter," IEEE J.
Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
[21] K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstos, "An 85 mW, 10b, 40 Msample/s
CMOS parallel-pipelined ADC," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 173-183,
Mar. 1995.
[22] M. Yotsuyanagi et al., "A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D
converter," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp.1533-1537, Dec. 1995.
[23] B. Nauta and A. G. W. Venes,"A 70-Ms/s 110mW 8-b CMOS folding and interpolating A/D
converter," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1302-1308, Dec. 1995.
[24] P. C. Yu and H. S. Lee, "A 2.5-V, 12-b, 5-Msample/s pipelined CMOS ADC," IEEE J. SolidState Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996.
[25] A. G. W. Venes and R. J. van de Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D
converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31,
no. 12, pp. 1846-1853, Dec. 1996.
[26] S. Tsukamoto et al., "A CMOS 6-b, 200 Msample/s, 3 V-supply A/D converter for PRML
read channel LSI," IEEE J. Solid-State Circuits, vol.31, no. 11, pp. 1831-1836, Nov. 1996.
[27] R. Roover and M. S. J. Steyert, "A 175 Ms/s, 6 b, 160mW, 3.3 V CMOS A/D converter,"
IEEE J. Solid-State Circuits, vol.31, no. 7, pp. 938-944, July 1996.

13-85
CHUNG-YU WU
[28] C. L. Portmann and T. H. Y. Meng, "Power-efficient metastability error reduction in CMOS
flash A/D converters," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1132-1140, Aug. 1996.
[29] M. P. Flynn and D. J. Allstot, "CMOS folding converter with current-mode interpolation,"
IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1248-1257, Sep. 1996.
[30] D. W. Cline and P. R. Gray, "A power optimized 13-b 5 Msamples/s pipelined analog-todigital converter in 1.2/spl mu/m CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp.
294-303, Mar. 1996.
[31] M. P. Flynn and B. Sheahan, "A 400-Msample/s, 6-b CMOS folding and interpolating ADC,"
IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1932-1938, Dec. 1998.
[32] S. Tsukamoto, W. G. Schofield, and T. Endo, "A CMOS 6-b, 400-Msample/s ADC with error
correction," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1939-1947, Dec. 1998.
[33] J. M. Ingino and B. A. Wooley, "A continuously calibrated 12-b, 10-Ms/s, 3.3-V A/D
converter," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1920-1931, Dec. 1998.
[34] I. E. Opris, L. D. Lewicki, and B. C. Wong, "A single-ended 12-bit 20 Msample/s selfcalibrating pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 18981903, Dec. 1998.
[35] H. van der Ploeg and R. Remmers, "A 3.3-V, 10-b, 25-Msample/s two-step ADC in 0.35-um
CMOS," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1803-1811, Dec. 1999.
[36] B. P. Brandt and J. Lutsky, "A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5
effective bits at nyquist," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1788-1795, Dec.
1999.
[37] I. Mehr and D. Dalton, "A 500-Msample/s, 6-bit nyquist-rate ADC for disk-drive readchannel applications," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 912-920, Dec. 1999.

14-1
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CH 14. MOS Switched-Capacitor Filter Design

14--1 Preliminary Considerations
14-1.1 Classification of systems and filters
1. Continuous-time, discrete-time, and sampled-data systems

Ampt.

Input x(t)

Ampt.

Input x(kt)

Loss

Ampt.

Input x(kt)

Loss
t

Output y(t)

Output y(kt)

Output y(kt)

continuous-time system
e.q.: analog Filter

k: integer

sampled-data system
e.q.: SCF

discrete-time system
e.q.: digital filter

difference equations

differential equations

2. Tine-invariant systems and causal systems

T.I.

: x(kt) y(kt) > x[(k-n)T] y[(k-n)T] for any x(kt) and n.

Causal : x(mt) => y(kT)=0 for k<m

3. Filter types:
(1) Low-Pass(LP)

H(s)=

K p

H ( j )
dB

-N*20dB/decade
N: order

S 2 + ( p / Q p ) S + p2
Ideal

(biquad)
Two complex poles (LHP)

14-2
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(2) High-Pass(HP)
KS 2
H(s)= 2
S + ( p / Q p ) S + p2
Two complex poles(LHP)
Two zeros at S=0
H ( j )
3) Band-Pass(BP)
H(s)=

K ( p / Q p ) S

p
Qp

dB

-N*10dB/decade
N: order

-3dB

S 2 + ( p / Q p ) s + p2

+N*10dB/decade
N: order

center freq. gain: k

center freq. p
Two complex poles (LHP)
One zeros at S=0

s1

p1

p2

s2

H ( j )

4)Band-Reject(BR)
K ( S 2 + z2 )
H(s)= 2
S + ( z / Q p ) s + p2

dB

p=z
Two complex poles(LHP)
Two imaginary zeros

p>z High-Pass Notch filter (HPN)

p<z Low-Pass Notch filter (LPN)
(5)Low-Pass Notch (LPN)
(6)High-Pass Notch
H ( j )

H ( j )

dB

dB
0dB

0dB

p z

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(7)ALL-Pass (Delay Equalizer)

H(S)=

S 2 ( p / Q p ) S + p2
S 2 + ( p / Q p ) S + p2

0dB

Gain
-180o

Two complex poles (LHP)

Two complex zeros (RHP)
mirror-imaged

phase
p

14-1.2 Sampling Process

ideal impulse sampling:
S(t)= S (t)=

multiplier
x(t)

S (t k )

xd(t)

k =

: sampling period
xd(t)=x(t)S (t)=x(t)

remember:

(t k )=

K =

x(t ) (t k )

k =

S(t)=S(t) for ideal

impulse sampling

(t k )dt = 1 (t k ) =0 for t k

> xd(t)= x(k ) (t k )

k =

Fourier transformation of S (t): SF(t)= ck e jk st

k =

Where Ck

s(t) e jk st dt=

>xd(t)=x(t)SF(t)= Ck x(t )e jk t
s

k =

F[xd(t)]=F[ Ck x(t )e

jk s t

k =

= C k X(j-jks)

]=

C F [ x(t )e

k =

jk s t

where F[x(t)] X(j), k=integer

k =

base-band spectrum

14-4
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X(j)

Aliasing:
introduces an
ambiguity into
X(j-jks)
and prevents
the eventual
recovery of
X(j)

sc

c
X(j-jks)

c s
X(j-jks) no

s<2c

2c

s>2c

aliasing

s 2
c

2c s

Sampling Theorem:
A function x(t) that has a Fourier spectrum X(j) such that X(j)=0 for

s 2 is uniquely described by a knowledge of its values at uniformly spaced

time instants, instants apart( = 2 / ws )
2c: Nyquist rate.
Anti-aliasing filter is required.
Reconstruction filter is also required to recover x(t).
spec
H ( j )

The smaller the s-2c (TB),

the higher the filter order!

Transition
band

Stop
band

Pass
band
s+c c

s-c

s-2c

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Finite -Pulse Sampling (non-ideal sampling):

a
2

a
2

Sp(t)= [u (t k ) u (t k + )] a>0
k =

Ck=

a
2
a

Sp(t) e jk st dt
e jk t dt =
s

a Sin(k s a / 2
k s a / 2

2 3 4

Now, we have sin / envelope onto X (j-jks)

xd(t)

k s a / 2

Pulse Amplitude Modulation

(PAM)

3 4

14-1.3 Z-Transformation

xd(t)= x(k ) (t k )
k =

Laplace Transformation> Xd(s)=L[xd(t)]= x(k )e ks

k =

Let z=es
j

S=j z=e

> X(z)= X (k )z k two-sided z-transform

k =

X(z)= X (k )z k

one-sided z-transform

k =0

example 1: x(t)=u(t)>x(k ) = 1 >X(z)= Z k =

K =0

1
1 z 1

z >1

example 2: x(t)=e-atu(t)>x(k ) = e ak >X(z)= e -akzz-k=

k =0

1
1 e

z 1

for z >e-a

For single input/output, linear, time-invariant, sampled data (or discrete-time)

system:
N

n =1

n =0

y(k ) + bn y[(k-n) ] = an x[(k-n) ]

M.N: non-negative integers

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Two cases:(1) bn = 0 for all n > nonrecursive system

M+1 tap transversal filter
Finite-Duration Impulse Response(FIR)Filter
(2) bn 0 for n 1 > Nth-order recursive system
Infinite Impulse Response(IIR) Filter
z-transform:
N

n =1

n =0

Y(z)(1+ bn Z n ) =X(z) a n z n
M

Y ( z)
H(z)=
=
X ( z)

a
n =0
N

z n

1 + bn z

pulse transfer function

n

n =1

ao (1 1 Z 1 )(1 2 Z 1 )......(1 N Z 1 )
=
(1 1 Z 1 )(1 2 Z 1 )........(1 N Z 1 )

z=i: poles
z=i: zeros

Mapping between Z-plane and S-plane:

z=es s=+j

=>

z=e ej

For s>20, the base-band response X(j) over the range-

sufficient to determine X(j) for all .

s
s / 2 is
2

s
s / 2 , << => all Z-plane Z =
2

3
s s , << => overlap on Z-plane Z = 3
2
2
s
3
s , << => overlap on Z-plane Z = 3
2
2

* =1, << => a straight line from z=0 to z= with angle 1

* j axis => =0 => z =1 unit circle
*>0

z >1 for all => RHP outside the z = 1 circle

*<0

z <1 for all => LHP inside the z = 1 circle

14-7
CHUNG-YU WU

* S=0

z=1

; =0 <<+ > Real Z axis (positive)

j

First-order transfer function:

H(z)=

1
Z=a is the pole
1 az 1

h(k) k=0, 1, 2, 3,.

z=a=eej
(1)a>1, diverging
unstable
(2)a=1 sequence of 1's unstable
stable
(3)a 0 a<1
(4)1<a 0

stable region
ImZ

(5)a=1
(6)a<1

unstable

z=ej

2
1

Ro Z
Z =1

G()=20log[ H (Z ) z=ej ] dB
Im H ( Z )

stable <0, =
k=k
unstable

()=tan-1 Re H ( Z )

rad

magnitude
phase

The magnitude and phase can be determined graphically in the same way as
those determined from the s-plane poles & zeros.

14-1.4 Sample and Hold Circuit

Zero-order hold or S/H function:
Ho(s)=

1 e s
s

sin( / 2)

Ho(j)=e-j/2 / 2

14-8
CHUNG-YU WU
h0(t)

X d ( j )

2 S

1/

H 0 ( j )

X r ( j )

+ C

2 S

Impulse response

ho(t)= u(t)- u(t-)

H O ( jw)

S
2 S

2 S

x(t)

xr(t)

x(k)
xr(t)=x(t) h0(t)

* may serves as a reconstruction circuit

Xr(j)=Xd(j)Ho(j)
* The different between Xr(j) & Xd(j) at c can be eliminated by setting
s/c>>1.

14-2 Switched-Capacitor Network System

General Switched-Capacitor Network (SCN):
ideal capacitors, ideal voltage-controlled-voltage sources (VCVS's), ideal switches
& sampled-data voltage inputs.
VCVS: freq. indep. gain amps or infinite gain OP amps.

* Typically, the sampled-data voltage input is only single, not multiple.

* The input may be a continuous one.
* The effects of non-ideal switches, non-ideal OP amps, & non-ideal cap. should be
considered as & second order effects.

14-9
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Block diagram:

(S/H)i

Continuous
Anti-aliasing
Filter

SwitchedCapacitor
Network

Continuous
Reconstruction
Filter

(S/H)o

Switched-Capacitor Network
(Two-phase clock) (can be multi-phase)
General symbols:
e

V1 ( kT )

V2 ( kT )

V1 (kT )

V2 (kT )

V1 (kT )

V2 ( kT )

even clock

Tc
Tc

Tc<T
to avoid overlapping
of e and

1T

2T

3T

odd clock
Tc

: sampling period

Tc

=2T

* Generally, SCN is time-variant since the network topology is different in the case of
e and . However, if we separate the input/output sampled-data voltage into one
even component and one odd component and separate the whole SCN into one
even part and one odd part, then we have two time-invariant networks coupled
together. Analysis thus can be performed.

14-10
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Sampled-Data Waveforms
1. Return-to-zero waveforms

va

va

1T

0T

V (t )

2T
e

4T

3T

5T

0T

va

1T

2T

3T

4T

5T

1T

2T

3T

4T

5T

Va (t )

Vb (t )

0T

V (t )

Va(z)=Vae (z ) + Va0 ( z ) = Vae (z )

Va0 ( z ) =0

Similarly, we have Vb(z)= Vbe (z ) +Vb0 ( z ) = Vb0 ( z )

Vbe (z ) =0

2. Full-clock-period (Full-cycle) sample-and-hold waveforms

vc

vc

vc (t)

1T

2T

3T

4T

5T

V (z)=Z

1
2

2T

3T

4T

5T

1T

2T

3T

4T

5T

Vc(z)= Vce (z)+ Vc0 (z)

0
c

1T

Vce (z) (Q Vc0 (kT)= Vce [(k-1)T])

Similarly, we have Vd(z)= Vde (z)+Vd0 (z)

14-11
CHUNG-YU WU

e
d

1
2

V (z)=Z Vd0 (z)

V (t )

or

vc , vd

Full-cycle S/H circuit

14-3 Filter Design Process

1. Specification
(1) Low-Pass Filter
Specification:
H ( j )

TransitionBand
TB

Gain
dB

Start
S : PB _ ripple
Specification

S
Stopband
SB

Passband
PB

SB
attenuation
No

O S
Cutoff frequency

Actual filter response

Stopband frequency

Satisfied
?

Yes
Approximation

Satisfied
?

No

Yes

Realization

delay
sec

Satisfied
?

Yes

Stop
actual delay function

No

14-12
CHUNG-YU WU

(2) Band-Pass Filter

SB H

SP

TB L

SL

CL

PB

TB H

CH SH

2.Approximation
(1) Classical approximation
a. Butterworth
b. Chebyshev
c. Elliptic
d. Bessel
(2) Modern approximation
3.Realization
Two methods:
(1) Realization of the biquad (2nd order filter)and the first-order filter>cascade
or couple them to form a high-order filter.
(2) Realize H(s) using LC network>replace L by some integrated-circuit
simulator or simulate the LC network using integrators.
* Low-sensitivity, high-performance

14-13
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14-4 SC Integrators via OP AMPS

14-4.1 SC Inverting Integrator

o(e): Vc1=0
e(o): Vc1=V1 -V2
Q=C1(V1-V2)

e ( o )

V1

V V2
V V2
Q
i = C1 1
= C1 f (V1 V2 ) 1
T
T
R
1
f: clock frequency
>R=
C1 f

VC1

e ( o )

V2

C1

o ( e )

o ( e )

f=100KHz, C1=10PF

>SC simulated positive resistor

> R=1M

Switch realizations:

o ore

o ore
o ore

or

+ V DD

VSS

VSS
o ore

E/D NMOS

The inverting SC integrator

vin

Operation:
(1)o phase

vout

vin

e
o

C1

C2

vout

14-14
CHUNG-YU WU

C2

+
+

vin

C1

vout

(2)e phase
+
+
+
+
+
+

vin

C1

C2

vout

e
n 1

n +1

t
vin
+ 1V

t
vout
0V

vout (Tn )

{
vout (Tn 1 )

{
C1
(1V )
C2

vout (Tn+1 )

t
{

14-15
CHUNG-YU WU

"Ideal OP AMP"
Vout(Tn)=Vc2(Tn)=Vout(Tn-1)=>

=>

C1
Vin(Tn)
C2

Vout (Tn ) Vout (Tn 1 )

C
1
= 1 Vin (Tn ) =
Vin (Tn )
T
TC 2
R1C 2
d
1
1
1
V
Vout =
Vin =
Vin =
1
1 in
dt
R1C 2
C
2
C2
(
)( )
C1 f
C1 f
High-precision integrator time constant RC=

C2 1
C1 f

Z-domain Expression:
Vout (z)=Vout(z)Z-1
>H(z)

C1
Vin(z)
C2

Vout ( z )
(C C )
= 1 21
(1 Z )
Vin ( z )

Backward Euler Transformation: S

H(S)=

1 Z 1
T

1
1
=
(C 2 / C1 )TS
R1C 2 S

Parasitic-Free structure:

vin
C P1

C1

C P 2 C P3

e
CP4

C2

C P5

vout
C P6

14-16
CHUNG-YU WU

14-4.2 Non-inverting SC Integrator

e(o) : Vc1=+V1
o(e) : Vc1=-V2
Q=C1(-V1-V2)
V + V2
Q
= i = C1 1
T
T

i
e ( o )

CV
+V
If V2=0 >i= 1 1 = 1
T
R
1
T
> R= =
C1
C1 f

VC1

V1

o ( e )

V2

C1

o ( e )

e ( o )

> SC simulated negative resistor!

The non-inverting SC integrator:

vin

vout

vin

e
o

o
C1

Operations:
(1)e phase

C2

vout

(2) o phase

C2

vin

+
+

C1

Vout (Tn)=Vout(Tn-1)+

>

>

vout

vin

C1
Vin (Tn1 )
C2

d
1
Vout =
Vin
dt
R1C 2
Vout
1
1
=
(s) H (s) =
Vin
R1C 2 S C 2 1
S
C1 f

+
+

C1

C2

+
+

vout

14-17
CHUNG-YU WU

Z-domain expression:
C1
)
Vout ( z )
C2
=
H(z)
Vin ( z ) 1 Z 1
Z 1 (

Forward Euler Transformation: S

1

H(s) +
(

C2
)TS
C1

=+

1 Z 1
TZ 1

1
R1C 2 S

Simpler non-inverting integrator!

14-5 Fully Differential-Type SC Integrators Using OP AMPs.

e
V BIAS

vin

V BIAS

vin

C
+

vout

vout

C
C

* Better noise rejection

* Better CMRR and PSRR
* Better Frequency response
* Better slew rate
** More components (switches, capacitor, OP AMPs)
** Thermal noise due to the added components and switching operations.
** Need common-mode feedback or common-mode bias circuit

14-18
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14-6 SC Differentiators Using OP AMPs

R
C1

Vin

Vout

Inverting:

o
C

Vin

C1

Vout(Tn)=Vout' (Tn)=
>H(z)=

V'out

Vout

C1
[Vin (Tn ) Vin (Tn 1 )]
C

C1
(1-Z-1)
C

Backward-Euler Transformation: S
H(S)=-S

C1
C 1
T = S 1 = SRC1
C
C f

1 Z 1
T
1
R=
cf

Noninverting:

Vin

C1

CC

CC

Vout

14-19
CHUNG-YU WU

o
2

C1

v out

v out

H(z)=+

C1
(1 Z 1 )
C

o
Differential-Type SC Differentiator:

o
vin

vin

e
e

C1
C1

C
+

vout

v out

o
Characteristics of SC differentiators:
1. Parasitic-free structure.
2. No dc instability problem as in SC integrators.
3. No high-frequency-noise problem as in continuous-time differentiators.
4. Can be used to design filters as SC integrators.
Ref: IEEE JSSC vol.sc-24, pp.177-180, 1989.

14-20
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14-7 The Design of SC Biquads (Second-Order Filter)

H(S)=

(K 2 S 2 + K 1 S + K o)

o
S + 02
Q

S2 +

Vout (s)
Vin (s)

14-7.1 Low-Q SC Biquads

Step 1: Flow diagram generation.
S2Vout=-[K2S2+K1S+Ko] Vin(o
1
S

>Vout=- [(K1+K2S)Vin+(

S
2
+ 0 ) Vout
Q

Wo
) Vout+ o V1)
Q

1
S

where V1= [(Ko/o) Vin+o Vout]

0

Vin
K0

0 Q

1
S

Vout

V1

0
K1 + K 2 S

Step2: Active-RC design

CA = 1

Vin

K0

Q 0

0
1

+
1
K1

K2

CB = 1

Vout

14-21
CHUNG-YU WU

Step 3: SCF
C2
CA=1
2
Vin

C4

C1

C3

OP1
+

C1'

CB=1

OP2
+

Vout

C1"

C1 = T * Ko/o= Adc * o * T= Adc

1
x

Adc

Ko

C2 = C3=o * T=

1
x

C4 = (o * T/Q)=

C
1
Q
= A (not suitable for high Q)
>
Qx
oT C 4

C1'= K1 * T =K1
C1" = K2
1
CA/C2=
oT
X=

1
oT

o x

> fo=

fs
fo: center (cutoff) frequency
2x

Step 4: refinement
Z-domain block diagram (If the accuracy is not good, change to Z-domain diagram)
-C2Z-1
C4
Vin

-C1Z-1

-1/CA

C3

1-Z-1
C1'+C1"(1-Z-1)

-1/CB
1-Z-1

Vout

14-22
CHUNG-YU WU

C1" = a0
C1' = a2-a0
C1 = 1/C3 * (a0+ a1+ a2)=

1
(2C1"+C1'a1)
C3

C4 = b2 -1
C2 * C3 = b1 + b2 + 1
C2=C3
In this diagram, each op-amp and its feedback capacitor (CA or CB) is replaced by
its voltage-to-charge transfer function.
Qout ( z )
V ( z) C
1 / Cf
=
= out
1
1 z
Vin ( z )
Vin ( z )
Here Cf is the feedback capacitor.
Similarly,
C * (1-z-1) for an unswitched capacitor (e.g. C1")
C
for a non-inverting capacitor (C1', C3, C4)
-1
for an inverting capacitor (C1, C2)
-C * z
From the block diagram, the exact transfer function is
Vout ( z )
(C1 '+C1 " ) z 2 + (C1C3 C1 '2C1 " ) z + C1 "
=
Vin ( z )
(1 + C 4 ) z 2 + (C 2 C3 C 4 2) z + 1
As compared to H(z) specifications, the capacitances can be determined.
a 2 * z 2 + a1 * z + a0
H(z) = b2 * z 2 + b1 * z + 1
TYPES
L-P CASE
B-P CASE
H-P CASE
NOTCH CASE

COEFFICIENTS
C1'=C1"=0
K1=K2=0 a0=a2=0
C1=C1"=0
K0=K2=0 a0=0,a1=-a2
C1=C1'=0
K0=K1=0 a0=a2= C1'=0
K1=0

a2=a0

a1
2

14-23
CHUNG-YU WU

14-7.2 High-Q SC Biquads

0
K1
0 S

Vin

S Q

-1 S

K0
0

-0
1

Vout

1
S

Vout = [K2SVin0V1]

V1

K2S

-1 S

1
S

Where V1= [(
2. Active-RC design

K0

K1

S )Vin + ( 0 +

S
)Vou t ]
Q

1
Q

K1

Vin

CA = 1

0
CB = 1

K0

OP1

Vout

OP 2

K2

3. SCF
C2

1
C1

C4

'

CA = 1

vin

C1

CB = 1

C1

''

C3

vout

14-24
CHUNG-YU WU

C1=K0 T/0 = (

K0

) oT = Adc 0T

C2 C3 0T
C4 1

(instead of

Q
)
0T

C1' K1/0
C1" K2
4. Z-domain block diagram of a high-Q biquad:
C2

+
''

C1 (1 Z 1 )

Vin

C1

C 4 (1 Z 1 )

+
C 3 Z 1
1 CA
1 Z 1 V1

1 CB
1 Z 1

''

C1 (1 Z 1 )

C1 " Z 2 + (C1C3 + C1 ' C3 2C1 " ) Z + (C1 "C1 ' C3 )

H(Z)=
Z 2 + (C 2 C3 + C3C 4 2) Z + (1 C3C 4 )
Choose C2=C3
Coefficient matching:
C1"=

a2
b2

C1'=(C1"-

ao
a ao
) / C3 = 2
b2
b2 c3

C1=(a1/b1-C1'C3+2C1")/C3=(a0+a1+a2)/(b2c3)
C4=(1-

1
) /C3
b2

C32=C22=(b1/b2-C3C4+2)=(b1+b2+1)/b2

Vout

14-25
CHUNG-YU WU

14-7.3 Design Examples

Example 1: Low-Q Lowpass SCF Biquad

C2

C4

CA

vin

C1

CB

H (S ) =

CA=CB=6.3 C1=4

C3

vout

4
S 2 + 1.2 S + 1

f
s
f =
c 2 C

C2=1 C3=1 C4=1.2

fc: CENTER FRE.

fs: SAMPLING FRE.

Example 2: Low-Q Bandpass SCF Biquad

C2

C4
CA

vin

CB

C3

'
1

vout

CA=CB=6.3 C1'=2

C2=1 C3=1 C4=1.2

H (S ) =

4
S 2 + 1 .2 S + 1

f
s
f =
c 2 C

fc: CENTER FRE.

fs: SAMPLING FRE.

14-26
CHUNG-YU WU

Example 3: High-Q Low-pass SCF Biquad

C2

1
2

C1

Vin

CB

C3

2
1

C4

CA

H (S ) =

CA=CB=6.3 C1=4

Vout

4
S
S2 +
+1
5.25

f
s
fc =
2 C

C2=1 C3=1 C4=1.2

A
fc: CENTER FRE.
fs: SAMPLING FRE.

Example 4: High-Q Band-pass SCF Biquad

C2

Vin

1
2

C'1
C4

CA

2
1

CA=CB=6.3 C '1=2

C2=1 C3=1 C4=1.2

CB

C3

2
1

1
2

Vout

H (S ) =

2S
S 2 + 1.2 S + 1

f
s
fc =
2 C

A
fc: CENTER FRE.
fs: SAMPLING FRE.

14-27
CHUNG-YU WU

Frequency response of low-Q Low-pass SCF biquad

CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz

CALCULATED

COMPUTED BY SWITCH CAP

EXPERIMENTAL

14-28
CHUNG-YU WU

Frequency response of low-Q Band-pass SCF biquad

CALCULATED

CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
COMPUTED BY SWITCH CAP EXPERIMENTAL

14-29
CHUNG-YU WU

Frequency response of High-Q Low-pass SCF biquad

CALCULATD

CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
COMPUTED BY SWITCH CAP EXPERIMENTAL

14-30
CHUNG-YU WU

Frequency response of high-Q Band-pass SCF biquad

CALCULATED

CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
COMPUTED BY SWITCH CAP EXPERIMENTAL

14-31
CHUNG-YU WU

14-8 First-Order SCFs

Ha(s)=

K1 S + K 0
S + 0

H(z)=

a1 z + ao
b1 z + 1

1. Flow diagram
0
Vin

K0

-1/S

Vout

K1S

2. Active-RC design
1/0

CA=1

1/K0
Vin

Vout

K1

3. SCF
1
C2

C1 K1
C1' TK0
C2 0T
fc=

fs
2x

C'1

1
2

2
CA

Vin

C1

Vout

14-32
CHUNG-YU WU

4. Z-domain block diagram

H(z)=

Vout
(C + C1 ' ) z C1
= 1
Vin
(1 + C 2 ) z 1
C'1

Vin

C1(1-Z-1)

C2

-1 / CA
1 - Z-1

Vout

14-9 Switched-Capacitor Ladder Filters

14-9.1 Approximate Design of SC Ladder Filters
(1) Third-order low-pass filter without finite transmission zeros
RS

-V1=
-I2=

1 Vin V1
(
I2 )
SC1
RS

1
(V1 V3 )
SL2

V3=

Loss

Vin

I2

C1

V3
3

C3

+
RL

Vout
-

V
1
( I 2 + 3 )
SC 3
RL

(no loss)
transmission zero
=>

L2

V1

LCR prototype circuit

Vin

1/RS

-1
SC1

-V1
-1

+1
-1
SL2

-I2

p
Loss response

+1

+
-1

-1
SC3

1/RL

Flow diagram

+V3

14-33
CHUNG-YU WU
RS

RS

Vin
1
-I2

Active-RC realization

C1
-V1

-1

L2
-

CS

Vin

1
C3

CS

-1

C1
1

Vout

+
C

1
C

RL

L2

SCF

C
C3
1

1
Vout

SCF realization equations:

C=

T
R

=> Cs

T<<1

CL

T
Rs

CT
CL T / RL
Due to the approximation made in finding C values, error still exists which may be
refined by the z-domain analysis.

14-34
CHUNG-YU WU

(2) Third-order low-pass filter with transmission zeros

a1=-a2=

-V1=
-I2=

1
L2 C 2

Vin V1

1
+

sC
V
I
2 3
2 ,
s (C1 + C 2 ) Rs

1
[V1 V3 ],
sL2

+V3=

V3
1

sC 2V1 I 2 +
s (C 2 + C 3 )
RL

LCR Prototype circuit:

RS

Vin

V1

C2

IC2

L2

I2

C1

V3
3

C3

+
RL

Vout
-

1/RS

Vin

1/RS

-1

-V1

s(C1+C2)

Flow diagram:

SC2

-I2

-1

-1
SL2

-1
SC2

-1
S(C2+C3)

1/RL

+V3

Vout

14-35
CHUNG-YU WU

RS

Active-RC
Realization:

CA=C1+C2
RS
Vin

-V1

-RI2
C2

-R

CB= L2/R2

C2

+
R
CC=C2+C3

-R

Vout

V3

RL

CS
Vin

CS

2
1

SCF:

CA
1

1
C

CB

1
C2

C2

Cs T / Rs,

CA=C1+C2,

CC

C T,
2

CB=L2,
Cc=C2+C3,
CL T / RL .

CL
Vout

14-36
CHUNG-YU WU

(3) Fourth-order Bandpass filter

C2

RS

Vin

V1

I2

L2

V3

I1

I3
L3

L1

C1

+
C3

Vo

RL

LCR Prototype Circuit

1/RS

Vin

1/RS

-1

-V1

s(C1+C2)

-V1=

-I1-I2

-I1

-1

-1
-V1

SL1

-I2

-I1=

V1
,
sL1

-I2=

V1 + V3
,
sL2

SC2
VB
VA

VC

-I2

-1

-1

SL2

+
VD

I3=

I3

-1
SL3

-1

-1
S(C2+C3)

V3

V3

I3-I2

1/RL

V3
,
sL3

V3=

SC2

-I2

Vin V1
1
+ sC 2V3 I 1 I 2 ,

s (C1 + C 2 ) RS

Vout

V3
1
sC 2V1 + I 3 I 2 +

s (C 2 + C 3 )
RL

14-37
CHUNG-YU WU

** The circuit has a stability problem at dc.

Due to inductor loops!

HAB

VB
VA

HCD

VC
VD

sL1
S L1 (C1 + C 2 ) + SL1 / Rs + 1

sL3
S L3 (C 2 + C 3 ) + SL3 / RL + 1

Circuits below A and B disconnected

Circuits below C and D disconnected

When S0, HAB0, HCD0

> There will be no dc feedback paths around the
center integrator which provides -I2.
> OP AMP will be in the open-circuit status with A.
> Saturation occurs
How to solve this problem?
Don't model the inductor loop currents separately.
i.e. I1, I2, I3.
Only two inductive currents I and I entering nodes
1 and 3 are modeled.
3

> Vin =0 and S0, I =0 and I =0

1

>No any instability at dc.

i.e.
Treat only two inductors as independent inductors.
I =I1+I2
I =I2-I3
1

New flow diagram:

14-38
CHUNG-YU WU

-V1=

Vin V1

1
+ sC 2V3 I (11) ,

s (C1 + C 2 ) Rs

-I(1)
1 ( I1 + I 2 ) =

V3=

1
sL12

L1V3
V1
,
L1 + L2

V3
1
,
sC 2V1 I (33) +
s (C 2 + C 3 )
RL

-I(3)3 I3-I2=

1
sL12

L1V1
,
V3 +
L1 + L2

Where L12 L1 L2 = L1 L2 /( L1 + L2 )

14-39
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14-40
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SCF:

14-41
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General Procedures for the approximate design of SC ladder filter

: 1. A doubly terminated LC two-port is designed from
the SCF specifications can be prewarped using the relation:
T
2
Wa = sin( )
T
2
which represents the frequency transformation due to
the LDI transformation implicit in the design
produce.
Inverting SC integrator + Noninverting SC integrator
1
(C1 / C 2 ) inv (C1 / C 2 ) noninv z
H(z)=
1 z 1
1 z 1
K
Kz 1
=
= 1
1
1 2

(1 z )
(z 2 z 2 )2
Ton z=ejT
> H(ejT)=

+K
4 sin 2 (T / 2)

LDI mapping (Lossless discrete integrator):

1
Sa= ( z z 1 )
2T
1

1 12
T
If
is used > Sa= ( z z 2 )
2
T
1
T
> a=
Sin( )
T /2
2
2.The state equations of the LCR circuit are found. The
signs of the voltage and current variables must be chosen
such that inverting and noninverting integrators alternate in
the implementation. If inductor loops exit, the inductive node
currents can be used.

14-42
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4. The block diagram or signal flow graph (SFG) is

constructed from the state equations. It is then
transformed (directly or via the active-RC circuit)
into the SCF.
5. If necessary, additional circuit transformations can
be performed to improve the response of SCF.

14-10 Exact Design of SC Ladder Filters

* Ladder synthesis based on the bilinear Sa-to-z transformation
Sa=

2
T

z 1
z +1

(1)jaaxis>unit circle
(2)preserves the flatness of PB and SB

14-10.1 Third-order SCF (Low-pass with finite transmission zero)

C2'=C2+CL2
-CL2=
-V1

T 2
4L2

V1 + Vin

s
C
V
I
a 2
3
2 ,
'
Rs
S a (C1 + C 2 )

1
-I2= s a C L 2
[V1 V3 ] ,
s
L

a 2
V3=

V
1

s a C 2 V1 I 2 + 3 .

s a (C 2 + C 3)
RL

LCR Prototype Circuit:

14-43
CHUNG-YU WU

Flow diagram

The center block has the transfer function:

2

1 S a L2 C L 2
1 ( S a T / 2) 2
1
=
=
H(Sa)=SaCL2S a L2
S a L2
S a L2

Transformation of the blocks into SC circuits:

(1) Finding Q-V relations of all blocks and branches in
the Sa domain.
(2) Transforming the Q-V relations into the z-domain.
(3) Realizing the transformed z-domain equations into
SC circuits.

Five different blocks:

(a) The input branch 1 Rs

14-44
CHUNG-YU WU

Qin (Sa)=

Qin (z)=

1
1
Vin
Rs
Sa

T z + 1 Vin ( z )
2 z 1 Rs

> (1-z-1)Qin =

T
(1+z-1)Vin(z)
2 Rs

qin(tn)-qin(tn-1)=
SC realizations:

Cs
[Vin(tn)+Vin(tn-1)]
2

Optional. To guarantee the charge flow only when 1=1

1

CS/2
2

Vin
CS

CP

Virtual
ground

Cs Cs
:
[V in (t n ) V in (t n 1 )]
2 2
Cs : Cs Vin (tn-1)

* Not stray insensitive.

Cp + Cs not Cs
(b) The feedback branch 1 R , 1 R
s
L
Vin

-CS/2
2

CS

Virtual
ground

Cs
C
: s [Vin (t n ) Vin (t n 1 )]
2
2

Cs: CsVin(tn)

Cs
[Vin(tn)+Vin(tn-1)]
2

* Stray insensitive.
(c)The branches SaC
Q
1
= CS a
=C
V
Sa
(d) The blocks -

Only a C is required.

1
SaC
Q
= C
V

> OP with a feedback capacitor C.

14-45
CHUNG-YU WU

(e) The center block

1 ( S a T 2) 2
-I2=(V1-V3)
S a L2
1 ( S a T 2) 2
I2
=
(V1-V3)
Q(Sa)=
2
Sa
S a L2
4C L 2 Z
Q( z )
1 [( z 1) /( z + 1)]2
>
=
=
2
2
V1 ( z ) V3 ( z )
(4 L2 / T )[( z 1) /( z + 1)]
( z 1) 2
-1

Q(z)=(1-z )Q(z)=

4C L 2
(V3 V1 )
z 1

4C L 2 / C 2
Q( z ) 4C L 2 z 1
1
)(C )
=
= (Cz )(
V3 V1 1 z 1
1 z 1
Realizations:
-V1
1

Virtual
ground
C2/4CL2

C
2

C
1

2
Q

Virtual
ground
V3

The final realization is shown in the next page.

* This circuit is not fully stray insensitive.
C
* The negative capacitor s has been merged into the feedback capacitors
2
CA and CB, respectively.
C
C
CB=C2'+C3 s
CA=C1+C2' s
2
2
* Why C2', -CL2 ?
To create a block which is realizable by SC circuit.

14-46
CHUNG-YU WU

SCF:
2
CS / 2
Vin

CS

CS

CA

2
2

C
CB

C
2

+
C'2

C
CC
1

2
2

C'2

CL
Vout

The complete bilinear ladder circuit equivalent to the LCR circuit

14-47
CHUNG-YU WU

14-10.2 Bandpass LCR filters

C1

C3
2

LC prototype
Circuit:
V

I2

L1

C2

V2

V3

IL2
L2

IL3

L3

-V2 can be produced as:

I2

C2
I2

-V2

I2=(SC1+

V
1
1
) (V1-V2)+(SC3+
) (V3-V2)- 2
SL1
SL3
SL2

Note that

1 ( S a T 2) 2
is realizable !
Sa L

>I2(S)=S[(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3]
1
S

+(

T 2s
) [1V1+(1+2+3)(-V2)+ 3V3]
4

1
T2
, i=
Where CLi
Li
4 Li
First Term:
Q2'(S)=(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3
Can be realized by unswitched capacitors.
Second Term:
T z +1 2 T 2
) ] [1V1+(1+2+3)(-V2)+ 3V3]
Q2"(Z)=[(
2 z 1
4
T 2 z 1
=
[1V1+(1+2+3)(-V2)+ 3V3]
(1 z 1 ) 2

14-48
CHUNG-YU WU

The same as before but now three functions are

superposed together. ( Q2 " / V1 , Q2 " /(V2 ), Q2 " / V3 )
C 4C7 T 2
CC
1
1
1
=
= 4C L1 ; 5 7 = T 2 ( + + ) = 4(C L1 + C L 2 + C L3 )
Conditions:
C8
L1 L2 L3
C8
L1
C6C7 T 2
=
= 4C L 3
C8
L3
Stage providing Q2(z):
V1

-V2

C4

C5

V3

LC prototype circuit:
C1

C6

C3
V2

V3

V1
L1

C2

L2

L3

C8
C7

Q2"(z)

Vitrual
ground

SC realization:
Design equations:
CL1=T2/(4Li)
c1=C1+CL1
c2=C1+C2+C3+CL1+CL2+CL3
c3=C3+CL3
c4= 4

c3

V1

c2

c8
C L1
c7

c
c5= 4 8 (C L1 + C L 2 + C L 3 )
c7
c6= 4

c1

Vt=-V2
c5

c4

c8
CL3
c7

c7, c8 arbitrary

c7

c8
Vb

V3
c6

14-49
CHUNG-YU WU

LC prototype circuit with RS:

C2

RS

C1

Vin

L1

V2

L2

SC realization:
c1
Vin

c2

c8

c3

c4
-V1

c5

V2

c9

Design equations:
C Li
c7

c6

T2
4 Li

, Cs

T
Rs

Cs
,
c2=c3=C9
2
c4=C1+C2+CL1+CL2-CS/2
c1=

c5=4

c6
(C L1 + C L 2 )
c7

c8=C2+CL2
c9=4

c6
CL 2
c7

c6, c7 arbitrary

14-50
CHUNG-YU WU

LC prototype
circuit with RL:

C1
VN

VL

C2

L1

L2

RL

SC realization:
c1

c3

c4

-VL
VN

Design equations:
CL1

T2
T
, CL
RL
4 Li

c5

c2

c1=C1+CL1
c2=4

c6
C L1
c7

c3=CL
c4=C1+C2+CL1+CL2-CL/2
c
c5= 4 6 (CL1+CL2)
c7
c6, c7 are arbitrary

c7

c6

14-51
CHUNG-YU WU

Z-domain verifications:
Upper OP AMP:
C1(1-z-1)V1+C3(1-z-1)V3+C2(1-z-1)Vt+C7Vb=0
Lower OP AMP:
-C4z-1V1C6z-1V3-C5z-1Vt+C8(1-z-1)Vb=0
Vt=-

>

N 1V1 + N 3V3
D

z 1 (1 z 1 )[(C 2 C 4 C1C5 )V1 + (C 2 C6 C3C5 )V3 ]

Vb=
C8 D
where
N1(z)=C1C8[(1-z-1)2+

C 4 C7 1
z ]
C1C8

N3(z)=C3C8[(1-z-1)2+

C6 C7 1
z ]
C 3 C8

D(z)=C2C8[(1-z-1)2+

C5C7 1
z ]
C 2 C8

* All poles and zeros of the transfer functions Vt/V1, Vt/V3, Vb/V1, and Vb/V3
are located on the unit circle.
After the bilinear s-to-z transformation,
Vt=

[(C1C8 C 4 C 7 / 4) S 2 + C 4 C 7 / T 2 ]V1 + V3 [(C 3C8 C 6 C 7 / 4) S 2 + C 6 C 7 / T 2 ]

(C 2 C8 C 5 C 7 / 4) S 2 + C 5 C 7 / T 2

1 S
S ( )[(C 2 C 4 C1C5 )V1 + (C 2 C6 C3C5 )V3 ]
Vb= T 2
(C 2 C8 C5C7 / 4) S 2 + C5C7 / T 2
* The phase shift between Vt and V1, as well as between
Vt and V3 are either 0 or 180 for s=j
>The same as for the LC prototype regardless of the
element values Ci.
>Can simulate a lossless LC with the same low
sensitivity.

14-52
CHUNG-YU WU

* It can also simulate the behavior of any LC ladder section which has a T
configuration.
V1

V2
C1

High-pass

V3
C3

L2
C2

L1

Low-pass

L3
L2
C2

Vt=-V2
> V2=

(aS 2 + b)V1 + (cS 2 + d )V3

eS 2 + f

* High-Pass Case :

c 2 / T
=
2
2
If the loss is zero (i.e. passband),

At Z=ejT =-1

, i.e. =

=>(1-z-1)Qin(z)=

T
(1+z-1)Vin(z)
2 Rs

=0
Qin(z)=0, but loss is zero
>The other part of the circuit
should have an infinite gain.
>unstable.
Rs input (i.e. input termination) is a problem!
* Inductor loop is O.K.

14-53
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14-10.3 Comparisons
LDI Realizations of Ladder Filters using SC Integrators
(1) Prewarping is required
(2) Inductor loop exists
>Modified design
>Component sensitivity
Bilinear Realizations of Ladder Filters using SC Integrations
(1) Prewarping is not required.
(2) Low-pass, band-pass ladder filters are O.K.
But they are not fully stray insensitive.
(3) Can't realize high-pass or band-reject filters.
> Instability exists.
(4) Some modifications are proposed.
But they are not fully stray insensitive.

14-11 The Scaling of High-Order SCF's.

Why scaling?

V1

F1

(1) Improve the actual performance.

(2) Reduce the silicon area

Q1

F7
V2

F2

Q2

Q4

F4

Vj

F5
Q5

V3

F3

OAj

Vi

F8

Q3

OAi

F6
A

Q6

SC filter section.

OAk

Vk

14-54
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Let all branches connected to the output terminal of OAi be modified such that
their Q / V transfer functions F4, F5, and F6 are multiplied by a positive real constant
factor k. This can be achieved simply by multiplying all capacitors in these branches
by ki.
Since the input branches and their voltages were left unchanged, the change
flowing in the feedback branch is
Q4(z)=- Q1(z)- Q2(z)- Q3(z) remains at its original value.
> V2.'(z)= Q4(z)/[kiF4(z)]=Vi(z)/ki
The old output voltage of OAi

The new output voltage of OAi

ViVi/ki due to scaling.

Q5'=F5'(z)Vi'(z)=kiF5(z)

Vi ( z)
=F5(z)Vi(z)= Q5 ( z )
ki

Voltage scaling does not change charge flowing from the scaled branch
to the rest of the circuit.
>Only Vi/ki, all other voltages or changes are not affected.
Optimization of the dynamic range using scaling

V1

V2

V3

F1

F4

F2

Vj

F5

OAn
F3

OAi

Vin

F6
A

Vn

Vmax/Ap Vin, max

Ap: passband gain.

Vn

Vout

14-55
CHUNG-YU WU

OA2 will saturate before OA5 because V2 V5 for ~2.

Now, we choose Vin, max=Vmax/A2
A2= V p 2 / Vin , Ap= V p 5 / Vin
A2=Ap VP 2 / VP 5
Vin, max=

Vmax Vmax VP 5 Vmax

=
<
A2
AP VP 2 AP

since VP5/VP2<1

>Maximum Vin > Dynamic range

Reducing V2 by scaling.
V2'()=V2()/k2

k2=VP2/VP5

>V2' has a peak value of VP2' which is equal to VP5.

>Vin, max=Vmax/Ap
Similarly, k3=VP3/VP5. k1=VP1/VP5<1, k4=VP4/VP5<1.
It is not good to choose k2(k3)> VP2/VP5(VP3/VP5)because the noise will be increased.
> dynamic range .
CONCLUSION:
For maximum dynamic range, all op-amp outputs should be scaled such that
each (at its own maximum frequency) saturates for the same input voltage level.

14-56
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Let the transfer functions Fj(z) Q j / V j of all branches connected to the input
terminal of OAi be multiplied by a positive real constant Mi => CimCi

Qn

, n=1, 2, 3, 4 Qn ' =mi Qn

F1, F2, F3, F4

Vi'=

Q4 ' mi Q4 Q4
=
=
= Vi
F4 '
mi F4
F4

Vi unchanged!

The output charges Q5 and Q6 also remain the same

=>The above scaling by mi leaves all op-amp output voltages
in the SCF unchanged. Only the charges in the scaled
branches get multiplied by mi.
=>Effective in reducing the cap. spread and the total
capacitance of a SCF.
Ci, min among all capacitors contained in these four branches
is located. =>All capacitors contained in these four branches
are multiplied by mi=Cmin/Ci, min
=> The smallest capacitance becomes Cmin and all op-amp
voltages remain unaffected.
* Scaling for optimum dynamic range should be performed first,
and scaling for minimum capacitance afterwards.
1. Scaling for Maximum Dynamic Range
(a) Set Vin() to the largest value for which the output
op-amp does not saturate. Record Vin() and Vi, max
(b) Calculate Vpi for all internal op-amp output
Vpi usually occur near the passband edges.
(c) Multiply all capacitors connected or switched to the
output terminal of op-amp i by ki=Vpi/Vi,max where
Vi,max is the saturation voltage at the output.
(d)Repeat for all internal op-amps.
2.Scaling for Minimum Capacitance
(a) Divide all capacitors in SCF into nonoverlapped sets.
Capacitors in the ith set Si are connected or switched to the input terminal of

14-57
CHUNG-YU WU

op-amp i.
(b) Multiply all capacitors in Si by mi=Cmin/Ci, min.
(c) Repeat for all sets Si.
* Scaling for optimum dynamic range may also reduce the sensitivity to finite
op-amp gain effects.
Y

V1
V2
V3

Y1
Y2
Y3

vout

Y0

(a)

(Y+Y0+Y1+Y2+Y3+...)/A
Y

V2
V3

Y2
Y3

vout

V1

Y1

(b)

The influence of finite op-amp gain: (a) actual circuits; (b) equivalent circuits.
3. The block diagram or signal flow graph (SFG) is constructed from the state
equations. It is then transformed (directly or via the active-RC circuit) into the
SCF.
4. If necessary, additional circuit transformations can be performed to improve the
response of SCF.

14-58
CHUNG-YU WU

14-10 Design Examples on Cascaded SCF and LDI Ladder SCF

14-10.1 Cascaded SCF
Filter Specification
Passband:

Stopband:

0 to fp=1kHz
passband ripple p 0.05dB
(Maximum allowable passband gain variation)
fs 1.5KHz to fc/2
Minimum stopband loss s 38dB
(Maximum allowable gain value)

Sampling frequency:

1
T

fc= =50KHz

Design Procedures:
1.S-domain transfer function H(s)
Frequency prewarping
ap=

T
2
tan p =6291.4667 rad/s
T
2

as= 2 tan T
s

Selectivity parameter
k

ap
0.6656
as

Elliptic filter is chosen to minimize the filter order.

Results:

S 2 a + 1
0.068
)(
)
(Sa)=(
S a + 0.78140011 S a 2 + 0.96934556S a + a1 2 + b1 2
(-2 a1 )
(- a 0 )
2

S a + 2
)
2
2
2a 2 S a + a 2 + b2
2

Sa

where 1=-0.48467278, b 1=0.82815049, 2=-0.128006731,

b 2=1.100351473, 1=1.5514948, 2=2.32131474

14-59
CHUNG-YU WU

=> filter order=5

ap=1 rad/s, p=0.044dB, as=1.49448 rad/s,
s=39.57dB, k =0.669
=> The specifications are satisfied with a(0)=1
2. frequency denormalization and z-domain transfer function H(z)
Denormalization: SaS/p
(Sa) H(S)
( S 2 + 1 )( S 2 + 2 )
H(S)=K
2
2
2
2
( S a0 )( S 2 2a1 s + a1 + b1 )( S 2 2a 2 s + a2 + b2 )
2

Where K=428.247646, 1=9.76117788103,

2=1.46044744104, ao=-4.91615278103
a1=-3.04930266103, b1=5.21028124103
a2=-805.350086, b2=6.92282466103
2 z 1
z 1
Bilinear transformation:
S
= 10 5
T z +1
z +1
H(s) H(z)
z + 1 z 2 + C1 z + 1 z 2 + C 2 z + 1
)(
)(
)
H(z)(C
z + d o z 2 + e1 z + f1 z 2 + e2 z + f 2
Where C=3.871927110-3, C1= -1.962247471, C2= -1.916465445,
do=-0.906284158, e1= -1.871739343, f1=0.88543246,
e2=-1.949416807, f2=0.968447477.
Check: H (e jT ) satisfies specifications.

1
H(ejT)

fc/2
fp

1
vs. f
H(ejT)

0ffc/2

14-60
CHUNG-YU WU

1
H(ejT)

vs. f

0 f f p

fp

3. SC realization
(1) H0(z)=

z +1
z 0.9063
CD

Vin
+

CS
2

H0(z)=-

-1/CE

Vout

1-Z-1

(1+Z-1)

1
CS/2

Vin

CS

Cs / 2
z +1

C D + C E z C E /(C D + C E )

Cs=2 arbitrarily chosen

=>CE=0.9063 , CD=0.0937

CD
CE

A1

z 2 + C1 z + 1
(2) H1(z)=
(1 / f1 ) z 2 + (e1 / f1 ) z + 1

Vout

(a + b1 )
Q1= 1
2 a1

0.99 Low-Q

The SCF is shown on P.14-21.

The component values are: C1"=a0=1,
C1'=a2-a0=0,
C2=C3= b1 + b2 + 1 = (e1 + 1) / f1 + 1 0.12436,

14-61
CHUNG-YU WU

C1=(a0+a1+a2)/C3 0.30358,
C4=b2-1=1/f1-1 0.12939,
CA=CB=1.
(3) H2(z)=

z 2 + C2 z + 1

( 1 ) z 2 + ( e2 f 2 ) z + 1
f2

(a + b2 )
Q2= 2
2 a2

4.33 =>High-Q

The SCF is shown on P.14-23.

The component values are:
C1 " = a 2 / b2 = f 2 0.96845

C1 ' = (a1 a 0 ) / b2 c3 = 0,

C 2 = C 3 = (1 + b1 + b2 ) / b2 =

f 2 + e2 + 1 0.13795,

C1=(a0+a1+a2)/b2C3=(2+c2)f2/C3 0.58645,
C4=(1-1/b2)/C3=(1-f2)/C3 0.22873.
(4)Overall SCF
* Ho (low-pass linear section) is placed first
=>High-frequency out-of-band signals and input noise can be attenuated.
The antialiasing filter preceding the SCF has a lower requirement.
* H2 (high-Q section) is placed to the center=>good signal-to-noise ratio
CD
CS/2
Vin

1 CS
2

CE
2

C4
2 C1

A1

C2

CA
A2

CB

C3
2

A3

C1"

SECTION 1

SECTION 2 (HIGH Q)
C2

2
A

1
C4

CA
C1

C3

A4

CB

C 1"

SECTION 3 (LOW Q)

A5

2
2

Vout

14-62
CHUNG-YU WU

4. Scaling
1) Vp1=occurs at dc where H0(1)=-CS/CD=-21.345
(1)We want an overall passband gain of 1. =>Ho(1)-1
=> CD=CS=2, CE 19.345, C1"20.672, C2 12.518
(Multiplying all capacitors connected or switched to the output node
of op-amp A1 by 21.345)
(2)All capacitors at the input node of A1 should be scaled so that the
smallest ( Cs 2 ) equals 1. (O.K.)
2) Vp2 (peak output voltage of op-amp A2) occurs around fp2=1.10kHz
(1) Vp2 177.05 for Vin=1
Reducing Vp1/Vin to 1
=>CA and C3 are multiplied by 177.05=> CA 177.05, C3 24.424.
(2) Vp3 180.80 at 1.07kHz
=>CB,C2, and C4 are multiplied by 180.80=>CB 180.80, C2 24.941,
C4 41.354.
(3) Minimize total capacitance=>C1, C2, C4, and CA at the input
node of op-amp A2 are scaled to make C1=1
=>C1=1, C2 1.9926, C4 3.3036, CA 14.144
(4) Similarly, C1"=1, C3 1.1815, CB 8.7466. (The input of A3)
3) Vp4 503.57 and Vp5 230.14
Thought the same procedures, we have
C A 17.666, C B 7.7286
C1 1.9926, C 2 = 1
C3 2.1116, C 4 = 2
C1 6.3085
"

5 Final Design
Cmin is chosen as 0.5pF => C=1
op amp: gain 70dB bandwidth 3 MHz
passband sensitivity to capacitance variation 0.2dB/1%

14-12.2 Bilinear Ladder SCF Design

1. The same filter specification.
Elliptic ladder filter is chosen(fifth-order).
The result is

14-63
CHUNG-YU WU
L2

L4

RS

Vin

C1

C2

C4

C3

C5

RL

Normalized component values:

Rs=RL=1
C1=0.85535 C2=0.15367 L2=1.20763
C3=1.48438 C4=0.46265 L4=0.89794 C5=0.63702
ap=1 rad/s
2. Frequency prewarping and denormalization
ap

T
f
2
tan p = 2 f c tan p 6291.4667rad / s
T
fc
2

Multiplying each resistor by z0, each inductor by L0=z0/ap, and

each capacitor by C0= 1 ap.
z0
50
Usually choose z0=real source and termination resistance 100
600
Here, C0=1 is chosen => z0=

ap

and L0=

1
2
ap

We have the denormalized element values as:

C1=0.85535, C2=0.15367, L2=1.20763Lo=3.0509010-8,
C3=1.48438, C4=0.46265, L4=0.89794Lo=2.2685110-8,
C5=0.63702, Rs=RL=z0=1.5894510-4
3. SC realization
Using the exact design technique of SC ladder filter (Section 14-10),
the state equations are
-V1=
-I2=-(
V3=

1 1
( (Vin V1 ) I 2 + sC ' 2 V3 ),
sC '1 RS

1
sC L 2 ) (V1V3),
sL2

1
( I 2 sC ' 2 V1 sC 4 'V5 + I 4 ),
sC ' 3

14-64
CHUNG-YU WU

I4=(

1
sC L 4 )(V3 V5 ),
sL4

-V5=

The signal flow diagram is:

V
1
( I 4 + sC ' 4 V3 5 ),
sC ' 5
RL

1/RS
Vin

-1/sC'1

1/RS

where
CL2=

T
= 0.003278,
4 L2

I4

1-(sT/2)2
sL4

sC'4

T2
CL4=
= 0.0044082,
4 L4

sC'4
-1/sC'5

C'4=C4+CL4=0.46706,
C'3=C3+C'2+C'4=2.10839,
C'5=C5+C'4=1.10408.
Vin

1
2

arbitrarily chosen

Cs=

C
CA=C1+C2+CL2- s = 0.94938,
2
CB=

2
1

CA
A1

Co2

C21

C22

CB

A2

Co3

C
C
= L 2 = 0.0008195,
4C L 2
4

Co4
CC

A3

Co5
Co6

C
C '2
= L 4 = 0.001102,
4C L 4
4

C
CE=C'5- L = 1.041165,
2
T
CL= = 0.12583.
RL

2
Co1

Cc=C'3=2.10839,
CD=

C2

C'=CL4=0.004408

T
= 0.1258293,
Rs

-V5

1/RL

C1

C=CL2=0.003278

V3

-1/sC'3

C'2=C2+CL2=0.15695,
C'1=C1+C'2=1.01230,

SCF:

sC'2

1-(sT/2)2
sL2

-I'2

sC'2

-V1

1
C41

C42

2
Co7

CD

A4

Co8

CE
2
A5

CL
Vout

14-65
CHUNG-YU WU

4.Scaling
Vin=1V, we have:
A1: CA,C2,C21, and C02
multiplied by Vp1
A2: C3,C01, and C03
multiplied by Vp2

Vp1 0.92V,
Vp2 34V,
Vp3 0.764V,
Vp4 28.86V,
Vp5 0.5V,

C1=1.00000
C2=1.83854
C3=2.00000
CA=13.87171
C01=1.77112
C02=1.20275
C03=1.00000
C04=1.00000
CB=11.11901
Cc=14.46156

for dynamic range scaling

minimum-capacitance scaling: C A

Cs

=13.87171

C05=1.14172
C06=1.52861
C07=2.02212
C08=1.00000
CE=8.27441
CD=14.43078
CL=1.00000
C41=2.09575
C42=5.67396
C21=1.29480
C22=1.90667

5.Final design
Cmin , OP amp: 70dB 3 MHz
=>Passband ripple: 0.06dB minimum stopband loss 39.5dB
Maximum sensitivity: 0.05dB %

14-12.3 LDI Ladder SCF Design

1. LCR prototype circuit
Fifth-order elliptic LC ladder filter with the same lowpass specifications.
2. Frequency prewarping and denormalization
ap p (for simplicity)
z0=1 => C0= 1

(2 10 )
3

F, L0=

1
H
(2 10 3 )

The denormalized element values:

State equations:
V + Vin
1
Rs=1,
( 1
+ sC 2V3 I 2 ),
-V1=
s
C
C
Rs
(
+
)
1
2
C1=136.13318F, C4=73.633034F,
C2=24.45734F, L4=142.91159H,
V V
-I2= 3 1 ,
L2=192.20028H, C5=101.38488H,
sL2
C3=236.24641F, RL=1 .
1
( I 2 sC 2V1 sC 4V5 + I 4 ),
V3=
s (C 2 + C 3 + C 4 )

I4=

V3 V5
,
sL4

-V5=

V
1
( I 4 + sC 4V3 5 ).
s (C 4 + C 5 )
RL

14-66
CHUNG-YU WU

3.SCF design
The flow diagram is shown on P.14-? whereas the active-RC
circuit is given on P.14-?.
The SCF is shown on P.14-? where T=20s is chosen and the component values
are
C2+C3+C4=334.34F,
C1+C2=160.59F,
CS=

T
=20F,
Rs

T
1

C= =20F,

C4+C5=175.018F,
CL=

T
=20f
RL

4.Scaling
Dynamic range scaling with Vpi listed:
followed by minimum-capacitance scaling

Element values:
C1=8.03214, C3=12.97271,
C3A=1.08390,
C1A=1,
C1B=1.07930, C3B=1,
C1C=1.29263, C3C=1.02540,
C1D=1.13212, C3D=1.66885,
C2=13.42236, C4=15.76379,
C2A=1.08053, C4A=1.71203,
C4B=1,
C2B=1,
C5=8.75121,
C5A=2.20614,
C5B=1,
C5C=6.29664.

for A1:Vp1=0.927 V at 1.182kHz.

for A2:Vp2=1.198 V at 1.121 kHz.
for A3:Vp3=0.857V at 1.061 kHz.
for A4:Vp4=1.105 V at 1.061 kHz.
for A5:Vp5=0.501 V at 967 kHz.
SCF:

5.Final design
Cmin Passband ripple: 0.095dB>0.044dB
Minimum stopband loss: 40.5dB
OP amp: 70dB, 3MHz
Maximum passband sensitivity: 0.08dB %

14-67
CHUNG-YU WU

14-13 Nonideal Effects in Switched-Capacitor Filters

1. Switch Turn-On Resistance
The turn-On resistance of a MOSFET can be written as
1

Ron=

uco w
(VG S VT )
2 L

Vin
signal voltage -Vss

* Nonlinear behavior

The Ron effect on the simple SC integrator:

C2
1

2
1

Vin

C1

Vout

2
t=nT

t=(n+1)T

C2

1
R1

R2

+
-

Vout
Vin

V1

C1

t=nT nT+T/2 (n+1)T

At t=nT , V1(t)=V1(nT)=Vin(nT)(1-e T 2 R C )
1 1

Assume 1 and 2 are activated for T 2 .

T
Q (nT+ ) = C1V1(nT )(1-e T / 2 R2C1 )=[Vout(nT+T)-Vout(nT)]C2
2

Let R1=R2=R
(1 e T 2 RC ) 2 C1 C 2
=> H(z)=
z 1
C C
Ideal: H(z)=- 1 2
z 1
1

14-68
CHUNG-YU WU

=1-(1-e T / 2 RC ) 2 2e T / 2 RC

Error:

Usually <0.1%(cap. ratio error) is acceptable.

2e T / 2 RC 10 4
1

=>

RC1
1
0.05
=RC1fc
T
2 ln 20000

or RC1 T (= 1 )
20

20 fc

fc=500KHz, C1=5pF R 20 K ; fc=100MHz, C1=2pF, R 250 ?

2.Clock Feedthrough Noise

* All switches directly connected to the integrating node
generate clock feedthrough noises.
1

n
T

* All clock feedthrough noises are proportional to the sampling

frequency. They may have a dc component.
* As soon as the clock feedthrough error voltage does not

14-69
CHUNG-YU WU

saturate the OP AMP, it can be eliminated at the

output by reconstruction filters(LPF).
* The dc component cause offset voltage problems.
3.Junction Leakage
* Worst-case (100C or 125C) leakage at the integrating node:
5m5m junction => 400 pA leakage
~10 nA/mil2
* fs, max is about 25KHz in this case to avoid significant errors.
* The leakage cause dc offset voltages.
4. DC offset Voltage of the OP AMP
-

+
ideal op amp

+
-

pratical op amp

Voff

Voff = 5~20mv

C2
2

2
Vout

C1

+
+
-

Voff

* Vout=(1+

C1
) Voff
C2

* Integrator-based design may have a dc offset

problem if no other negative feedback paths
exist.
* Too-low-frequency operation is not good.
C2

5. Finite Gain of the OP AMP.

1
Vout(nT)=Vc2(nT)- Vout(nT)
AO

C2[Vc2(nT)-Vc2(nT-T)]
+C1[Vin(nT)+

1
Vout(nT)]=0
AO

2
C1

Vout ( z ) (C1 C 2 )[1 + (1 + C1 C 2 ) / AO ]1 z

=
=>H(z)=
Vin ( z ) z (1 + 1 ) /[1 + (1 + C1 C 2 ) / AO ]
AO

Vout

+
A0

14-70
CHUNG-YU WU

H(ejT)=Hi(ejT)

1
1+ ( 1

AO

(C1 / C 2 )
z 1
1
F()=
1 m( ) + j ( )

)(1 + C1 / 2C 2 ) j (C1 / C 2 ) / 2 AO tan(T 2)

Hi(z)=

F()
m()=

C1 / C 2
C
1
(1 + 1 ) ()=
AO
2C 2
2 Ao tan(T / 2)

C1 / C 2
AoT
relative magnitude error

F ( ) =

1
(1 m) +
2

1
1 m

1+m

<<1

F()=-tan 1 m tan-1
-1

relative phase error

<<1

m<<1

T<<1 , Ao >1000 , C1/C2 normal value.

AoT>>1

Ao>1000=>0.1%

f
1
= s
AoT Ao
=> m and are very small.
But for <2/AoT , is large.
>>

Ao>100=>1%
<0.1%

6. Finite Bandwidth of the OP AMP.

A(s)=

1
1 / Ao + S / o

single-pole response

Similarly
C2
C1 + C 2

m()=-e-k1[1-KcosT]

k=

()=e-k1KsinT

k1 K woT/2

If oT/2=o/c >>1 => m0, 0.

** o 5c is adequate.
* The unity-gain bandwidth o of the OP AMP should be
(at least) five times as large as the clock frequency c.

14-71
CHUNG-YU WU

o vs c:
(1) Given o, c should be chosen low enough so that the OP AMPs have
enough time to settle.
But c should not be too low, or the noise aliasing effect becomes serious
the antialiasing and smoothing filters must be too selective and too
complex.
(2) Given c, o should be just high enough to assure that the stage can settle
within each clock phase. Any higher value worsens unnecessarily the
noise aliasing effect, and raises the dc power and chip area requirements
of the op-amps.
(3) Ao=1000 (60dB), fo=10MHz, fp1=10KHz
choose fc=2MHz, and f<40 KHz
Typically f/fc 48 i.e. oT

1
4

7. Finite Slew Rate of the OP AMP

* The output voltage of the OP AMP must be settled down with the clock
active duration.
tslew + t settle<T2
* May cause nonlinear distortion.
8. Nonzero OP AMP Output Resistance
2Ro (

C1C 2
1
+ C L ) T1 < T 2=1
C1 + C 2
7

C2: feedback cap ; C1:input cap; CL: load cap.

9. Overall considerations:
For an integrator settling error of 0.1% or less,
we must have
Ao 5000
o/c 4
T/RonC1 40
10. Noise Generated in SC Circuits
(1) Clock feedthrough noise
(2) Noise coupled directly or capacitive from the power, clock,
ground lines, and from the substrate.

14-72
CHUNG-YU WU

(3) Thermal and flicker ( 1 f ) noise generated in the switches and op-amps.
Thermal and flicker ( 1 f ) noise:
* Internal sampling and holding=>If 1 f noise has no
aliasing=>It can be eliminated.
* Thermal noise will be sampled and held with the OP AMP as
a frequency limiting element.=> o>>c is not suitable.
* The circuit noise if the circuit cap.

15-1
CHUNG-YU WU

CH 15. Continuous-Time Filters in CMOS

15-1 Categories of continuous-time filter ICs
Amplifier Types

Continuous-Time Filter Types

Voltage OP AMP AV
Current OP AMP AI
Finite-gain voltage amp
Finite-gain current amp.
Infinite-gain Operational Transconductance
Amp. (OTA) Gm
Finite-gain OTA or gm amplifier
Infinite-gain Operational Transimpedance
Amp. Rm
Finite-gain Transimpedance Amp. or Rm
amplifier
Mixed Gm and Rm Amplifiers
Mixed AV, AI, Gm, and Rm Amplifiers
RF amplifier

(Voltage-mode) Active RC filters

:
:
:
:
:

(Current-mode) Active RC filters

(Voltage-mode) Active RC filters
(Current-mode) Active RC filters

(Voltage-mode) Gm-C filters

(Current-mode) Rm-C filters

?
?

Integrated LC filters

well developed
less developed but with great potential
much less developed
not explored
to be developed with potential

Common characteristics of continuous-time filters:

1. Not parasitic free
=>Greater tolerance in performance.
2. No switches or clocks
=>Lower noise (clock-induced) or simpler circuit.
3. Need tuning to accommodate the process variations on
filter characteristics if high accuracy is required.
=>Extra overhead and higher cost.
=>Might not be needed if process-independent design
is used and reasonable tolerance is allowed.

15-2
CHUNG-YU WU

4. Could achieve higher-frequency operation in the VHF

or UHF range if finite-gain amplifiers are used.
5. Could achieve GHz operation if deep submicron CMOS
is used.

15-2 Gm-C or OTA-C (Operational-Transconductance-Amplifier-C)

Filters
15-2.1 Transconductor or OTA characteristics
Gm amp or OTA symbol

Ideal characteristics:
gm=hIABC or h'VABC
Io=gm(V+-V-)
Ri , Ro=0
h(h') is a constant.

V+

Io

V-

IABC or VABC

V+

Nonideal characteristics:
gm is not linearly proportional
to IABC or VABC.
Ri and Ro are finite.

gm

Ri
V-

Io
gm(V+ - V-)
Ro=0

ideal equivalent circuit

Ri
V-

Ro
gm(V+ - V-)

15-2.2 Basic OTA building blocks

Ref.: IEEE Circuits and Device Magazine, pp.20-32, March 1985.
1. Voltage amplifiers Gm or op amp + resistors.

(a) Basic inverting

Io

V+

(b) Basic noninverting

15-3
CHUNG-YU WU

(c) Feedback amplifier

(e) Buffered amplifier

(d) Noninverting feedback amplifier

(f) Buffered VCVC feedback

(g) All OTA amplifiers

15-4
CHUNG-YU WU

2.Controlled impedance elements

1

(a) Single-ended voltage

variable resistor (VVR)

(c) Scaled VVR

(b) Floating VVR

(d) Voltage variable impedance inverter

(e) Voltage variable floating impedance

(f) Impedance multiplier

15-5
CHUNG-YU WU

(f) Super inductor

(f) FDNR
(d) Variable Impedance Inverter (VIC) or Gyrator
* ZL is a capacitor=> Zin is a inductor=>active inductor.
* Can be used in voltage-controlled oscillator (VCO)
(h) FDNR (Frequency Dependent Negative Resistance)
R
S=j Zin(j)= 2

* Gyrator +super inductor.

3. Integrators

Gm or OTA + R or C

(a) Simple

(b) Lossy

15-6
CHUNG-YU WU

gm1

Vo/Vi=gm1/(sC+gm2)
Vo

gm2

(b) Adjustable

15-2.3 Gm-C or OTA-C filters (first-order)

(a) First-order lowpass voltage-controlled filter, fixed dc gain, pole adjustable
Vi

H(s)=

|H|
gm

Vo

Vo
gm
=
Vi sc + g m

1
gm
gm/C

(b) Lowpass, fixed pole, adjustable dc gain

|H|

Vi

H(s)=

Vo

gm

Vo
gm
=
Vi sc + 1
R

gm

1/RC

(c ) Highpass, fixed high-frequency gain, adjustable pole

|H|

H(s)=

Vi
gm

Vo

Vo
sc
=
Vi sc + g m

gm

gm/C

15-7
CHUNG-YU WU

(d) Shelving equalizer, fixed high-frequency gain, fixed pole, adjustable zero
|H|

Vi

Vo

gm

gmR>1

H(S)=

Vo R( sc + g m )
=
Vi
sRC + 1

gmR=1
gmR<1

1/RC

(e) Shelving equalizer, fixed high-frequency gain, fixed zero, adjustable pole
|H|

Vi

Vo

gm

gmR<1

H(s)=

Vo g m (1 + sRC )
=
Vi
sc + g m

gmR=1

gmR>1
1/RC

(f) Lowpass filter, adjustable pole and zero

H(s)=

|H|

C2
Vi

gm

Vo

gm

Vo
sc2 + g m
=
Vi s (c1 + c2 ) g m

C1

gm/(C1+C2)

(g) Shelving equalizer, independently adjustable pole and zero

C

|H|

Vi

Vo

gm1

1
gm2

H(s)=
gm1>gm2
gm1<gm2

Vo sC + g m1
=
Vi sC + g m 2

gm1=gm2

15-8
CHUNG-YU WU

(h) Lowpass or highpass filter, adjustable zero and pole, fixed ratio or
independent adjustment
|H|

C2

gm1/(gm1+gm2)

Vi

Vo

gm1

C1

gm

C2/(C1+C2)
gm1/(gm1+gm2) > C2/(C1+C2)

gm2

|H|
C2/(C1+C2)
gm

g m1 + sC 2
V
H(s)= o =
Vi s (C1 + C 2 ) + g m1 + g m 2

gm1/(gm1+gm2)
gm1/(gm1+gm2) < C2/(C1+C2)

(i) Phase shifter, adjustable with gm

H(s)=

C
H

Vi

Vo

gm1
gm2
R

180o

Vo
sC g m1
=
Vi sC + g m1 g m 2 R

gm2R=1
gm

90o
0o

gm1/C

15-2.4 Second-order Gm-Cor OTA-C filters

(a)

V01=

S 2 C1C 2VC + SC1 g m 2VB + g m1 g m 2V A

S 2 C1C 2 + SC1 g m 2 + g m1 g m 2

15-9
CHUNG-YU WU

Transfer functions for the biquadratic structure (a)

Circuit Type Input Conditions
Transfer Function

If gm1=gm2=gm
o Q (fixed)

g m1 g m 2
Vi=VA
o Adjustable
2
Lowpass VB and VC Grounded s C1C 2 + SC1 g m 2 + g m1 g m 2

gm
C1C 2

C2
C1

sc1 g m 2
Vi=VB
o Adjustable
Bandpass VA and VC Grounded s 2 C1C 2 + SC1 g m 2 + g m1 g m 2

gm
C1C 2

C2
C1

s 2 C1C 2
Vi=VC
o Adjustable
Highpass VA and VB Grounded s 2 C1C 2 + SC1 g m 2 + g m1 g m 2

gm
C1C 2

C2
C1

s 2 C1C 2 + g m1 g m 2
s 2 C1C 2 + SC1 g m 2 + g m1 g m 2

gm
C1C 2

C2
C1

o Adjustable
Notch

Vi=VA=VC
VB Grounded

(b)

o=

g m1 g m 2
C 2 g m1
1
, Q=
C1C 2
g m3 R C1 g m 2

* Can implement lowpass, bandpass, highpass, and notch.

* If gm3 is fixed and gm1=gm2=gm is adjusted, the poles can be moved in a
constant-Q manner.
* If gm3 is adjusted with gm1 and gm2 fixed, the pole movement in a constant-0
manner.
(c)
S 2 C1C 2Vc + SC1 g m 2VB + g m 2 g m1V A
Vo3=
S 2 C1C 2 + Sg m 3C1 + g m1 g m 2
o=

g m1 g m 2
g g
C
, Q= ( 2 ) m1 m 2
C1C 2
C1
g m3

15-10
CHUNG-YU WU

* o can be adjusted linearly with gm1=gm2=gm and gm3 constant

=> constant-bandwidth movement.
* If gm1, gm2, and gm3 are adjusted simultaneously, constant-Q pole movement.
* Interchanging "+" and "-" terminals of gm1 and gm2 and setting VA=VB=VC=Vi,
and making gm1=gm2=gm3=gm => 2nd-order gm adjustable phase equalizer.
(d)
Vc C1C 2 S 2 + VB g m 3 sC1 + g m1 g m 2V A
V04=
S 2 C1C 2 + SC1 g m 3 + g m1 g m 2

gm 1
VA

gm 2

C1

gm 3

C2

Vo4

VC VB

o=

g m1 g m 2
1
, Q=
g m3
C1C 2

g m1 g m 2 C 2
C1

* The adjustment of the bandpass version with gm1=gm2=gm will result in a

constant bandwidth, constant gain response.
(e) Elliptic biquadratic filter

x x'
VA

gm1
gm2
C1

C2

Vo

C3

Vo
S 2 + g m1 / C1C 2
C2
)(
)
H(s)= = (
Vi
C 2 + C3 S 2 + Sg m 2 /(C 2 + C3 ) + g m1 g m 2 / C1 (C 2 + C3 )
* Can be applied to the realization of high-order voltage-controlled elliptic
filters.
=>Cascading these second-order blocks with interstage unity-gain buffers.
All gm's are made equal and adjusted simultaneously.
* The voltage-controlled amplifier of Fig. (g) on p.15-3 can be
inserted between x and x'. The transconductance gain of the two OTAs in the

15-11
CHUNG-YU WU

amplifier can be used as the control variable to adjust the ratio of the zero
location to pole location.
(g) General biquadratic structure

S 2 C1C 2Vc + SC1 g m 4VB + g m 2 g m 5V A

Vo=
S 2 C1C 2 + SC1 g m 3 + g m 2 g m1
* when Vi=VA=VB=VC, the o and Q for the poles and zeros can be adjusted by
gm's to any desired value.

15-2.5 Fully Differential Gm-C or OTA-C Filters

1. General first-order filter

H(s)=

H(s)=

Vout K1 S + K o
=
Vin
S + o
SCx + Gm1
=
S (C A + C X ) + Gm 2

=>Cx=(

S(

Gm1
Cx
)+
C A + Cx C A + Cx
Gm 2
S+
CA + CX

K1
)C A , Gm1=Ko(CA+CX), Gm2=0(CA+CX)
1 K1

15-12
CHUNG-YU WU

2. General biquadratic filter

-0
-0/Q
K0/0
Vin(S)

1/S

1/S
Vout(S)

K1+K2S

H(s)=

H(s)=

Vout ( s ) K 2 S 2 + K1 S + K o
=

2
Vin ( s )
S 2 + ( o )S + o
Q

Vout ( s )
=
Vin ( s )

S2(

Design equations:

G m 2 Gm 4
Gms
GX
) + S(
)+
C X + CB
C X + CB
C A (C X + C B )
Gm 3
Gm1Gm 2
)+
S 2 + S(
C X + CB
C A (C X + C B )
CX=CB(

K2
) where 0 K 2 <1
1 K2

Gm1=oCA
Gm2=o(CB+CX)
Gm3=

o (C B + C X )
Q

Gm4=(KoCA)/o
Gm5=K1(CB+CX)

15-13
CHUNG-YU WU

15-3 CMOS Transconductor or OTA

1. CMOS transconductor using triode transistor

* Q9: operated in the triode region.

* Gm can be adjusted by Vgs9 and scaled by the current
mirrors Q3/Q7 and Q4/Q8.
* Q5/Q6 are feedback devices to set the drain voltages
of Q1/Q2.
2. CMOS transconductor using varying bias-triode transistors.

* Q3 and Q4 are in the triode region.

* Gm=

1
1
where rds3=rds4=
rs1 + rs 2 + (rds 3 || rds 4 )
2 K 3 (VGS 1 Vtn )

rs1=rs2=

I
1
1
=
VGS1-Vtn= 1
g m1 2 K 1 (VGS1 Vtn )
K1

15-14
CHUNG-YU WU

3. CMOS differential-pair transconductor with floating voltage supply.

Conceptual circuit:

Real circuit:

(iD1-iD2)= 4 K eq I B (V1 V2 )
Gm=4 K eq I B
* 30~50 dB linearity.

4. CMOS bias-offset cross-coupled transconductor.

(i1-i2)=2KVB(V1-V2)
Gm=2KVB
*30~50dB linearity

15-15
CHUNG-YU WU

15-4 Design Example of Gm-C or OTA-C Filters

Ref.: 1. IEEE Trans. Circuits and Systems, pp. 1132-1138, Nov. 1986
2. IEEE JSSC, pp.987-996, Aug. 1988
1. CMOS linear transconductance amplifier (CMOS inverter-based
complementary differential-pair transconductor)
VDD

gm=2keff (VG1+ VG 4 VT)

VG1

M1

VT=VTn1+VTn3+ VTP 2 + VTP 4

M2

keff =

Vout

Vin

M3

VG4

kn k p
( kn + k p )2

1
W
kn,p= (u eff cox ) n , p
2
L

M4

Tunable gm amplifier symbol:

VSS

2. Gm-C biquad (general)

5

VL

VB

C1

C2
VH

V2

6
Vo

V3

C1 g m SN BP + C1 g m S 2 N HP + g m N LP + (C1C 2 g m S 2 + g m L g m ) N BR
H(s)=
3
C1C 2 g m S 2 +C1 g m ( g mQ g m ) S + g m
2

NBP: VB 0 , VL=VH=0
NHP: VH 0 , VL=VB=0
NLP: VL 0 , VH=VB=0
NBR: VL=VH=VBR, VB=0

15-16
CHUNG-YU WU

Experimental results on BP filter:

Center frequency 4MHz

TABLE I
EXPERIMENTAL FILTER DATA
Control
Passband ripple
Stopband attenuation
Bandwidth
S/N in passband
Distortion (for 0.5Vpp)
Max. signal level

Automatic
1 dB
>60 dB
800 KHz
40dB

Frequency control range

Q-control range
Offset (reference inverter)

1 MHz
40%

* Smaller speed
The load of op amps is resistive

1.5 MHz
unlimited

1mV @ Gain 50

* MOSFET-C filters are slower than Gm-C filters

Miller integration.

75dB
0.5%
1.2 Vpp

15-5 MOSFET-C Filters

* Straightforward design methodology

Manual
0.5 dB

15-17
CHUNG-YU WU

1. Two-transistor integrators.

(a) Active-RC integrator

R1 R p 1 = Rn1

Vdiff Vpo-Vno=

(b) Two-transistor MOSFET-C integrator

R 2 R p 2 = Rn 2
ino i po
SC1

=
=

(i p1 + i p 2 ) (in1 + in 2 )
SC1
1
1
(V p1 Vn1 ) +
(V p 2 Vn 2 )
SR1C1
SR2 C1

2.General biquadratic MOSFET-C filter

Active-RC circuit:

MOSFET-C biquadratic filter:

15-18
CHUNG-YU WU

GG
C1 2 G2
)S + ( )S + 1 3
V ( s)
C
CB
C AC B
= B
H(S)= o
GG
G
Vi ( s )
S 2 + ( 1 )S + 3 4
GB
C AC B
(

3. Four-transistor integrators
Vdiff Vpo-Vno
=

(V pi Vni ) +

srDS 1c1

srDS 2 c1

(Vni V pi )

where rDS1=
u n cox (

rDS2=

W
)1 (Vc1 V x Vt )
L

1
W
u n cox ( ) 2 (Vc 2 V x Vt )
L

All four transistors are matched

=>Vdiff=

1
srDS c1

(V pi Vni )
1

where rDS=
u n cox (

W
)(Vc1 Vc 2 )
L

16-1
CHUNG-YU WU

CH 16. Oversampling Data Converters

16-1 Fundamental Concept
16-1.1 Oversampling without noise shaping
e(n)

1. Quantization noise modeling

x(n)

x(n)

y(n)

Quantizer

y(n)

e(n) y(n) x(n)

* e(n) can be approximated as an independent random variable uniformly
distributed between

where is the difference between two adjacent

2

quantization levels, i.e. VLSB.

2
* The quantization noise power = = Pe
12
* The quantization noise power is independent of the sampling frequency fs.
f
* The spectral density of e(n), Se(f) is white and all its power is within s .
2
fs
2
fs

fs
2
fs

S e2 ( f )df =

=>Kx=(

Se(f)

2
2
2
K x df = K x f s =
12

Height Kx

1
)
12 f s

fs
2

2. Oversampling Advantage

fs
2

H( f )

x(n)
fo

quantizer
N-bit

y(n)

y (n)
2

H(f)
filter

fs
2

-fo

fo

fs
2

Oversampling ratio OSR

f
2 fo

fs

16-2
CHUNG-YU WU

Assume that the input signal is a sinusoidal wave between 0 and 2N.
The signal power Ps is
2 2 2
) =
Ps=(
8
2 2
2 N

With H(f), Ps remains the same since the signal's frequency content is below fo,
but the quantization noise power Pe becomes
fs
2
fs

fo

Pe= S ( f ) H ( f ) df = fo K x df =
OSR 2 => Pe
SNRmax=10log(

2
e

2 f o 2 2 1
= (
)
f s 12 12 OSR

1
or -3dB, or 0.5 bits
2

Ps
3
) = 10 log( 2 2 N ) + 10 log(OSR)
Pe
2

=6.02N+1.76+10log(OSR)
=>SNR enhancement obtained from oversampling: 10log(OSR).
SNR improvement of 3 dB/octave or 0.5 bits/octave
3.The advantage of 1-bit D/A converter
* Oversampling improves the SNR, but it does not improve linearity.
* Theoretically, 1-bit converter with fo=25 KHz can obtain a 96-dB SNR(16 bits)
if the sampling frequency fs=54,000 GHz!
* The advantage of a 1-bit DAC is that it is inherently linear.

Vout

always linear

Bin

16-1.2 Oversampling with noise shaping

1. The system architecture of a oversampling ADC is shown in the next page

16-3
CHUNG-YU WU

Oversampling Delta-Sigma Analog-to-Digital Converters:

fs >> 2fo

Decimation Filter
1-bit
stream

Delta-Sigma
Delta-Sigma
A-to-D Converter
A-to-D Converter
(Modulator)
(Modulator)

Analog Signal

DSP
DSP
Decimation
Decimation
Chip
Chip

fs >> 2fo

2 fo =
Minimum
Anti-Aliasing
Filter

Analog
Delta-Sigma
Modulator

.
.
.

1
(OSR)T

Digital
Low-Pass
Filter

f0

Multi-Bit
Output

Nyquist
Rate PCM

OSR

Down Sampler
e(n)

2. Noise-shaped modulator
u(n)

X(n)

1-bit
Quantizer

H(Z)
-

y(n)

u(n)

H(Z)

X(n)

DAC
1-bit

DAC
1-bit

Two independent inputs: U(z) and E(z)

Signal Noise
Signal transfer function STF(z)

Y ( z)
H ( z)
=
U ( z) 1 + H ( z)

Noise transfer function NTF(z)

Y ( z)
1
=
E( z) 1 + H ( z)

=>Y(z)=STF(z)U(z)+NTF(z)E(z)
If H (z ) for 0<f<fo => S TF ( z ) 1 and N TF ( z ) 0
=> Quantization noise and signal unchanged.
3.First-order noise shaping:

y(n)

16-4
CHUNG-YU WU
z 1
(Noniverting Forward-Euler SC integrator)
1 z 1
H ( z)
= z 1
=>STF(z)=
1 + H ( z)

H(z)=

NTF(z)=

1
jT
j2f/fs
= (1 z 1 ) z=e =e
1 + H ( z)

NTF(f)=1-e-j2f/fs=sin (

N TF ( f ) = 2 sin(

f
) (2 j ) (e j f / fs )
fs

f
)
fs

The quantization power noise power over 0 to fo is

2 1
f
Pe= fo S ( f ) N TF ( f ) df = fo ( ) [2 sin( )]2 df
fs
12 f s
fo

2
e

fo

Since fo << fs, i.e. OSR>>1, sin(

f
f
)
fs
fs

2 2 2 f 3 2 2 1 3
=> Pe ( )( )( ) =
(
)
12 3 f s
36 OSR
P
3
3
2 2 2 N
Ps=
=> SNRmax=10 log( s ) = 10 log( 2 2 N ) + 10 log[ 2 (OSR) 3 ]
8

Pe
2
=> SNRmax=6.02N+1.76-5.17+30 log(OSR)
Double OSR => SNRmax by 9dB or 1.5bits/octave
Without noise shaping: SNRmax by 3dB/ octave or 0.5bits/ octave.

Y=Z-1U+E(1-Z-1)
Block diagram:
U

E
z 1
H ( z) =
1 z 1

+
-

Y = UZ 1 + E (1 Z 1 )

16-5
CHUNG-YU WU

SC implementation:

C
2

+
_

1
1

2
Comparator

Y
1

phase 2
Reset
Quantizer(1-bit ADC )

H(Z)

Latch
(2)

+
_

.5
0

-. 5

1-bit DAC

0. 5

Can be eliminated by connecting

the node A Directly to the node A'.

-0 . 5

-1

Control signal

First-order noise shaping with 2-bit ADC and 2-bit DAC

U
+

z 1
1 z 1

2-bit
A/D

2-bit
D/A

0. 5

+
0

.5

+
-0. 5

.75 .25 -.25 -.75

-. 5

MUX

-1

Control line

16-6
CHUNG-YU WU

4. Second-order noise shaping

H1
U +

H2

1
+
1
1 z

z 1
1 z 1

Y
Quantizer

DAC

STF(Z)=Z-1

NTF(Z)=(1-Z-1)2

N TF ( f ) = [2 sin(

Y=Z-1U+(1-Z-1)2E

f 2
)]
fs

2 4 1 5
(
)
=> Pe
60 OSR
SNRmax=10log(

Ps
3
5
) = 10 log( 2 N ) + 10 log( 4 ) + 10 log(OSR) 5
Pe
2

=6.02N+1.76-12.9+50log(OSR)
OSR2 => SNRmax by 15dB/Octave or 2.5 bits/Octave
General formula of SNRmax with k-order noise shaping:
2k + 1
) + (2k + 1) 10log(OSR)
SNRmax=6.02N+1.76- 10log(
4

OSR2=> SNRmaxby 3(2k+1)dB/Octave or 0.5(2k+1)bits/Octave

Noise-shaping transfer functions:

TF

(f)

Second-order
First-order
No noise shaping
f

s
2

The SC implementation of the second-order modulator is shown in the next page.

* Single-ended structure
* Can be converted into fully differential structure for better noise rejection and

16-7
CHUNG-YU WU

linearity.
* The capacitor and switches in the feedback path to OP2 can be reduced as
shown on page 16-5.
SC implementation: Single-Ended type circuit diagram

V+

C
2

Control
signal

1
V-

1-bit
DAC

2
1
U

2
1

C
1

2
-OP
+1

COMP-1

2
-OP
+2

Preamplifier

Latch
(2)

Comparator as quantizer or 1-bit ADC

16-8
CHUNG-YU WU

16-2 System Architecture of Oversampling ADC

1. Architecture

in

x (t )

(t )

Antialiasing
filter

Sampleand-hold

2. Signals and spectra

sh

(t )

dsm

(n)

Mod

Analog

Digital
low-pass
filter

x
dsm

sh

f
s

(f)

(n) = 1.000000K

3
12 4...

lp

OSR

x (f)

X sh (t )

x (n)

(n )

Decimation filter

Digital

(t )

lp

f
s

dsm

( )

2(f0/fs)
/6

(n)

123.....

lp

x ( )

3...

Ts

( )

/6

2(f0/fs) =
OSR OSR=6

x (n)
12

Ts

16-bit resolution in 16-bit ADC

T0
2 4 6 8 10 12

2 T
6

* The decimation process does not result in any loss of information, since the
bandwidth of the original signal was assumed to be fo. The spectral information is
spread over 0~

in Xep and 0~ in Xs.

6

16-9
CHUNG-YU WU

16-3 System Architecture of Oversampling DAC

1. Architecture

x (n)
s

OSR
2

(n )

Interpolation
(low-paaa)
fs
filter

(n )

s2

OSR

f
2f

lp

Mod

dsm

(n )

da

x (t )

(t )

Analog
low-pass
filter

1-bit
D/A
s

Digital Analog

s
()

2. Signals and spectra

x (n)
s

s2

(n )

x ( )
s

(2)

(3)

123...(1)

x
x

lp

s2

( )

(2

lp

dsm

(n )

da

( )

( )

dsm

( 2f )
0

x
c

da

( 2f )

(t )

n,t

Ts

(n)

123.....

T0

2 4 6 8 10 12

Ts

Ts

(f)

(t )

t
Time

f
s

x (f)
c

Frequency

f
s

16-10
CHUNG-YU WU

16-4 High-Order Modulators

Multi-stAge noise SHaping (MASH) architecture:
To use a cascade-type structure where the overall higher-order modulator is
constructed using lower-order ones.
=> The stability could be maintained.

Q1

z
1 z

= UZ

+ Q (1 Z

z 1

+
Q1

Q1

z
1 z 1

(1 z 1 )

YZ 1

= Q1 Z 1 + Q (1 Z 1 )

= UZ

Q (1 Z

)2

16-5 Design Considerations

16-5.1 Limitations on accuracy and linearity
A. Noise
Thermal noise in resistors, conducing switches, op-amps. Usually aliased
by sampling
1/f op-amp noise, dc offset
Supply, ground and substrate noise
clock feedthrough noise
clock jitter noise
quantization noise leakage

16-11
CHUNG-YU WU

B. Nonlinear effects
R&C nonlinearities
Amplifier nonlinearities
Finite op-amp slew rate
Signal-dependent clock feedthrough noise
Signal-dependent sampling aperture noise
Internal A/D and D/A nonlinearities
Linearity of 1-bit DAC:
1. The two output levels somehow become functions of the low-frequency
signals=> Linearity limitation
Power supply voltage are changed for different low-frequency signals to
cause distortion.
=> must be well-regulated.
The clock feedthrough of the input switches is also dependent on the gate
voltage and thus the supply voltage.
=> low-frequency input signal dependent
The clock jitter could be a function of the low-frequency input signals.
2.The memory between output levels also causes severe linearity limitation.

Typical
Ideal
V2
V1
Binary
1
1
1
1
1
1
1
Area for
A1
A0 + 2 A 0 A1 + 1 A0 + 2 A1 + 1
A1 + 1
symbol
1, 2: The area difference of the present binary state with different past states.
1-1: 2
-11: 1
Average 0 : 1, -1,1, -1,- - 1
: 1, 1, -1, 1, -1, 1--3
1
Average - : -1, -1, 1, -1, -1, 1, -1--3

Average

Va (t ) =

A1 + AO 1 + 2
+
2
2

Vb(t ) =

2 A1 + AO 1 + 2
+
3
3

Vc(t ) =

A1 + 2 AO 1 + 2
+
3
3

16-12
CHUNG-YU WU

Ideal case: 1=2=0, practical case: 1 2 0

=>Three averages do not lie on a straight line=>Nonlinear.
How to improve this nonlinearity?
1. 1=-2 : To match falling and rising signals => Very difficult to achieve.
2. The use of memoryless coding scheme, i.e. return-to-zero (RTZ) coding
scheme.

Typical
Ideal
V2
V1
Binary
Area for
symbol

1 : -11 and 11
-1 : -1-1
=> Better linearity.

-1

-1

1
A

-1
A

Every 1 has the same area.

Every -1 has the same area.

3. Basically, SCF or SC circuits are memoryless if enough time is left for settling
on each clock phase.
Idle tones phenomena
1-bit DAC
dc level

1
=> y(n)={1, 1, -1, 1, 1, -1..}
3

periodic pattern with the power concentrated at dc and

fs
.
3

After low-pass filter=> only dc level remains.

dc level

1 1 3
+
= => y(n)={1, 1, -1, 1, 1, -1, 1, 1, -1, 1, 1, -1, 1, 1, 1, -1, 1, 1, -1,
3 24 8

1,}

16-13
CHUNG-YU WU
periodic pattern with 16 cycles and some power at dc and f s .
16

=> lowpass filter

=> dc level

3
and f s tone
8
16

(fo= f s is assumed and lowpass filter will not attenuate fs/16 signal)
16

=> Low-frequency tones cannot be filtered out by the lowpass filter and can lead
to annoying tones in the audible range. They exist even in high-order modulators.
There tones might be a signal varying over some frequency range in a random-like
fashion.
Dithering technique to reduce idle tones.
To add the dithering signal to the modulator just before its quantizer.
The dithering signal has a white-noise type spectrum and is a random
(psuedo-random) signal.
The dithering signal breaks up the tones so that they never occur.
Add about 3-dB extra in-band noise
Require rechecking the modulator's stability.

16-6 Advantages and Applications

Advantages of Delta-Sigma Converters:
Low-Complexity Analog, High-Complexity Digital
High-Resolution Conversion
Low-Precision Analog (no trimming)
Simple Anti-Aliasing Filters
No Sample & Hold Needed
Can be Built Completely In CMOS
Overall Small Chip Area in Fine-Line Technology
Can be Integrated on Chip With Other DSP Functions
Ideally Suit for Rates up to and Including Audio Band
Commercial Applications Well-Suited for Delta-Sigma ADC
Standard Voice Band Telephony
13-bit dynamic range, 8-bit linearity (u/A-Law), 8KHz Sampling rate
Digital Mobile Radio (same req. as above)

16-14
CHUNG-YU WU

High-Precision Voice-Band (CCITT V.32 9600-Baud Modems)

14-15 bit dynamic range, 12-bit linearity, 3-4kHz BW, 9600 Sampling rate
ISDN Wideband Speech (CCITT G.722)
13-bit dynamic range, 16kHz Sampling rate
ISDN U-Interface
13-bit dynamic range, 80kHz Sampling rate, 160kb/s Transmission Rate
Audio-Band (CD, DAT; stereo (2))
16-18-bit (18-20 bit) resolution, 14-16 bit)(15-16bit) linearity, 48kHz
Sampling Rate
5 1/2 Instrumentation A/D Converter
20 bit resolution, 0.1-10Hz BW with Self-Calibration Circuit
Integration with Digital Signal Processors
Ideally Suited for Rates up to and Including Audio Band
A variety of applications from voice-band through audio-band

16-7 Examples
2nd-order modulator implemented by fully differential SC circuit.

16-15
CHUNG-YU WU

Testing Environment:
Digital-to-Analog Converter
Precision
Function
Generator
.
.

Low-noise cable

Pure test
Pattern

Good
Transmission Line

ADC

Mearurement

Chip under test

*Develop design-for-testability ADC and environment

The measured SNR versus input signal level.

17-1
CHUNG-YU WU

CH 17 Phase-Locked Loops (PLLs)

17-1 General architecture and Operational Principle
1. Applications of PLLs: 1. Clock recovery in communication and digital systems.
2. Frequency synthesizer used in televisions or wireless
communication systems to select different channels.
3. Demodulation of FM signals.
2.Basic PLL architecture:
Vin

+
-

Phase
detector

Vpd

Low-pass
filter V
Hlp(s)

Gain
lp

Klp

Output
voltage

Loop filter

Average voltage proportional to phase difference

VOSC

Vcntrl

VCO
Voltage-Controlled Oscillator

If the phase detector is of analog-multiplier type, its output voltage Vpd can be written
as
Vpd=KMVinVosc=KM Ein Eoscsin(t)cos(t-d)
where d is the phase difference between the input
signal Vin and the output Vosc of the VCO.
Vpd=KM Ein Eosc [sin( d ) + sin( 2t d )]
2
Since the lowpass filter is to remove the high-frequency (2) term, the signal Vcntl is
given by
E E
Vcntl=KlpKM in osc sind
2
E E
E E
KlpKM in osc d=KlpKpdd
where Kpd K M in osc
2
2
The frequency of VCO can be expressed as
osc=KoscVcntl+fr
where fr is the free-running frequency of the VCO with its control voltage Vcntl=0.

=> Vcntl=

i n f r
K osc

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CHUNG-YU WU

where in is the frequency of the input signal, which is equal to the

frequency of VCO output when the PLL is in the locked state.

=> d=

in f r
Vcntl
=
K l P K pd K l P K pd K osc

3.Linearized small-signal analysis

When a PLL is in lock, its dynamic response to input-signal phase and frequency
changes can be well approximated by a linear model, as long as these changes are
slow and small about their operating point.
A signal-flow graph for the linearized small-signal model of a PLL when in lock:

in ( s )

Kpd

KlpHlp(s)

Vcntl

osc ( s )

Kosc

1/s
Vcntl(s)=KpdKlpHlP(s)[in(s)-osc(s)]

osc(s)=Kosc(Vcntl(s)/s) ((t)=
=>

d (t )
dt

( s) =

( s)
s

SK pd K lP H lP ( s )
Vcntl ( s )
=
in ( s ) S + K pd K lP K osc H lP ( s )

General transfer function applicable to almost every PLL.

* Different PLLs => Different Hlp(s), Kpd, Kosc.
If a lead-lag lowpass filter is used in Hlp(s), we have
Hlp(s)=

1 + s z
1 + s p

z<<p

1
S (1 + s z )
Vcntl ( s )
K osc
=
=> (s)
s 2 p
in ( s )
1
1 + S(
+z) +
K pd K lp K osc
K pd K lp K osc
* H(s)=0 as s0 => in=0 leads to Vcntl=0

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CHUNG-YU WU

1
S (1 + s z )
Vcntl ( s )
K osc
=
s 2 p
in ( s)
1
1 + S(
+z) +
K pd K lp K osc
K pd K lp K osc
*

Vcntl ( s )
in ( s )

s =0

1
K osc

The above second-order s-domain transfer functions have o and Q as

o=

Q=

K pd K lp K osc

K pll

P
1
+ Z K pd K lp K osc
K pd K lp K osc

P
1
+ Z K pll
K pll

1
2

* Q= good settling behavior

Q=
Q=

1
3
1
2

= 0.577 maximally flat group delay

= 0.707 maximally flat amplitude response

* Usually Q=

1
is recommended in PLLs
2

In most cases, when o<<fr, we have

Z>>

1
2
K pll

=> Q

=> Z =

z K pll o Z

1
2

2 P 2
=
K pll o

The transient time constant pll of the complete loop for small phase or frequency
changes can be expressed as
pll

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Design considerations:

1.Choosing Kpd and Kosc based on practical considerations

2.Choose p to achieve the desired loop settling time
3.Choose Z to obtain the desired Q of the loop

f Z =0, => Q= P Kpll, o=

K pll
Q

K pd K osc
Q

(Klp=1)

4. Capture range and acquisition time

Capture range: The maximum difference between the input signals' frequency and
the VCO free-running frequency where lock can eventually be
attained.
The capture range is on the order of the pole frequency of the
lowpass filter.
Acquisition time: The time required to attain lock If the initial difference between the
input signal's frequency and the VCO frequency is moderately large,
the acquisition time tacq is
tacq

Q( i n osc ) 2

* If a PLL is designed to have a narrow loop bandwidth o, tacq can be quite large and
lock is attained too slowly.
Solution: 1. To add a frequency detector that detect when in-osc is large. Then drive
the loop toward lock much more quickly. When in-osc is small, the
frequency detector and the driver are disabled.
2. To design the lowpass filter with a programmable pole frequency o.
Initial acquisition: o speed up acquisition.
Lock
: o increase noise rejection.
3. To sweep the VCO's frequency range during acquisition with the PLL
disabled. When oscin, sweeping is disabled and PLL is activated.
5. Lock range
Lock range: Once lock is attained, the PLL remains in lock over a range as long as
the input signal's frequency in changes only slowly. This range is the
lock range, which is much larger than the capture range.
Vcntl-max=Klp KM Ein Eosc =KlpKpd
2
=> lck = KoscKlpKpd

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17-2 Phase Detectors in PLLs

Three categories: 1. Analog phase detectors (PDs) or multipliers:
Rely on the DC component when multiplying two sinusoidal
waveforms of the same frequency.
2. Sequential circuits (e.g. EXOR and Flip-Flop PDs):
Operate on the information contained in the zero-crossings of
the input signal to aid acquisition when the loop is out of lock.
Also a sequential circuit actually.
3. Phase-frequency detector:
Provide a frequency sensitive signal to aid acquisition when the
loop is out of lock. Also a sequential circuits actually.

17-2.1 Multiplier PD
Vpd =KMEinsin(1t+1)Eosccos(2t+2)
=KM Ein Eosc {sin[(1-2)t+1-2]+sin[(1+2)t+1+2]}
2
At phase lock, 1=2
=> Vpd= KM Ein Eosc [sin(1-2)+sin(2t+1+2)]
2
After the lowpass filter, we have
Vpd=KlpKM Ein Eosc sin (1-2)=KM Ein Eosc sind d if d is small.
2
2
* The multiplier PD is especially useful in applications where the reference
frequency is too high and where the loop bandwidth is sufficiently narrow so
that the filtering of the undesired components can be effective.
* The loop could lock to harmonics of the input signal.
=>False lock
* 1=2 is required.

17-2.2 EXOR PD
(a)

A
B

(b)

A
B
C=A B

17-6
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(c)
Average
value of C

-1

-0.5

0.5

* when A(Vin) and B(Vosc) are 90 out of phase, the output Vpd(c ) has =2in
and 50% duty cycle. This is a reference point. Vpd d for 0o<d<180.
* False lock could occur
* 1=2 is required.

17-2.3 Flip-Flop PD
(a)

(b)

A
B
C
(c)
Average
value of C
-1

-0.5

0.5

* The average value of Vpd or C has the shape of a saw tooth, with a linear range
of a full cycle.
* At the center of the linear range of Vpd average, the most important harmonic is
situated at the fundamental of the reference frequency as compared to the twice
of reference frequency in the EXOR PD.

17-7
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(a)

(b)

EXOR PD

Flip-flop PD

Phase
0

0.5

0.5

Center of the linear

range

Center of the linear

range

Average

Fundamental

2nd
Harmonic

17-2.4 Charge-pump PD
VDD
Ich
Vin
Vosc

Sequential
phase
detector

Pu
Pd

S1

Vlp

S2

C1

Ich R

C2

-VSS
Charge-pump phase
comparator

Low-pass filter

1. Desirable features: 1. It does not exhibit false lock.

2. Vin and Vosc are exactly in phase when the loops in lock.
3. The PLL attains lock quickly even when in is quite different
from fr.

17-8
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Some typical waveforms of a charge-pump PD

Vin

Vosc
in

Pu

2
Pd
Time

2.Small-signal analysis of a charge-pump PLL:

The average charge flow into the lowpass filter is

Iavg= in Ich
2
Iavg=Kpd(in-osc)=Kpdin
I
=> Kpd= ch
2
For the lowpass filter R, C1 has a transfer function Hlp(s) as
Hlp(s)=

Vin ( s )
1 + SRC1
1
=R+
=
I avg ( s )
SC1
SC1

Substituting Hlp(s) and Kpd into the transfer function

we have
Vlp ( s )
1
=
in ( s ) K osc

=> o =
Q=

S (1 + SRC1 )
S 2 C1
1 + SRC1 +
K pd K osc

K pd K osc
C1

1
1
1
2
=
=
RC1 o R C1 K pd K osc R C1 I ch K osc

Vlp ( s )

in ( s )

17-9
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3. Design Considerations:
(1) Choose Ich based on practical consideration like power dissipation and speed.
(2) o is chosen according to the desired transient settling-time constant pll as
o=

pll

(3) C1 is chosen from the equation of o whereas R is chosen using the equation of Q.
The chosen Q value is slightly less than what is eventually desired. R => Q
(4) Add C2 to minimize glitches.
C2 => Q => chosen Q value is smaller => Exact Q.
1
of
8 10

C2 1 ~

=> lp(s)=

C1

R
1
+
1 + SRC 2 SC1

4. Phase/Frequency detector (PFD)

* The most common sequential phase detector is the PFD.
* Asynchronous sequential logic circuit.
* 4 NOR-type RS flip-flops.
* Can also be realized in NAND gates.

Pu

Pd

FF1

Vin

FF2

Reset

set1

set2

Pu-dsbl

Pd-dsbl
FF3

FF4

set3

set4

* Basic operating principle:

Assume the PLL is in lock with Vin leading Vosc
Initial conditions: Pu=0, Pd=0, Pu-dsbl=0, Pd-dsbl=0, Reset=0 Vin=0, Vosc=0
inputs: 1001

Vosc

17-10
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Vin1
Vosc1

=> Pu=1 => Charge pumping starts and Vlp => osc
=> Reset nor gate inputs: 00010000 => Reset 01
=> Pu=0 and Pd=0 after one gate-delay ; Pd 010
Pu-dsbl=1 and Pd-dsbl=1 after two gate-delays.
=> Reset 10 after one gate-delay of Pu-dsbl1 and Pd-dsbl1
or after three gate-delays of Vosc1.
=> eeping Pu=0 and Pd=0 => charge pumping.
=> FF3 is reset and Pu-dsbl=0
It is only when Vin 10
Vosc 10 => FF4 is reset and Pd-dsbl=0

* The waveforms of a PFD when Vin is at a higher frequency than Vosc.

Vin
Vosc
Pu
Pd
Pu-dsbl
Pd-dsbl
in>osc => Pu=1 => Charge pumping to increase osc until lock is achieved.

* Transfer characteristic of a charge-pumping PFD

(a)

Up
Ref
Div

I
IC

PFD
Dn

Zlf

17-11
CHUNG-YU WU

(b)
Ref
Div
IC
(c)
Average
value of C
-1

-0.5

0.5

17-3 Loop Filters and Loop Gains

17-3.1 First-order PLL with zero-order loop filter
Loop gain of the feedback structure with in(s) and Vcntl(s)
Loop gain=GH(s)=Kpd Klp KoscHlp(s)
Zero-order loop filter: Hlp(s)=1
=> GH(S)=KpdKlpKosc

1
s

log GH ( )

Bode plots of GH(s):

1
s

PLL with zero-order loop filter

=> First-order type-1 PLL
SK pd K lp
Vcntl ( s )
=
in ( s ) S + K pd K lp K osc
close-loop transfer function

GH ( )

0
-90

17-12
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17-3.2 Second-order PLL with first-order loop-filter

First-order loop filter: Hlp(s)=

=> GH ( s ) =

1
1 + S / p

p K pd K lp K osc
S (1 + S / p )
S 2 + pS
K pd K lp K osc

Bode plots of GH(s):

log GH ( )

PLL with first-order loop filter

=> 2nd-order type-1 PLL
S p K pd K lp
Vcntl ( s )
= 2
in ( s ) S + p S + p K pd K lp K osc

GH ( )

0
-90
-180

17-3.3 Third-order PLL with second-order loop filter

To improve the transient characteristics of the PLL, a low-frequency pole a is
introduced in the loop filter. => Extra phase shift of 90.
To compensate the extra phase shift, a compensating zero z must be introduced in
order to keep the phase margin high enough.
log GH ( )
2nd-order loop filter: Hlp(s)=

=> GH(S)=

(1 + S / z )
(1 + S / p )(1 + S / a )

K pd K lp K osc (1 + S / z )
S (1 + S / p )(1 + S / a )
Bode plots of GH(S):

z c

=> Third-order type-1 PLL

S (1 + S / z ) K pd K lp
Vcntl ( s )
=
in ( s ) S (1 + S / p )(1 + S / a ) + K pd K lp K osc (1 + S / z )

If a=0
=> Third-order type-2 PLL.

GH ( )

0
-90
-180

17-13
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17-3.4 Third-order type-2 charge-pump PLL

Hlp(s)=

Loop filter:

1 + s z
s (C Z + C p )[1 + s p ]

Rz

z= RzCz
p=Rz(Cz-1+Cp-1)-1
=> GH(s)=

Cp

Cz

K pd K lp K osc (1 + s z )
S 2 (C z + C p )(1 + s p )

17-4 Voltage-Controlled Oscillators (VCOs)

Basic VCO specifications/requirements:
1. phase stability:
The output spectrum of the VCO should approximate as good as
possible the theoretical Dirac-impulse of a single sine wave, i.e. low
phase noise.
The definition of phase noise:
L{}=10 log (

noise power in a 1-Hz bandwidth at freq. +

) units: dBc/Hz
carrier power

: offset frequency

1Hz

VCO output

2. Electrical tuning range

The VCO must be able to cover the complete required frequency
band of the application, including initial frequency offsets due to
process variations.
3. Tuning linearity
To simplify the design of the PLL, the VCO gain Kosc should be

17-14
CHUNG-YU WU

constant.
4. Frequency pushing (MHz/V)
The dependency of the center frequency on the power supply
voltage.
5. Frequency pulling
The dependence of the center frequency
6. Low cost

17-4.1 Relaxation oscillator as VCO

* Multivibrator-based nonlinear oscillator.
* fosc~in the order of a few 100 MHz
* In CMOS, phase noise value of -90dBc/Hz at 500KHz offset.
Ref.: IEEE JSSC, vol.23, pp.1386-1393, Dec. 1988.

17-4.2 Ring oscillator as VCO

* Tosc=2nTd n: number of inverters; Td: one inverter delay.
* Tuning: varying the current of the inverters.
* High phase noise: switching action introduces a lot of disturbances.
* Power consumption linearly => phase noise
* Typical phase noise:
-94dBc/Hz at 1 MHz offset from a 2.2GHz carrier.
-83dBc/Hz at 100 KHz offset from a 900MHz carrier.
* Circuit structure
1. Three-stage ring oscillator
inverter

2. Differential two-stage ring oscillator

+ +

- -

+ +

- -

17-15
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3. 1-stage-delay ring oscillator

Gm

Gm

Gm

* fosc MHz ~ GHz

Ref.: 1. Proc. of IEEE 1995 Custom Integrated Circuits Conference (CICC),
pp.331-334.
2. IEEE JSSC, vol.31, pp.331-334, March 1996.

17-4.3

LC-oscillator as VCO

* Typically a 20dB better phase noise obtained over ring and relaxation oscillators.
* High-speed operation is possible due to the simple working principle.
* The realization of the inductor is the key point.
Design example: 0.7m CMOS planar-LC VCO.

M4

M3
L1

L2
Vc

Ibias
Vout+
M1

C1

C2
VoutM2

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* Constant current => To limit power dissipation

* M1 and M2: To provide a negative resistance for oscillation
* L1=L2=3.2nH planar spiral inductors
* p+ n-well junction diodes C1 and C2 as varactors for frequency tuning by Vc.
C1=C2 1pF
* Different output voltage.
Chip photograph of the VCO. (Die size 750750 m2)

L1 and L2 area consuming

Inductors used in output buffers

Measurement results:
1. Measured output spectrum for a carrier frequency of 1.81 GHz.

17-17
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2. Measured phase noise w.r.t. frequency offset

Phase noise: -116dBc/Hz at 600 KHz offset

3. Measured frequency tuning characteristics

* At Vc=0.5V, the diode varactors C1 and C2 have a larger leakage current => Phase
noise 3dB.

17-18
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17-4.4 Comparisons of Integrated VCOs

Remarks
Technology
Freq. Power Tuning Phase noise [dBc/Hz]
[-]
[GHz] [mW] [%]
reported
equiv.*
Relaxation oscillators
[Banu JSSC88] 0.75-um CMOS 0.56 50
100
-90 @500kHz -81
Tuning from 100kHz to1GHz
Reference

[Sneep JSSC90] 3-GHz Bip

0.1

30

100

-118 @1MHz

-90

Tuning from low freq. to 150MHz

[Dobos
9-GHz Bip
CICC94]
Ring oscillators
[Kwasn
1.2-um CMOS
CICC95]
[Razav JSSC96] 0.5-um CMOS

0.4

100

-110 @1MHz

-92

Tuning from 800kHz to 800MHz; Fast

start-up

0.74

6.5

- 89 @100kHz -97

Comparison of 3 designs

2.2

NA

NA

-94 @1MHz

-91

Three-stage; differential gain stage

[vd Tan
9-GHz BiCMOS 2.0
ISSCC97]
LC-tuned oscillators
[Nguye JSSC92] 10-GHz Bip
1.8

NA

95

-106 @2MHz

-96

Two-stage CCO; stacked with mixer

70

10

-88 @100kHz

-104

[Based ESSC94] 1-um CMOS

1.0

16

-95 @100kHz

-105

High-ohmic substrate; tuning with 2

tanks
Wide metal turns; substrate back-etched

[Soyue
12-GHz
JSSC96a]
BiCMOS
[Ali ISSCC96] 25-GHz Bip

2.4

50

-92 @100kHz

-110

0.9

10

N.A.

-101 @100kHz -110

*at 600 kHz offset from a 1.8-GHz carrier

4-level, extra thick metal; high-ohmic

substrate
Complete PLL; planar inductors

17-19
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Reference

Technology
[-]

Freq. Power Tuning Phase noise [dBc/Hz] Remarks

[GHz] [mW] [%]
reported
equiv.

LC-tuned oscillators(cont'd)

[Rofou ISSCC96] 1-um CMOS

0.9

10..40 14

-85 @ 100kHz -95

Front-etched inductors; quadrature

signals
Thick metal (2.1 m) and field oxide
(11m)
Linear tuning; quadrature signals

[Soyue JSSC96b] 0.5-um BiCMOS 4.0

12

-106 @ 1MHz -109

[Razav ISSCC97] 0.6-um CMOS

1.8

15

-100 @ 500kHz -102

[Dauph ISSCC97] 11-GHz BiCMOS 1.5

40

10

-105 @ 100kHz -119

[Janse ISSCC97] 15-GHz Bip

2.2

43

11

-99 @ 100kHz -116

[Parke CICC97]

0.6-um CMOS

1.6

NA

12

-105 @ 200kHz -114

Full PLL circuit; capacitor bank for

extended tuning

[Steya EL94]

6-GHz Bip

1.1

-75 @ 10kHz

Bonding wire inductor

[Crani JSSC95]

0.7-um CMOS

1.8

24

-115 @ 200kHz -124

[Crani JSSC97]

0.7-um CMOS

1.8

14

-116 @ 600kHz -116

[Crani CICC97]

0.4-um CMOS

1.8

11

20

-113 @ 200kHz -122

Hollow rectangular coils standard

process
High-Q MIS capacitor and varactor

Presented designs

-106

Bonding wire inductor; enhanced

LC-tank
2-level metal; conductive substrate;
standard CMOS
2-level metal; standard CMOS

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[Banu JSSC88] M. Banu, "MOS oscillators with multi-decade tuning range and
gigahertz maximum speed", IEEE Journal of Solid-State Circuits,
vol. 23, no. 6, pp. 1386-1393, December 1998.
[Sneep JSSC90] J. G. Sneep and C. J. M. Verhoeven, "A new low-noise 100-MHz
balanced relaxation oscillator", IEEE Journal of Solid-State Cir cuits,
vol. 25, no. 3, pp. 692-698, June 1990.
[Dobos CICC94]

L. Dobos and B. Jensen, "A versatile monolithic 800-kHz to

800-MHz phase-startable oscillator", in Proc. of the IEEE 1994

Custom Integrated Circuits Conference, San Diego, USA, May 1994,

pp. 8.4.1-4.
[Kwasn CICC95]

T. Kwasniewski, M. Abou-Seido, A. Bouchet, F. Gaussorgues,

and J. Zimmerman, "Inductorless oscillator design for personal

communication devices - a 1.2-m CMOS process case study", in
Proc. of the IEEE 1995 Custom Integrated Circuits Conference, San
Diego, USA, May 1995, pp. 327-330.
[Razav JSSC96] B. Razavi, "A study of phase noise in CMOS oscillators", IEEE
Journal of Solid-State Circuits, vol. 31, no. 3, pp. 331-343, March

1996.
[vdTan ISSCC97]

J. van der Tang and D. Kasperdovitz, "A 0.9-2.2 GHz

monolithic quadrature mixer oscillator for direct-conversion satellite

receivers", in ISSCC Digest of Technical Papers, San Fransisco,
USA, February 1997, pp. 88-89.
[Nguye JSSC92] N. M. Nguyen and R. G. Meyer, "A 1.8-GHz monolithic LC voltage
controlled oscillator", IEEE Journal of Solid-State Circuits, vol. 27,
no. 3, pp. 444-450, March 1992.
[Based ESSC94] P. Basedau and Q. Huang, "A 1-GHz, 1.5-V monolithic LC
oscillator in 1-m CMOS", in Proc. of the 1994 European

17-21
CHUNG-YU WU

Solid-State Circuits Conference, Ulm, September 1994, pp. 172-175.

[Soyue JSSC96a]

M. Soyuer, K. A. Jenkins, J. N. Burghartz, H. A. Ainspan, F. J.

Canora, S. Ponnapalli, J. F. Ewen, and W. E. Pence, "A 2.4-GHz

silicon bipolar oscillator with integrated resonator", IEEE Journal of
Solid-State Circuits, vol.31, no.2, pp. 268-270, February 1996.

[Ali ISSCC96] A. Ali and L. Tham, "A 900-MHz frequency synthesizer with
integrated LC voltage-controlled oscillator", in ISSCC Digest of
Technical Papers, San Fransisco, USA, February 1996, pp. 390-391.

[Rofou ISSCC96]

A. Rofourgan, J. Rael, M. Rofourgan, and A. Abidi, "A

900-MHz CMOS LC-oscillator with quadrature outputs", in ISSCC

Digest of Technical Papers, San Fransisco, USA, February 1996, pp.

392-393.
[Soyue JSSC96b]

M. Soyuer, K. A. Jenkins, J. N. Burghartz, and M. D. Hulvey,

"A 3-V 4-GHz voltage-controlled oscillator with integrated

resonator", IEEE Journal of Solid-State Circuits, vol. 31, no. 12, pp.
2042-2045, December 1996.
[Razav ISSCC97]

B. Razavi, "A 1.8-GHz CMOS voltage-controlled oscillator", in

ISSCC Digest of Technical Papers, San Fransisco, USA, February

1997, pp. 388-389.

[Dauph ISSCC97]

L. Dauphinee, M. Copeland, and P. Schvan, "A balanced

1.5-GHz

voltage-controlled

oscillator

with

an

integrated

LC-resonator", in ISSCC Digest of Technical Papers, San Fransisco,

USA, February 1997, pp. 390-391
[Janse ISSCC97]

B. Jansen, K. Negus, and D. Lee, "Silicon bipolar VCO family

for 1.1 to 2.2 GHz with fully integrated tank and tuning circuits, in
ISSCC Digest of Technical Papers, San Fransisco, USA, February

1997, pp. 392-393.

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[Parke CICC97] J. Parker and D. Ray, "A low-noise 1.6-ghz CMOS PLL with
on-chip loop filter", in Proc. of the IEEE 1997 Custom Integrated
Circuits Conference, Santa Clara, USA, May 1997, pp. 407-410.

[Steya EL94]

M. Steyaert and J. Craninckx, "1.1-GHz oscillator using bond-wire

inductance", IEE Electronic Letters, vol. 30, no. 3, pp. 244-245, 3rd
February 1994.

[Crani JSSC95] J. Craninckx and M. Steyaert, "A 1.8-GHz low-phase-noise voltage

controlled oscillator with prescaler", IEEE Journal of Solid-State
Circuits, vol. 30, no. 12, pp. 1474-1482, December 1995.

[Crani JSSC97] J. Craninckx and M. Steyaert, "A 1.8-GHz low-phase noise CMOS
VCO using optimized hollow inductors", IEEE Journal of
Soild-State Circuits, vol. 32, no. 4, pp. 736-744, May 1997.

[Crani CICC97] J. Craninckx and M. Steyaert, "A fully integrated spiral-LC CMOS
VCO set with prescaler for GSM and DCS-1800 systems", in Proc.
of the IEEE 1997 Custom Integrated Circuits Conference, Santa

Clara, USA, May 1997, pp. 403-406.