z80 LH0080 Tech Manual

LH0080
Z80 CPU Central Processing Unit
LHOOSO
Description
The LH0080 Z80 CPU (Z80 CPU for short below) is a general-purpose 8-bit microprocessor
fabricated using an N-channel silicon-gate process.
The LH0080A Z80A, LH0080B Z80B, LH0080E
Z80E CPU are the high speed version which can
operate at the 4MHz, 6MHz and 8MHz system
clock, respectively.
Pin Connections
LH0080/LH0080A/LH0080B/LH0080E
LH0080H/LH0080AH
Features
1. 8-bit parallel processing microprocessor
2. N-channel silicon-gate process

3. 158 instructions (The instruction of the 8080A
are included as a subset ; 8080A software compatibility is maintained)
4. 22 registers
5. The capability of 3 modes maskable interrupt
and non-maskable interrupt
6. On-chip dynamic memory refresh counter
7. Instruction fetch cycle : 1.6 s(Z80), 1.0 s
(Z80A), 0.67 s (Z80B), 0.5 s (Z80E)
8. Single + 5V power supply and single phase
clock
9. All inputs and outputs fully TTL compatible
10. 40-pin DIP (DIP40-P-600)
44-pin QFP (QFP44-P-1010A)
44-pin QFJ (QFJ44-P-S650)
LH0080M/LH0080AM
D2
D,
Do
D1
INT
NMI
HALT
MREQ
IORQ
LH0080U/LH0080AU/LH0080BU
*The GND pins must be connected to the GND level.
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ZBO CPU Central Processing Unit
Ordering Information
Product
Clock frequency
Model No.
LH0080
280 CPU
2.5MHz
LH0080
LH0080H*
LH0080M
LH0080U
Z80A CPU
4MHz
LH0080A
LH0080AH*
LH0080AM
LH0080AU
Z80B CPU
6MHz
LH0080B
Z80E CPU
8MHz
LH0080E
Package
40-pin DIP
44-pin QFP
44-pin QFJ
LH0080BU
Operating
temperature
O"C to + 70C
-20c to +85t:
o'c to +60c
oc to +70C
II suffix is a wide temperature spec, packaged in 40-pin DIP.
Block Diagram
System Data Bus
Halt State
Memory Request
Input/Output Request
Read
write
Bus Acknowledge
Machine Cycle 1
Refresh
Interrupt Request
Non+Maskable Interrupt
Wait
Bus Request
Reset
Data Bus Interface

0...
c:
0
u
nst ruct ionIr---~
bl)
c:
5
i-=
Decoder
ALU
Register
::::>
0..
Register
Array
Address Bus Interface
v..
{ + SV)
GND
System
(()V)
Clock
System Address Bus
Pin numbers apply to 40-pin DIP.
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LH0080
Pin Description
Signal
Ao-A1s
Pin name
Address bus
Do-D7
Data bus
Ml
----
MREQ
--
IORQ
RD
-
WR
--
Machine cycle one
1/0
3-state 0
Bidirectional
3-state
0
Memory request
3-state 0
l/O request
3-state 0
Memory read
3-state 0
Memory write
3-state 0
Refresh
Halt state
Wait
--
INT
Maskable interrupt
request
--
Non-maskable
RFSH
--
HALT
---
WAIT
NM!
--RESET
interrupt request
Reset
Bus request
BUSAK
Bus acknowledge
CLOCK
System clock
---
BUSRQ
----
Function
System address bus
System data bus
Active "Low". Indicates that the current machine cycle
is the OP code fetch cycle of an instruction execution.
Active "Low". Indicates that the address bus holds a
valid address for a memory read or memory write oper at ion.
Active "Low", Indicates that the lower 8 bits of the
address bus holds a valid 1/0 address for an 1/0 read
or write operation. Also generated concurrently with
MI during an interrupt acknowledge cycle to indicate an
interrupt response.
Active "Low". Indicates that the CPU wants to read data
from memory or an 110 device.
Active "Low". Indicates that the CPU data bus holds
valid data to be stored at the addressed memory or 1/0
location.
Active "Low". Indicates that the lower 7 bits of the systern address bus can be used as a refresh address to the
system's dynamic memories. Together with MREQ at
"Low".
Active "Low". Indicates that a Halt instruction is being
executed. While halted, the CPU executes NOPs to maintain memory refresh. The Halt state is cleared with RESET, NMI, or INT (when allowed).
Active "Low", Indicates to the CPU that the addressed
memory or 1/0 devices are not ready for a data transfer.
The CPU continues to enter a wait state as long as this
signal is active.
Active "Low". Generated by 1/0 devices. The CPU honors a request at the end of the current instruction if the
interrupt enable flip-flop is enabled.
Active "Low". Has a higher priority than INT. Always
recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop.
Automatically forces the Z80 CPU to restart at location
0066H.
Active "Low". Resets the interrupt enable flip-flop, the
program counter interrupt vector register and the mernory refresh register, and sets the interrupt status to
Mode 0, in order to initialize the CPU.
Active "Low". Has a higher priority than NMI. Always
recognized at the end of the current machine cycle. Activated to allow a bus master other than the CPU to control the system bus.
Active "Low". Indicates to the requesting device that the
external circuitry can control the system bus.
Inputs+ 5V single-phase clock.
-
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Z80 CPU Central Processing
Absolute
Unit
Maximum Ratings
Parameter
Input voltage
Output voltage
Symbol
VIN
VouT
Operating temperature
Topr
Storage temperature
Tstg
Note 1:
Note 2:
Note 3:
LH0080
40-pin DIP and 44-pin QFJ

44-pin QFP
40-pin DIP with wide temperature
Ratings
-0.3 to +7.0
-0.3 to +7.0
0 to +70
0 to +60
-20 to +85
-65to+150
Unit
spec.
All ac parameters assume a load capacitance of

100 pF. Add 10 ns delay for each 50 pF increase
in load up to a maximum of 200 pF for the data
bus and 100 pF for address and control lines.
DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
(Vcc=5V5%, Ta=O to +7ocNote

Symbol
V1Lc
Vmc
VIL
V1H
VoL
VoH
Current consumption
Input leakage current

3-state output leakage
current in float
Note 1:
1
2
3
Standard Test Conditions

The characteristics below apply for the follow
ing standard test conditions, unless otherwise
noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.
Note
v
v
Conditions
loL = l.8mA
loll= -250A
Iu
TYP.
]LEAK
O~VIN~Vcc
MAX.
0.45
Vcc+0.3
0.8
Vee
0.4
Unit
150
200
200
200
10
mA
mA
mA
mA
A
10
2.4
LH0080
LH0080A
LH0080B
LH0080E
Ice
MIN.
-0.3
Vcc-0.6
-0.3
2.0
YotJT =0.4 V to V cc
1)
v
v
v
v
v
v
Ta=O to +60C for 44-pin QFP

Ta= -20 to +85C for 40-pin DIP with wide temperature spec.
(f= I MHz, Ta=25C)
Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance
Symbol
Cc LOCK
C1N
CouT
Conditions
Unmeasured pins returned
to ground
MIN.
TYP.
MAX.
35
5
10
Unit
pF
pF
pF
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Unit
LH0080
(Vcc=5V5%, Ta=O to +70t:Note
AC Characteristics
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Parameter
Clock cycle time
Clock pulse width (High)
Clock pulse width (Low)
Clock fall time
Clock rise time
Clock t to address valid delay
Addreess valid to MREQ l delay
Clock l MREQ l delay
Clock t to MREQ t delay
MREQ pulse width (High)
MREQ pulse width (Low)
Clock l to MREQ t delay
Clock l to RD l delay
Clock t to RD t delay
Data setup time to clock t
Data hold time from RD f
WAIT setup time to clock l
WAIT hold time after clock l
Clock t to M 1 l delay
Clock t to M 1 t delay
Clock t to RFSH l delay
Clock t to RFSH t delay
Clock l to RD t delay
Clock t to RD l delay
Data Setup to clock 1 during
M2, M3, M4 or M5 cycles
Address stable prior to IORQ l
Clock t IORQ l delay
Clock l to IORQ t delay
Data stable prior to WR l
Clock l WR l delay
WR pulse width
Clock l to WR t delay
Data stable prior to WR l
Clock t to WR l delay
Data stable from WR t
Clock l to HALT tor l
NMI pulse width
BUSREQ setup time to clock t
BUSREQ hold time after clock t
Clock t to BUSACK l delay
Clock l to BUSACK t delay
Clock t to data float delay
Clock t to control output float
----delay (MREQ, IORQ, RD, and WR)
Clock t to address float delay
MREQ t , IORQ t , RD and WR t
to address hold time
LH0080
MIN. MAX.
400*
TcC
180*
TwCh
TwCl
180 2000
30
TfC
TrC
30
TdCr (A)
145
125 *
TdA(MREQf)
TdCf (MREQf)
100
TdCr (MREQr)
100
170*
TwMREQh
360*
TwMREQl
TdCf (MREQr)
100
TdCf (RDf)
130
TdCr (RDr)
100
TsD (Cr)
50
ThD (RDr)
0
TsWAIT (Cf)
70
ThWAIT {Cf)
0
TdCr (Mlf)
130
TdCr (Mir)
130
TdCr (RFSHf)
180
TdCr (RFSHr)
150
TdCf (RDr)
110
TdCr (RDf)
100
Symbol
Tso (Cf)
60
TdA (lORQf)
TdCr (IORQf)
TdCf (IORQr)
TdDm (WRf)
TdCf (WRf)
TwWR
TdCr (WRr)
TdDi (WRf)
TdCr (WRf)
TdWRr (D)
TdCf (HALT)
TwNMI
TsBUSRQ (Cr)
ThBUSRQ (Cr)
TdCr (BUSAKf)
TdCf (BUSAKr)
TdCr (Dz)
320*
LH0080A
MIN. MAX.
250*
llO*
110 2000
30
30
llO
65*
85
85
no '
220*
85
95
85
35
0
70
0
100
100
130
120
85
85
50
LH0080B
MIN. MAX.
165 *
65 *
65 2000
20
20
90
35*
70
70
65*
135 *
70
80
70
30
0
60
0
80
80
110
100
70
70
30
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75 *
110*
120
110
90
100
100
90
90
90
80
80
80
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TdCr (CTz)
110
80
70
60
ns
TdCr (Az)
110
90
80
70
ns
TdCTr (A)
180*
LH0080E*
MIN. MAX.
125 ..
5"o *
55 2000
10
10
80
20*
60
60
45 ..
100*
60
70
60
30
0
50
0
70
70
95
85
60
60
1)
90
llO
190*
100
260
300
so*
55
15 *
30*
70
50
0
80
50
0
160*
60
65
300
60
-55*
-55*
60*
80
80
0
70
80
80
120*
60
100*
135 *
-10*
20*
70
80
220*
55
60
5*
25 *
so*
90
360*
65
70
75
85
35 *
225
80
40
0
20*
ns
! Rising edge, !Falling edge

Note 1: Ta=O to +60"C for 44pin QFP.
Ta=-20 to +85"C for 40pin DIP with wide temperature spec.
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No.
46
47
48
49
50
51
52
53
Parameter
RESET J to clock t setup time
RESET from clock' t hold time
INT to clock t setup time
INT from clock t hold time
M 1 l to IORQ J delay
Clockk l to IORQ l delay
Clock t to IORQ t delay
Clock l to data valid delay
LH0080
LH0080
MIN. MAX.
TsRESET (Cr)
90
ThRESET (Cr)
0
TslNTf (Cr)
80
ThlNTr (Cr)
0
TdMlf (IORQf) 920*
TdCf (IORQf)
110
TdCf (IORQr)
100
TdCf (D)
230
Symbol
LH0080A
MIN. MAX.
60
0
80
0
565*
85
85
150
LH0080B
MIN. MAX.
60
0
70
0
365 *
70
70
130
LH0080E*
Unit
MIN. MAX.
45
ns
0
ns
55
ns
0
ns
270*
ns
60
ns
60
ns
115
ns
All ac parameters assume a load capacitance of 100 pF. Add 10

s delay for each 50 pF increase in load up to a maximum of 200
pF for the data bus and I 00 pF for address and control lines.
*For clock periods other than the minimums shown in the table,
calculate
parameters
using the following expressions.
Footnotes to AC Characteristics
No.
1
2
7
10
11
26
29
31
33
35
45
50
Symbol
TcC
TwCh
TdA (MREQf)
TwMREQh
TwMREQl
TdA (IORQf)
TdD (WRf)
TwWR
TdD (WRf)
TdWRr (D)
TdCTr (A)
TdMlf (!ORQf)
LH0080
TwCh+TwCl+TrC+TfC
MAX. 200 s
TwCh+TfC-75
TwCh+TfC-30
TcC-40
TcC-80
TcC-210
TcC-40
TwCl+TrC-180
TwCl+TrC-80
TwCl+TrC-40
2Tch + TwCh + TfC- 80
LH0080A
TwCh + TwCI + TrC + TfC
MAX. 200s
TwCh+TfC-65
TwCh+TfC-20
TcC-30
TcC-70
TcC-170
TcC-:30
TwCI +TrC-140
TwCl+TrC-70
TwCI + TrC- 50
2TcC+TwCh+TfC-65
LH0080B
TwCh+TwC!+TrC+TfC
MAX. 200s
TwCh+TfC-50
TwCh+TfC-20
TcC-30
TcC-55
TcC-140
TcC-30
TwCl+TrC-140
TwCl+TrC-55
TwCl+TrC-50
2TcC+TwCh+TfC-50
LH0080E
TwCh+TwCl+TrC+TfC
MAX. 200s
TwCh+TfC-45
TwCh+TfC-20
TcC-25
TcC-50
TcC-120
TcC-25
TwCl+TrC-120
TwCl+TrC-50
TwCl+TrC-45
2TcC+TwCh+TfC-45
AC Test Conditions :
Vrn=2.0V
y,.=Q.8V
Vmc=Vcc-0.6V
V1c=0.45V
VoH=2.0V
VaL=0.8V
FLOAT= 0.5
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LH0080
CPU Timing
(1)
The 280 CPU executes instructions by proceeding through a specific sequence of operations:
Memory read or write
1/0 device read or write
Interrupt acknowledge
The basic clock period is referred to as a T time
or cycle, and three or more T cycles make up a
machine cycle (Ml, M2 or M3 for instance).
Machine cycles can be extended either by the CPU
automatically inserting one or more Wait states or
by the insertion of one or more Wait states by the
user.
InstructionOpcode Fetch
The CPU places the contents of the Program

Counter (PC) on the address bus at the start of the
cycle (Fig. I). Approximately one -halfclock cycle
later, MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the CPU
data bus.
The CPU samples the WAIT input with the falling edge of clock state Tz. During clock states Ti
and T, of an M 1 cycle dynamic RAM refresh can
occur while the CPU starts decoding and executing
the instruction. When the Refresh Control signal
becomes active, refreshing of dynamic memory can
take place.
CLOCK
RD
Note: T .-Wait cycle added when necessary for slow ancilliary devices.
Fig. 1
(2)
Instructionopcode fetch
Memory Read or Write Cycles
Fig. 2 shows the timing of memoryread or write

cycles other thanan opcode fetch (Ml) cycle.
The MREQ and RD signals function exactly as in
the fetch cycle. In a memory write cycle, MREQ
also becomes active when the address bus is stable.
The WR line is active when the data bus is stable,
so that it can be used directly as an R/W pulse to
most semiconductor memories.
(3)
Input or Output Cycles
Fig. 3 shows the timing for an 110 read or l/O

write operation.
During 1/0 operations, the CPU automatically inserts a single wait state (T.). This extra wait state
allows sufficient time for an l/O port to decode the
address from the port address lines.
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LH0080
CLOCK
MREQ
WAIT
Read opera~10n{'
RD
Do-D,
Write operation
WR
=17_@__ _., '--------~1...____
-t
D0-D7
Fig. 2
;:t
Data out
Memory read or write cycles
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LH0080
CLOCK
IORQ
RD
I 10 read operation
{ Do-D7
WR
110 write operation
{ Do-D7
Note : Tw =One wait cycle automatically inserted
Fig. 3
(4)
by CPU.
Input or output
Interrupt request/acknowledge cycle
The CPU samples the interrupt signal with the

rising edge of the last clock at the end of any instructiollJfig. 4). When an interrupt is accepted, a
special Ml cycle is generated. During this Ml cy
cle, IORQ becomes active (instead of MREQ) to indicate that the interrupting device can place an 8-bit
vector on the data bus. The CPU automatically
adds two wait states to this cycle.
CLOCK
INT
Ml
IORQ
Note 1 : TL= Last state of previous instruction.

Note 2:
Two wait cycles automatically inserted by CPU ( *).
Fig. 4
Interrupt request/acknowledge cycle
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LH0080
(5)
Non-maskable interrupt request cycle
NM! is sampled at the same time as the maskable

interrupt INT but has higher priority and cannot be
disabled under software control.
The subsequent timing is similar to that of a nor-Last Mcycle
ma! instruction fetch except that data put on the

bus by the memory is ignored. The CPU instead executes a restart (RST) operation and jumps to the
NM! service routine located at address 0066H
(Fig. 5).
----~+E----------~M]----------...;;.,
Last T time T1
Ts
CLOCK
NM!
Ao-A1s
Ml
MREQ
RD
RFSH
"Although NM! is an asynchronous input. to guarantee its being

recognized on the following machine cycle. NMl's falling edge
must occur no later than rising edge of the clock cycle preceding
TtAST
Fig. 5
(6)
Non-maskable interrupt request operation
Bus request/acknowledge cycle
The CPU samples BUSREQ with the rising edge

of the last clock period of any machine cycle (Fig.
6). If BUSREQ is active, t~CPU s~ts
address,
data, and MREQ, IORQ, RD, and WR lines to a
high-impedance state with the rising edge of the
next clock pulse. At that time, any external device
can take control of these lines, usually to transfer
data between memory and 1/0 devices .
(7)
Reset cycle
RESET must be active for at least three clock cycles for the CPU to properly accept it. As long as
RESET remains active, the address and data buses
float, and the control outputs are inactive. Once
RESET goes inactive, three internal T cycles are
consumed before the CPU resumes normal processing operation. RESET clears the PC register, so
the first opcode fetch will be location 0000 (Fig. 8).
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LH0080
RFSH
Unchanged
HALT
Note: Tt=Last state of any M cycle.
Tx=An arbitrary clock cycle used by requesting device.
Fig. 6
Ml
Z-bus request/acknowledge cycle
"I"'
"I"'
Ml
Ml
CLOCK
HALT
rt
HALT instruction received
NM!
~~~~~~~~~~~~~~~-
Note: INT will also force a Halt exit.
Fig. 7
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Halt acknowledge cycle
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Unit
LH0080
Ml-Ti
T2
CLOCK
RESET
Ml
MREQ.
RD.WR,
IORQ,RFSH,
BUSAK,
HALT
Fig. 8
Reset cycle
CLOCK
Ml
RESET
Fig. 9
Timing diagram when M1 cycle has no wait state
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LH0080
Unit
<Reference>
The RAM contents may be adversely affected by

resetting the CPU while it is in operation.
To prevent this, a RESET signal should be input
in the following timings.
(1) No wait state in the M 1 cycle
Input a RESET signal to start sampling this signal at the clock rising in the Ml cycle's T, state.
(See Fig. 9.)
(2)
A walt state in the M 1 cycle

Input a RESET signal to start sampling this signal at the clock rising in the Ml cycle's T3 state.
(See Fig. 10.)
CLOCK
Ml
MREQ
RESET
Fig. 10
Reset circuit and timing diagram when

M1 cycle has a wait state
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LH0080
CPU Registers
I
A Accumulator
B General Purpose
D General Purpose
H General Purpose
F Flag Register
C General Purpose
E General Purpose
L General Purpose
A' Accumulator
B' General Purpose
D' General Purpose
H' General Purpose
F' Flag Register

C' General Purpose
E' General Purpose
L' General Purpose
8 bits---~
I Interrupt Vector
I R Memory Refresh
Index Register
IX
IY
Index Register
SP
Stack pointer
Program Counter
PC
+---------16 bits--------~
+------
Architecture
(1)
CPU Registers
( i) Program Counter (PC)

The program
counter holds the 16 bits memory address of a cur
rent instruction. The CPU fetches the contents
from memory address specified by the PC.
The PC feeds the data to the address line, auto
matically setting the PC value to
1. When a program jump takes place, a new value is directly set to
the PC.
(ii)
Stack Pointer (SP)
The stack pointer
holds the top 16-bit address of the stack with an
external RAM. An external file is based on LIFO
(Last-In, First-Out).
The data are transferred between a Cl'Ur specified register and the stack by a PUSH or POP in
struction. The last-pushed data are first popped
from the stack.
(iii) Index Register (IX & IY)
For index
mode addressing, there are independent index reg
isters IX and IY, each of which holds 16-bit refer
ence address.
In the index mode, the index registers are used to
designate the memory area for data input/output.
With an INDEX ADDRESSING instruction, an
effective address comes by adding a one-byte dis
placement to the register content. This displace
ment is an integral signed two's complement nurnber
(iv) Interrupt Register (I)
The 280 CPU has
indirect subroutine call mode for any memory area
according to an interrupt. For this purpose, this
register stores the upper 8 bits of memory address
for vectored interrupt processing and the lower 8
bits for the interrupting device.
----------SHARP__._._._.
The built-in re(v) Refresh Register (RI

fresh register provides user-transparent
dynamic
memory refresh. Its lower 7 bits are automatically
incremented during each instruction fetch cycle.
While the CPU records a fetched instruction and
executes the instruction, the refresh register data
are placed on the address bus by a REFRESH con
trol signal.
(vi) Accumulator and Flag Register (A & F)
The CPU has also two independent 8-bit accumulators in combination with two 8-bit flag registers.
The accumulators store an operand or the re
suits of an 8-bit operation. The flag registers, on
the other hand, deal with the results of an 8-bit or
16-bit operation; for example, seeing if the result
is equal to 0 or not.
(vii) General-Purpose Registers
There are
several pairs of general-purpose
registers. In each
pair, they can be used separately or as a 16-bit
paired register. The paired registers are BC, DE,
HL, as well as BC' DE' HL'. Either of these sets can
work by an "Exchange" instruction at any time on
a program.
(2)
Arithmetic/Logical
Unit (ALU)
An 8-bit arithmetic/logical
operation instruction
is executed by the ALU inside the CPU. The ALU
connects to each register through the internal bus
for data transfer between them.
(3)
InstructionRegister, CPU Control
Each instruction is read out of the memory, held

in the instruction register, and decoded. The con
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LH0080
trol unit controls this action and gives control signals necessary to read and write data from and to
the registers.
The control unit also makes ALU control signal
and other external control signals.
<Interrupts : General Operation> The 280 CPU
accepts two interrupt input signals: NM! and INT.
The NM! is a non-rnaskable interrupt and has the
highest priority. INT is a lower priority interrupt
and it requires that interrupts be enabled in software in order to operate.
(1)
Non-Maskable Interrupt (NM!)
The non-rnaskable interrupt will be accepted at

all times by the CPU.
After recognition of the NM! signal, the CPU
jumps to restart location 0066H.
(2)
Maskable Interrupt (INT)
The maskable interrupt, INT, has three

rammable response modes available.
( i)
mode
terrupt
prog-
Mode _O Interrupt Operation.

is similar
microprocessor
This
in-
The interrupting
de-
to the 8080A
service procedures.
Table
Lower
byte
Upper byte
vice places an instruction on the data bus. This is a

Restart instruction or a Call instruction.
(ii) Mode 1 Interrupt Operation.
Mode 1
operation is very similar to that for the NM!. The
principal
difference is that the Mode 1 interrupt
has a restart location of 0038H only.
(iii)
Mode 2 Interrupt Operation.
This interrupt mode has been designed to utilize most
effectively
the capabilities of the 280 microprocessor and its associated peripheral family. The
interrupting peripheral device selects the starting
address (16 bits) of the interrupt service routine. It
does this by placing an 8-bit vector on the data
bus during the interrupt acknowledge cycle. The
CPU forms a pointer using this byte as the lower
8-bits and the contents of the I register as the upper 8-bits. This points to an entry in a table of
addresses for interrupt service routines. The CPU
then jumps to the routine at that address.
All the 280 peripheral devices have the interrupt priority circuit with a daisy-chain
configuration. During an interrupt acknowledge cycle, vectors are automatically fed. For more details, refer
to the 280 PIO description.
;--yPointe; b~its
7_b-its
I~
'-----From
application device
I register contents
To the beginningof service rotine
Fig. 1
_._..-------SHARP--------.--___..
298
Mode 2 interrupt diagram
promsoft.com
LH0080
Instruction Set
Table 1
Symbolic
operation
r+-r
Mnemonic
LD r, r
LD r, n
Le-r-Fl
LO r, (HL)
LO r, (IX+d)
r+- (HL)
r+- (IX +d)
LD r, (IY+d)
r+- (IY +ct)
LO (HL), r
LO (IX+d), r
(HL)..-r
(IX +d)+--r
LD (IY+d), r
(IY +d)+-r
LO (HL), n
(HL)+-n
LD (IX+d), n
(IX +d)+-n
LD (IY+d),
(IY+d)+--n
OP code
HEX code
76 543 210 (Basic)
r
r
01
40+
00 r 110
06+
+n -+
01 r 110
46+
11 011 101
DD
46+
01 r 110
+- d -+
FD
11 111 101
01 r 110
46
+- d -+
01 110 r
70+
11 011 101
DD
01 110 r
70+
+- d -+
11 111 101
FD
01 110 r
70+
+- d -+
00 110 110
36
+- n -+
11 011 101
DD
00 110 110
36
__.
+-d
+--
LD A, (BC)
LD A, (DE)
LD A, (nn)
LO (BC), A
LD (DE), A
LO (nn), A
A +-- (BC)
A+-- (DE)
A +-- (nn)
(BC) +-- A
(DE)+-- A
(nn) +-- A
LO A,I
A+-- I
LOA,R
A+--R
LOl,A
I+- A
LOR, A
R +-A
11
00
+-+-00
00
00
+-+-00
00
00
+-+-11
01
11
01
11
01
11
01
n
111
110
d
n
001
011
111
n
n
000
010
110
n
n
101
010
101
011
101
000
101
001
8-bit load group

Flags
c z
P/V
No. of No. of No. of

Bytes M Cycles T States
1
1
4
2
2
7
r.r
1
3
2
5
7
19
19
1
3
2
5
7
19
19
10
19
19
OA
lA
3A
1
1
3
2
2
4
7
7
13
02
12
32
1
1
3
2
2
4
7
7
13
Comments
000
001
010
011
100
101
111
Reg.
B
c
D
E
H
L
A
-+
101
110
FD
36
-+
-+
010
010
010
-+
-+
010
010
010
-+
-+
101
111
101
111
101
111
101
111
ED
57
ED
5F
ED
47
ED
4F
IFF
!FF
Notes: r, r' means any of the registers A, B, C, D, E, H, L, !FF the content of the interrupt enable flip-flop, (!FF) is copied into the P/V flag.
Flags: C (carry), Z (zero), S (sign), P/V (parity/overflow), H (half carry), N (add/substract).
: =unchanged, 0 =reset, 1 =set, X =undefined.
t set or reset according to the result of the operation.
299
promsoft.com
LH0080
ie-en
Table 2
LO dd, nn
Symbolic
operation
dd +-- nn
LO IX, nn
IX+-- nn
LO IY, nn
IY +-- nn
LO HL, (nn)
H +-- (nn+l)
L +-- (nn)
Mnemonic
LO dd, (nn)
LO IX, (nn)
LO IY, (nn)
LO (nn), HL
LO (nn), dd
LO (rm), IX
LO (nn), IY
LO SP, HL
LO SP, IX
LO SP, IY
PUSH qq
PUSH IX
PUSHIY
POP qq
POP IX
POPIY
Notes :
Flags:
OP code
HEX code
76 543 210 (Basic)
00 ddO 001
01+
+-- n -+
+-- n -+
11 011 101
DD
21
00 100 001
+-- n -+
+-- n -+
FD
11 111 101
00 100 001
21
+-- n -+
+-- n -+
00 101
+-- n
+-- n
ddn +- (nn+ 1) 11 101
ddi +-- (nn)
01 ddl
+-- n
+-- n
IXH +- (nn+J) 11 011
IXL +-- (nn)
00 101
+-- n
+-- n
IYH +- (nn+I) 11 111
IYL +-- (nn)
00 101
+-- n
(nn + 1) +-- H 00 100
+-- n
(nn) +-- L
+-- n
(nn+l) +- ddu 11 101
(nn) +-- ddi
01 ddO
+-- n
+-- n
(nn+ l)+-IXH
11 011
(nn) +-- IXL
00 100
+-- n
+-- n
(nn+l)+-IYH
11 111
(nn) +-- IYL
00 100
+-- n
+-- n
SP +-- HL
11 111
SP +--IX
11 011
11 111
SP +-- IY
11 111
11 111
(SP-2)+-qqL
11 qqO
(SP-1)+-qqH
(SP-2)+-IXL
11 011
(SP-1)+-IXH
11 100
(SP-2)+-IYL
11 111
(SP-1)+-IY
11 100
QQH +-(SP+ l) 11 qqO
QQL +-- (SP)
IXH+-(SP+l)
11 011
IXL +-- (SP)
11 100
IYH .... (SP+l) 11 111
IYL +--(SP)
11 100
010
Flags
c z
P/V
ED
4B+
DD
2A
-+
No. of No. of No.of

10
3
3
4
14
14
16
20
20
20
16
20
Comments
dd
00
01
10
2A
-+
101
011
load group
11
Reg.
BC
DE
HL
SP
nn : 2-byte number.
Lower byte just
after opcode.
Upper byte comes
next.
-+
-+
101
010
-+
-+
ED
43+
DD
22
20
FD
22
20
001
101
001
101
001
101
F9
DD
F9
FD
F9
C5+
1
2
1
2
6
10
10
11
101
101
101
101
001
DD
E5
FD
E5
Cl+
15
15
10
101
001
101
001
DD
El
FD
El
14
14
101
010
FD
2A
-+
010
22
-+
-+
101
011
-+
-+
101
010
-+
-+
101
010
-+
-+
qq
00
01
10
11
Reg.
BC
DE
HL
AF
dd is any of the register pairs BC, DE, HL, SP.

qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively, e.g., BCL=C, AFH=A.
=unchanged, O=reset, 1 =set, X=undefined, f =set or reset according to the result of the operation
.--------SHARP--------300
promsoft.com
Table 3
Mnemonic
EX DE, HL
EX AF, AF'
EXX
EX (SP), HL
EX (SP), IX
EX (SP), IY
LDI
LDIR
LDD
LDDR
CPI
CPIR
CPD
CPDR
Symbolic
operation
DE-HL
AF-AF'
(~~)-(~~:)
HL
HL'
H +-+ (SP+l)
L-(SP)
IXH +-+ (SP+l)
IXL - (SP)
IYH - (SP+l)
IYL - (SP)
(DE) +-- (HL)
DE ... DE+l
HL +-- HL+ 1
BC+-- BC-1
(DE) +-- (HL)
DE .... DE+l
IJL +-- HL+ 1
BC+-- BC-1
If BC=O end
(DE) +-- (HL)
DE .... DE-1
HL +-- HL-1
BC+-- BC-1
(DE) +-- (HL)
DE ... DE-l
HL +-- HL-1
BC+-- BC-1
If BC=O end
A- (HL)
HL +-- HL+l
BC+-- BC-1
A- (HL)
HL +-- HL+l
BC+-- BC-1
If A= (HL) or
BC=O end
A- (HL)
HL +-- HL-1
BC+--BC-1
A- (HL)
HL +-- HL-1
BC+-- BC-1
If A= (HL) or
BC=O end
LH0080
Exchange, block transfer, block search groups
OP code
HEX code
76 543 210 (Basic)
11 101 011
EB
00 001 000
08
11 011 001
D9
11 100 011
E3
11
11
11
11
11
10
101
011
101
0l l
101
000
E3
FD
E3
ED
AO
11 101 101
10 110 000
ED
BO
11 101 101
10 101 000
ED
11 101 101
10 111 000
ED
B8
11 101 101
10 100 001
ED
Al
11 101 101
10 110 001
ED
Bl
011
100
111
100
101
100
DD
AB
11 101 101
10 101 001
ED
A9
11 101 101
10 111 001
ED
B9
Flags
c z
P/V

CDi

i
CD

Comments
l
l
4
l
1
4
4
Register bank and
1
1
auxiliary register
bank exchange
19
1
5
2
23
23
Load (HL) into (DE),
increment the pointers and decrement
the byte counter(OC)
If BCio 0
16
21
2
2
4
4
16
16
If BC=O
21
If
2
2
4
4
16
16
If BC=O
t
@
CD
t
CD
21
If BCio 0 and
Aio(HL)
2
16
t t t
CD
16
t t
21
t
@
sc+ o
CD
If BC=O or
A= (HL)
If BCio 0 and
Aio(HL)
2
16
If BC=O or
A= (HL)
Note:
(!)P/V flag is 0 if the result of BC=O, otherwise P/V= I

@Z flag is I if A= (HL), otherwise Z=O
Flags : = unchanged
0 = set,
I = reset
i = set or reset according to the result of the operation
------.-.---SHARP.-..-.----.-.---301
promsoft.com
LH0080
Table 4 8-bit arithmetic and logical group

Mnemonic
ADD A, r
ADD A, n
ADD A, (HL)
ADD A, (IX +d]
ADD A, (IY+ d)
ADC A, s
SUB s
SBC A, s
AND s
OR s
XOR s
CP s
INC r
INC (HL)
INC (IX+d)
INC (IY+d)
DEC m
Symbolic
operation
A+-A+r
A+-A+n
OP code
HEX code
76 543 210 (Basic)
k
r
10
80+
11 k 110
C6+
+n --+
A+- At (HL)
10 k 110
86+
A +- At (Ix+ d) 11 011 101
DD
10 k 110
86+
+d --+
A+- At (IY+d) 11 111 101
FD
10 k 110
86+
+d --+
A+- A+s+C
4 types
A+-A-s
available
A+-A-s-C
based on
A+- A/\s
the above ADD
A+-AVs
instruction
A+- AEBs
(see Comments)
A-s
r +- r+l
r
00
00+
(HL) +- (HL) + 1 00 110 e
30+
(IX+d)+II Oil 101
DD
(IX+d)+l
00 110 e
30+
+d --+
(IY+d)+FD
11 111 101
(IY+d)+l
30+
00 110 e
+d --+
m +-m-1
4 types
available
based on
the above INC
instruction
Flags
c z PIV s
t t v t
t t v t
N
0
0
t v t
t v t
0
0
t
t
t
t
t
t v
t v t
t v t
i
t
t
t
t
t
v
v
v
v
t
t
t
t
t
0
0
0
i
i
i
0
1
1
0
0
0
1
0
0
0
i
i
t
t
t
t
t
1
3
302
r
000
001
010
011
100
101
111
7
19
19
Mnemonic
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
Reg.
B
c
D
E
H
L
A
k
000
001
010
011
100
110
101
111
1 liil
2
2
5
4*1
7
7
19
1
1
3
1
3
6
4
11
23
S=r, n, (HL),
(IX+d), (IY+d)
23
i
i
i
I *2
I
3
3
Note : V and P mean overflow and parity, respectively.

Flags : =unchanged
O=reset
l==set
X=undefined
f =set or reset according to the result of the operation
---------SHARP..__.
2
5
Comments
1 liil
2
1
3
1
0
0

1
4
1
2
7
2
1 *2
3
6
6
4*2
11
23
23
Mnemonic
INC
DEC
e
100
101
m=r, (HL),
(IX+d), (IY+d)
111 l: depends on s.
1112: depends on m.
_.
promsoft.com
Table 5
CPL
Symbolic
operation
Decimal
adjustment
(add/subtract)
A-A
NEG
A-O-A
Mnemonic
DAA
IM l
lM 2
Note
Flags .
LH0080
General purpose arithmetic and CPU control groups
HEX code
OP code
76 543 210 (Basic) c
00 100 111
27
i
00 101 Ill
11
01
c-c
00
c-1
00
No operation 00
01
CPU halted
IFF- 0
11
!FF+- 1
11
Set interrupt 11
01
mode 0
Set interrupt II
mode 1
01
Set interrupt 11
mode 2
01
CCF
SCF
NOP
HALT
DI
EI
IM 0
Unit
101
000
111
110
000
110
110
111
IOI
000
101
010
101
011
101
100
111
111
000
110
011
011
101
110
101
110
101
110
2F
ED
44
3F
37
00
76
F3
FB
ED
46
ED
56
ED
5E
Mnemonic
ADD HL, SS
ADC HL,
SS
SBC HL, SS
ADD IX, pp
ADD IY, rr
1
1
1
1
1
1
2
1
1
1
1
1
1
2
4
4
4
4
4
4
8
00 x0
Complement
accumulator
(one's complement).
Negate acc.
(two's complement).
Complement carry flag.
Set carry flag.
Interrupt not enable

Interrupt enable
Set interrupt mode.
16-bit arithmetic group
Symbolic
OP code
HEX code
operation
76 543 210 (Basic) c
HL +-HL
00 ssl 001
09+
i
+ss
HL-HL
11 101 101
ED
i
+ss+C
01 ssl 010
4A+
HL-HL
11 101 101
ED
i
-ss-C
01 ssO 010
42+
DD
IX - IX+pp 11 011 101
i
00 pp! 001
09+
lY - IY+rr 11 111 101 FD
i
00 rrl 00)
09+
00 ssO 011
03+
ss - ss+ 1
11 011 101
DD
IX - IX+l
00 100 011
23
IY- IY+l
11 111 101
FD
00 100 011
23
ss +- ss-1
00 ssl 011
OB+
11 011 101
DD
IX - IX-1
00 101 011
28
11 111 101
FD
IY - IY-1
00 101 011
2B
INC SS
INC IX
INC IY
DEC SS
DEC IX
DECIY
Flags:

Comments
1
1
4
Decimal adjust
accumulator.
PIV
!FF indicates the interrupt enable flip-flop, CY indicates the carry flip-flop.
=unchanged, 0 =reset, 1 =set, X =undefined, f =set or reset according to the result of the operation
Table 6
Note :
Flags
ss is any of the
pp is any of the
rr is any of the
=unchanged,
register pairs BC, DE, HL, SP.

register pairs BC, DE, IX, SP.
register pairs BC, DE, IY, SP.
O=reset, 1 =set, X=undefinede,
Flags
N
0
v i
15
15
15
15
1
2
1
2
6
10
10
1
2
1
2

1
11
3
PIV
i v
Comments
00
01
10
11
Reg.
BC
DE
HL
SP
pp
00
01
10
11
Reg.
BC
DE
IX
SP
6
10
rr
00
01
10
10
11
Reg.
BC
DE
IY
SP
SS
f =set or reset according to the result of the operation
--.-------SHARP-------.----303
promsoft.com
LHOOBO
Table 7
Symbolic
operation
Mnemonic
RLCA
Flags
OP code
HEX code
76 543 210 (Basic)
c z
00 000 111
07
00 010 111
17
00 001 111
OF
00 011 111
lF
11
00
11
00
11
11
CB
00+
CB
06+
DD
4iH8}J
RLA
Rotate and shift groups
RRCA
RRA
RLCr
RLC (HL)
RLC (IX+d)
r, (HL),
+--
(IX+d),
(IY +d)
00
11
11
RLC (IY+d)
+--
00
RL m
001 011
k
r
001 011
k 110
011 101
001 011
d -+
k 110
111 101
001 011
d -+
k 110
RR m
4i3=@J
06+
FD
SRA m
SRL m
RLD
RRD
No. of
No. of
No. of
Comments
Rotate left circular

accumulator.
Rotate left
accumulator.
Rotate right circular 1

accumulator.
Rotate right
accumulator.
Rotate left circular
register r.
15
23
23
CB
r
000
001
010
011
100
101
111
Reg.
B
c
D
E
H
L
A
06+
SLA m
CB
RRC m
P/V
Mnemonic
RLC
RRC
RL
RR
SLA
SRA
SRL
000
001
010
011
100
101
111
m=r, (HL),
(IX+ d), (JY + d)
"depends on m.
2*
2
4
4
2*
4
6
6
g*
15
23
23
A~
11 101 101
(HL) 01 101 111
ED
6F
18
A~
11 101 101
01 100 111
(HL)
ED
67
18
Rotate digit left and

right between the
accumulator and
location (HL).
The content of the
upper half of the
accumulator is unaffected.
Flags : =unchanged
O=reset
l=set
X =undefined
t =set or reset according to the result of the operation
-----------SHARP-------304
promsoft.com
Unit
LH0080
Table 8 Bit set, reset and test group

Mnemonic
BIT b, r
Symbolic
OP code
operation
z-
76 543
11 001 Oll
fb
BIT b, (HL)
Z-(HL)
BIT b, (IX +d)
Z - (IX+d)
ll 001 Oil
01
b llO
11 Oll 101
11 001 Oil
CB
d
b
01
SET b, (HL)
SET b, (IX+d)
ll
a
(HL) +- 1
ll
a
(IX+d) +- 1 ll
ll
r +-I
(IY+d)b
+-
a
I 11
RES b, m
FD
CB
llO
46+
CB
001 Oll
CB
llO
06+
011
101
DD
001
011
CB
-+
llO
06+
111
101
FD
Oil
CB
11 001
+d
CB
P/V
x x
N
0
Bytes
No. of
No. of
Comments
M Cycles T States
x x
12
x x
20
Reg.
000
001
010
Oll
100
101
H
L
111
Bit Tested
000
20
-+
001 011
+SET b, (IY+d)
DD
46+
IOI
11 001 Oil
d
46+
No. of
Flags
c z
-+
110
11 111
+-
SET b, r
CB
40+
01
Z - (IY+d)
(Basic)
01
BIT b, (IY+d)
HEX code
210
15
23
23
-+
110
001
010
Oll
100
101
110
111
Mnemonic
SET
11
RES
10
06+
mb+-0
2*
2*
15
s*
m=r,
23
(IX+ d), (IY + d)
23
(HL),
"depends
on m
Note : The notation ms indicates bit b (0 to 7) or location m.

Flags : =unchanged
O=reset
l=set
X=undefined
t =ser or reset according to the result of the operation
.-.--------SHARP_..
_..~--
305
promsoft.com
LH0080
Table 9 Jump group

Mnemonic
JP nn
JP cc, nn
Symbolic
OP code
HEX code
operation
76 543 210
(Basic)
PC+- nn
If condition cc
is true PC
+-
11
nn,
otherwise con
.....
.....
n
n
cc
n
n
tinue
JR e
PC+- PC+e
010
--
00 011 000
+-
JR C, e
--
11 000 011
.....
.....
e2
C2+
18
-+
If C=l
00 111 000
PC+- PC+e
+-
e 2
C3
38
-+
Flags
c z
P/V
No. of
N
If C=O
continue
JR NC, e
lfC=O
00 110 000
PC+- PC+e
+-
e2
30
-+
If C=l
continue
JR Z, e
If Z=l
00 101 000
PC+- PC+e
+-
e-2
28
-+
lfZ=O
continue
JR NZ, e
lfZ=O
00 100 000
PC+- PC+e
+-
e-2
20
-+
If Z= 1
continue
JP (HL)
PC+- HL
11 101 001
E9
JP (IX)
PC+- IX
11 Oll 101
DD
11 101 001
E9
JP (IY)
DJNZ, e
PC+-IY
11 111 101
FD
11 101 001
E9
IfB+-B-1
00 010 000
10
B*O
+-
e-2
-+
Bytes
3
No. of
No. of
Comments
M Cycles T States
3
10
10
10
12
12
cc
Condition
000
NZ
001
010
NC
011
100
PO
101
PE
110
111
NZ : non-zero
Z : zero
C : carry
2
12
PO : parity odd
PE : parity even
P : sign positive
M : sign negative
12
12
13
PC+- PC+l
If B=O
continue
Note : e represents the extension in the relative addressing mode.
e is a signed two's complement number in the range <-126,
129>
e - 2 in the opcode provides an effective address of pc+ e as PC is incremented by 2 prior to the addition of e.
e itself is obtained from opcode position.
Flags : =unchanged
O=reset
l=set
X=undefined
i =set or reset according to the result of the operation
__..--------SHARP----.---_.306
promsoft.com
ZBO CPU Central Processing
Unit
LH0080
Table 10 Call and return group

Mnemonic
CALL nn
CALL cc, nn
RET
RET cc
RETI
RETN
RST p
Symbolic
operation
(SP-1) ..... PCH
(SP-2) ..... PCc
PC+- nn
If condition cc is
false continue,
otherwise same
as CALL nn
PCL +-(SP)
PC .... (SP+ I)
If condition cc is
false continue,
otherwise same
as RET
Return from
interrupt
Return from
non-mask able
interrupt
(SP-1) +- PCH
(SP-2) +- PCL
PCH +- 0
PCL +- p
OP code
HEX code
76 543 210 (Basic) c
11 001 101
CD
+n
+n
C4+
11 cc 100
+n
+n
--
C9
11
co+
II 101 IOI
01 001 101
11 101 101
01 000 101
ED
4D
ED
45
11
C7+
111
l l 001 001
000
P/V
cc
Flags

3
17
5
17
10
10
11
14
14
11
Comments
cc
000
001
010
011
100
101
llO
ll 1
Condition
NZ
r
000
001
010
011
100
101
llO
l ll
p
OOH
08H
10H
18H
20H
28H
30H
38H
z
NC
c
PO
PE
p
M
Flags : =unchanged
O=reset
1 =set
X=undefined
i =set or reset according to the result of the operation
_._....-:------SHARP---------307
promsoft.com
LH0080
Table 11
IN A, (n)
Symbolic
operation
A+-(n)
IN r, (C)
r +- (C)
Mnemonic
INI
INJR
IND
INDR
OUT (n), A
(HL) +- (C)
B +-B-1
HL +- HL+l
(HL) +- (C)
B +- B-1
HL +- HL+l
Repeat until
B=O
(HL) +- (C)
B +- B-1
HL +- HL-1
(HL) +- (C)
B+-B-1
. HL +- HL-1
Repeat until
B=O
(n)+-A
OUT (C), r
(C) +- r
OUT!
(C) +- (HL)
OTIR
OUTD
OTDR
B +- B-1
HL +- HL+l
(C) +-(HL)
B+-B-1
HL +- HL+l
Repeat until
B=O
(C) +- (HL)
B +-B-1
HL +- HL-1
(C) +- (HL)
B +- B-1
HL +- HL-1
Repeat until
B=O
Input and output group
OP code
HEX code
76 543 210 (Basic)
11 011 011
DB
+- n -+
11 101 101
ED
01 r 000
40+
11 101 101
ED
10 100 OIO
AZ
11 101 101
10 110 010
ED
B2
Flags
c z
P/V

t t t
p
x t x x
No. of
No. of
No. of
16
C--+ Ao-A,
B--+ AA-A1c,
21
r
000
001
010
011
100
101
111
Comments
n --+ Ao-A7
2
11
3
Ace--+ Ax-A1c,
2
12
3
<D
x x
{If Bio 0)
11 101 101
10 101 010
ED
AA
x t x x
11 101 101
10 Ill 010
ED
BA
010 011
n -+
101 101
r 001
101 101
100 011
D3
11 101 101
10 110 011
ED
B3
ED
41 +
ED
A3
16
16
5
(If BioO)
4
llf B=O)
21
11
12
CD
1
x x
11
+II
01
11
10
4
(IfB=O)

x t x x
Reg.
B
c
D
E
H
L
A
16
n --+ (ABUS)o-
Ace--+ (A-BUSk15
16
C--+ Ao-A7
5
(If8*0)
4
ill B=O)
21
B-+ AH-A10
<D
x x
11 101 101
10 101 011
ED
AB
x t x x
11 101 lOI
IO 111 Oil
ED
BB
16
16
5
(If Bioa)
4
{If B=O)
2I
CD
1
x x
16
(I)If the result of B-1 is zero the Z flag is set, otherwise it is reset.
@z flag is set upon instruction completion only.
Flags : =unchanged
O=reset
l=set
X=undefined
t =set or reset according to the result of the operation
Note :
------------SHARP----------308
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LH0080

Z80 CPU Central Processing Unit

Z80 CPU Central Processing Unit

2. N-channel silicon-gate process

*The GND pins must be connected to the GND level.

ZBO CPU Central Processing Unit

II suffix is a wide temperature spec, packaged in 40-pin DIP.

Data Bus Interface

Address Bus Interface

System Address Bus

Pin numbers apply to 40-pin DIP.

Z80 CPU Central Processing Unit

Machine cycle one

Z80 CPU Central Processing

40-pin DIP and 44-pin QFJ

All ac parameters assume a load capacitance of

(Vcc=5V5%, Ta=O to +7ocNote

Input leakage current

Standard Test Conditions

Ta=O to +60C for 44-pin QFP

(f= I MHz, Ta=25C)

Z80 CPU Central Processing

(Vcc=5V5%, Ta=O to +70t:Note

! Rising edge, !Falling edge

Z80 CPU Central Processing Unit

All ac parameters assume a load capacitance of 100 pF. Add 10

using the following expressions.

Z80 CPU Central Processing Unit

The CPU places the contents of the Program

Memory Read or Write Cycles

Fig. 2 shows the timing of memoryread or write

Input or Output Cycles

Fig. 3 shows the timing for an 110 read or l/O

ZBO CPU Central Processing Unit

=17_@__ _., '--------~1...____

Memory read or write cycles

Z80 CPU Central Processing Unit

Interrupt request/acknowledge cycle

The CPU samples the interrupt signal with the

Note 1 : TL= Last state of previous instruction.

Two wait cycles automatically inserted by CPU ( *).

Interrupt request/acknowledge cycle

ZBO CPU Central Processing Unit

Non-maskable interrupt request cycle

NM! is sampled at the same time as the maskable

ma! instruction fetch except that data put on the

"Although NM! is an asynchronous input. to guarantee its being

Non-maskable interrupt request operation

Bus request/acknowledge cycle

The CPU samples BUSREQ with the rising edge

ZBO CPU Central Processing Unit

Z-bus request/acknowledge cycle

HALT instruction received

Note: INT will also force a Halt exit.

Halt acknowledge cycle

Z80 CPU Central Processing

Timing diagram when M1 cycle has no wait state

Z80 CPU Central Processing

The RAM contents may be adversely affected by

A walt state in the M 1 cycle

Reset circuit and timing diagram when

Z80 CPU Central Processing Unit

F' Flag Register

( i) Program Counter (PC)