Lec 29-32 :

FET Applications
FET biasing methods and modeling.
Small-signal analysis.

Prepared by SHLim 05/14

Introduction
The general relationships that can be applied to the dc
analysis of all FET amplifiers.

and

For JFETs and D-MOSFETs, Shockleys equation is

given as
VGS 2
I D = I DSS ( 1
)
VP

For E-MOSFETs, the following equation is applicable:

Fixed-Bias Configuration
The resistor RG is present to ensure that Vi appears at the
input to the FET amplifier for the ac analysis.

Fixed-Bias Configuration

For the dc analysis,

Applying KVL,

ID is now controlled by Shockleys

equation

Fixed-Bias Configuration
ID could be found using graphical method. the fixed level of VGS has
been superimposed as a vertical line at VGS =- VGG.
At any point on the vertical line, the level of VGS is VGG.
The ID must simply be determined on this vertical line.

The point where the two curves

Intersect referred to as the
quiescent or operating point.

Note:
Find the intermediate
plot points

Fixed-Bias Configuration
The drain-to-source voltage of the output,
Applying KVL,

given

Self-Bias Configuration
self-bias configuration eliminates the need for two dc supplies.
The controlling gate-to-source voltage is now determined by
the voltage across a resistor RS.

Self-Bias Configuration

Applying KVL,

-------- eq1

Self-Bias Configuration
Substitute eq1into Shockleys equation

The quadratic equation form,

apply

Self-Bias Configuration
choose a level of ID equal to one-half the saturation level
for second point for the straight-line plot

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Self-Bias Configuration

The level of VDS can be determined by applying KVL

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Example

(g) compare Q-point mathematic with mathematic

approach

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Solution

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Voltage Divider Bias Configuration

VGS provided the link between input and output circuits.

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Voltage Divider Bias Configuration

The voltage VG, equal to the voltage across R2,

Applying KVL,

dc analysis.

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Voltage Divider Bias Configuration

Substitute VGS,=0V,

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Voltage Divider Bias Configuration

Increasing values of RS result in lower quiescent values of

ID and more negative values of VGS.

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Voltage Divider Bias Configuration

Once the quiescent values of IDQ and VGSQ are

determined, the remaining network analysis can be
performed in the usual manner.

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Example

(f) compare Q-point mathematic with mathematic approach

Solution

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Common Gate Configuration

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Common Gate Configuration

Applying KVL,

dc analysis.

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Common Gate Configuration

as I D = 0 mA;

VGS = VSS |I

=0 mA

and

as VGS = 0V ;

VSS
ID =
|V
RS

GS

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=0 V

Common Gate Configuration

Applying KVL across both source,

With

VD = VDD I D RD

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Solution

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Special Case VGS Q= 0V

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Special Case VGS Q= 0V

Since the transfer curve will cross the vertical axis at IDSS
the drain current for the network is set at the level of

Applying KVL,

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D-MOSFET Configuration

The similarities in appearance between the transfer

curves of JFETs and depletion type MOSFETs permit
a similar analysis of each in the dc domain.
The primary difference between the two is the fact
that depletion-type MOSFETs permit operating
points with positive values of VGS and levels of ID that
exceed IDSS.
Main concern point on plotting Shockleys equation
for positive values of VGS with the effect on ID and IDSS.

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Example

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Solution

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Example

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Solution

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E-MOSFET Configuration

For the n-channel enhancement-type MOSFET, the drain

current is zero for levels of gate-to-source voltage less
than the threshold level VGS(Th).

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E-MOSFET Configuration

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Feedback Biasing Configuration

The resistor RG brings a suitably large voltage to the gate

to drive the MOSFET on.

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Feedback Biasing Configuration

Since IG = 0 mA and VRG = 0 V, the dc equivalent network

appears as shown.

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Feedback Biasing Configuration

Transfer curve

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Example

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Solution

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Voltage-Divider Bias Configuration

VGG as derived from voltage-divider rule:

Applying KVL for VGS,

Applying KVL for VDS,

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Example
Next, compare Q-point mathematic with mathematic
approach

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Solution

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JFET Small-Signal Model

VGS controls the ID of a FET through transconductance

factor, gm :

Definition of gm
using transfer characteristic.
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JFET Small-Signal Model

An alternative approach to determining gm :

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JFET Small-Signal Model

Slope of the transfer curve is a maximum at VGS=0 V, thus

Equation then becomes

f : forward transfer parameter

s : source terminal.
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JFET Small-Signal Model

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JFET Small-Signal Model

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JFET Small-Signal Model

JFET Input impedance, Zi

The Zi all commercially available FETs is sufficiently large
to assume that the input terminals approximate an open
circuit.

JFET : practical value of ~ 10 9

MOSFET : practical value of 1012 ~ 1015

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JFET Small-Signal Model

JFET Output impedance, Zo

Zo will typically appear as yos with the units of S (~10 to 50 S).

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JFET AC Equivalent Circuit

The control of Id by Vgs is included as a current source

gmVgs connected from drain to source

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JFET Fixed Bias Configuration

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JFET Fixed Bias Configuration

Input impedance, Zi

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JFET Fixed Bias Configuration

Output impedance, Zo

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JFET Fixed Bias Configuration

Voltage gain, Av

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Example

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JFET Self Bias Configuration

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JFET Self Bias Configuration

Input impedance, Zi

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JFET Self Bias Configuration

Output impedance, Zo

Voltage gain, Av

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JFET Self Bias Configuration

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JFET Self Bias Configuration

Output impedance, Zo

Apply KCL,

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JFET Self Bias Configuration

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JFET Self Bias Configuration

Voltage gain, Av
Apply KVL,

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JFET Voltage Divider Bias Configuration

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JFET Voltage Divider Bias Configuration

Input impedance, Zi

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JFET Voltage Divider Bias Configuration

Output impedance, Zo

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JFET Voltage Divider Bias Configuration

Voltage gain, Av

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JFET-Source Follower (Common Drain)

Configuration

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JFET-Source Follower (Common Drain)

Configuration

Input impedance, Zi

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JFET-Source Follower (Common Drain)

Configuration

Output impedance, Zo
Apply KCL,

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JFET-Source Follower (Common Drain)

Configuration

Voltage gain, Av
Apply KVL,

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Example

Fig 9.44
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JFET Common Gate Configuration

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JFET Common Gate Configuration

Input impedance, Zi

Apply KVL,

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Apply KCL,

JFET Common Gate Configuration

Output impedance, Zo

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JFET Common Gate Configuration

Voltage gain, Av
Apply KCL,

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Example
Calculate Vo

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D-MOSFET

The only difference offered by D-MOSFETs is that VGSQ

can be positive for n-channel devices and negative for pchannel units.
The result is that gm can be greater than gm0 as
demonstrated by the example to follow. The range of rd is
very similar to that encountered for JFETs.

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E-MOSFET

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E-MOSFET

For E-MOSFETs, the relationship between output current

and controlling voltage is defined by

and

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Drain Feedback Configuration

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Drain Feedback Configuration

Input impedance, Zi

Apply KCL at node D

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Drain Feedback Configuration

Output impedance, Zo

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E-MOSFET Drain Feedback Configuration

Voltage gain, Av

AV = g m ( RF || rd || RD )

AV = g m RD
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RF >> rd ||RD ;rd 10 RD

Example

Voltage Divider Configuration

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Voltage Divider Configuration

Input impedance, Zi

Output impedance, Zo

Voltage gain, Av

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