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ECEN 651
MICROPROGRAMMED CONTROL OF DIGITAL SYSTEMS
FINAL PROJECT
IMPLEMENTATION OF A 32 BIT PIPELINED MIPS CPU
PROJECT REPORT
SUBMITTED BY
SWAPNIL S. LOTLIKAR
UIN: 218009104
DATE: 26th NOVEMBER 2008
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TABLE OF CONTENTS
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1. PROBLEM STATEMENT
The goal of the project is to design and implement a subset of a 32-bit pipelined MIPS
processor using verilog hardware description language. The design has to be tested using a set
of assembly language instructions. Finally the MIPS Processor will be synthesized using the
Synopsys Design Compiler.
2. DESIGN SPECIFICATIONS
In this project we implement a 32-bit MIPS processor using the standard 5-stage pipeline. The
basic block diagram for the processor is given in the figure below:
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3. MODULE SPECIFICATIONS
This section describes each of the individual modules in a little more detail, listing the functions
performed by each module, block diagram and the pin interface of each module. The modules
are listed below:
3.1. INST_FETCH
3.1.1.
BLOCK DIAGRAM
IF/ID
JMP OFFSET
CALCULATION
ADDER
BRANCH OFF
JR INST OFF
MUX
JUMP OFF
PC REG
INSTRUCTION
MEMORY
PC+4
PC_SOURCE
3.1.2.
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FUNCTIONS
Implements the mux to select the new value to be loaded in the PC Register (The
new value can be either PC+4, Jump Offset, Jump register offset or Branch offset)
Reads the Instruction memory and stores the result in the Instruction Register (IR)
Implements the adder to generate PC+4
Implements the left shifter to generate the jump offset.
Implements the PC register in the IF/ID stage
3.1.3.
PIN INTERFACE
PIN NAME
clk
resetn
Jr_inst
Jr_offset
Br_cond
Branch_offset
Data_out_31_26
Data_out_25_21
Data_out_20_16
Data_out_15_0
If_id_pc_reg
Inst_opcode
Inst_funct
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TYPE WIDTH
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
1
1
32
1
32
6
5
5
16
32
6
6
DESCRIPTION
Clock signal to the module
Active low reset signal
Jump register instruction indication
Jump register instruction offset
Branch condition indication
Branch instruction offset
Opcode field of instruction
rs field of instruction
rt field of instruction
rd/imm field of instruction
Pipeline register for PC
Instruction opcode field (not a registered output)
Instruction function field (not a registered output)
3.2. INST_DECODE
3.2.1.
BLOCK DIAGRAM
ID/EX
Jr_offset
Inst_read_reg_addr1
Inst_read_reg_addr2
reg_file_rd_data1
A
rt
Reg_wr_addr
REGISTER
FILE
rd
reg_file_rd_data2
B
5d31
Reg_wr_data
Reg_dst
Alu_data_out
mdr_data_out
SIGN EXT
Mem_to_reg
LEFT
SHIFT
Inst_imm_field
3.2.2.
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FUNCTIONS
Implements the write address select mux (selects either rt ,rd fields or 30(overflow
bit register) or 31(JAL instruction return address) as write back address to the
register file during register write back stage)
Implements the write data select mux (selects either the alu data out or memory data
out or overflow indication as the write back data for the register file during write back
stage)
Generates the sign extended immediate and sign extended left shifted immediate
registers to be used in the instruction execute stage of the pipeline. These are used
for Load/Store and some I-Type Instructions
Generates the 32 bit immediate register without sign extension by concatenating
zeros to the 16 bit immediate field from the instruction. This is used for I-Type
instructions
3.2.3.
Reads the register file with rs and rt as read addresses on its two read ports and
stores the read data in the reg_A and reg_B registers respectively for use by the
ALU in instruction execution stage.
Implements the ID/EX pipeline registers for Program Counter(PC), Instruction
Function field, Instruction Opcode and rt (To be passed on till the write back stage)
Generates the Jump Register instruction indication by sampling the opcode and
function bits of the instruction
Generates the jump register offset by using the contents read from register rs of the
register file
PIN INTERFACE
PIN NAME
Clk
Resetn
Inst_read_reg_addr_1
Inst_read_reg_addr_2
Inst_wr_addr_1
Inst_wr_addr_2
Mdr_data_out
Alu_data_out
Reg_file_wr_en
Reg_dst
Mem_to_reg
Inst_imm_field
If_id_pc_reg
If_id_inst_31_26
Mem_wb_overflow
Reg_A
Reg_B
Imm_fld_wo_sign_ext
Sign_ext_imm
Sign_ext_ls_imm
Id_ex_pc_reg
Id_ex_inst_5_0
Id_ex_inst_31_26
Id_ex_inst_20_16
Jr_inst
Jr_offset
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TYPE WIDTH
IN
IN
1
1
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
5
5
32
32
1
2
1
16
32
6
1
32
32
32
32
32
32
6
6
5
1
32
DESCRIPTION
Clock signal to the module
Active low reset signal
rs field of the instruction connected to read port 1
of register file
rt field of the instruction connected to read port 2
of register file
Rt field of the instruction
Rd field of the instruction
Read data from memory
Alu result to be written to the memory
Write enable to the register file
Select line to the write address select mux
Select line to the write data select mux
Immediate field of the instruction
IF/ID Pipeline register for PC
IF/ID Pipeline register for instruction opcode
Overflow indication pipeline register
Data fetched from register rs
Data fetched from register rt
Original immediate field without sign extension
Immediate field with sign extension
Immediate field with sign extension and left shift
ID/EX pipeline register for PC
ID/EX pipeline register for instruction funct bits
ID/EX pipeline register for instruction opcode bits
ID/EX pipeline register for instruction rt field
JR instruction indication
Jump offset for JR instruction
BLOCK DIAGRAM
clk
resetn
Reg_rd_data1
Reg_rd_addr1
REG
Reg_rd_addr2
FILE
Reg_wr_en
Reg_rd_data1
Reg_wr_addr
Reg_wr_data
3.3.2.
3.3.3.
FUNCTIONS
Implements the 32 Word deep General Purpose register bank.
Implements two read ports and one write port to the register bank
Initializes all GPRs to 0 under reset
PIN INTERFACE
PIN NAME
Clk
Resetn
Reg_rd_addr_1
Reg_rd_addr_2
Reg_wr_en
Reg_wr_addr
Reg_wr_data
Reg_rd_data1
Reg_rd_data2
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TYPE WIDTH
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
1
1
5
5
1
5
32
32
32
DESCRIPTION
Clock signal to the module
Active low reset signal
Read address to port 1 of the register file
Read address to port2 of the register file
Write enable to the register file
Write address to the register file
Write data to the register file
Read data from port 1
Read data from port 2
BLOCK DIAGRAM
PC
Branch_offset
Sign_ext_ls_imm
Br_cond
opcode
Reg_A_data
Alu_res
ALU
Reg_B_data
overflow
Sign_ext_imm
Imm_fld_wo_sign_ext
Alu_cntl_ip
funct
opcode
ALU
CONTROLLER
EX/MEM
Alu_op
3.4.2.
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FUNCTIONS
Implements the ALU input A select mux
Implements the ALU input B select mux
Instantiates the ALU and the ALU Controller modules
Generates branch condition indicator for branch instructions
Generates branch offset for the branch instructions using sign extended left shifted
immediate generated in the Instruction Decode stage. This along with branch
indication is used by the pc select mux in the instruction fetch module
Generates the overflow indication for signed addition and subtraction instructions
Implements alu_out register to store the alu output
Implements the EX/MEM Pipeline registers
3.4.3.
PIN INTERFACE
PIN NAME
Clk
Resetn
Pc_reg
Reg_A_data
Reg_B_data
Sign_ext_imm
Sign_ext_ls_imm
Imm_field_wo_sign_ext
Inst_reg_5_0
Inst_opcode
Alu_src_A
Alu_src_B
Alu_op
TYPE WIDTH
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
1
32
32
32
32
32
32
6
6
1
3
2
Id_ex_inst_20_16
Alu_out
Ex_mem_reg_B_data
Ex_mem_inst_5_0
Ex_mem_inst_31_26
Ex_mem_inst_20_16
Ex_mem_inst_15_11
IN
OUT
OUT
OUT
OUT
OUT
OUT
5
32
32
6
6
5
Ex_mem_overflow
Br_cond
Branch_offset
OUT
OUT
OUT
1
1
32
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DESCRIPTION
Clock signal to the module
Active low reset signal
ID/EX pipeline register for PC
Read data from Register A
Read data from Register B
Sign extended immediate number
Immediate field with sign extension and left shift
Original immediate field without sign extension
ID/EX pipeline register for instruction funct bits
ID/EX pipeline register for instruction opcode
Select line for the ALU Input A select Mux
Select line for the ALU Input B select Mux
Select line used to select the type of ALU
operation required. This is given as an input to the
alu controller.
ID/EX pipeline register for rt field of instruction
Alu output register
EX/MEM pipeline register for the register B data
EX/MEM pipeline register for instruction funct bits
EX/MEM pipeline register for instruction opcode
EX/MEM pipeline register for rt field of instruction
EX/MEM pipeline register for rd field of
instruction
EX/MEM pipeline register for overflow indication
Branch condition indicator
Branch offset for the branch instruction
BLOCK DIAGRAM
funct
ALU
CONTROLLER
opcode
Alu_cntl_ip
Alu_op
3.5.2.
3.5.3.
FUNCTIONS
Generates the control inputs to the ALU based on the instruction opcode, instruction
function bits and the alu_op field
PIN INTERFACE
PIN NAME
Inst_reg_5_0
Alu_op
Inst_opcode
Alu_cntl_ip
TYPE WIDTH
IN
IN
IN
OUT
6
2
6
4
DESCRIPTION
Instruction function field
Type of alu operation required
Instruction opcode field
Control lines to the ALU
The relationship between function field, alu_op, instruction opcode and alu_cntl_ip is
shown in the table below:
ALU_OP FUNCT OPCODE
ALU_CNTL_IP
0
X
X
4h2 Signed addition
1
6h04
6h06
6h20
6h21
6h22
6h23
6h24
6h25
6h26
6h27
6h2A
6h2B
X
X
X
X
X
X
X
X
X
X
X
X
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DESCRIPTION
Used for Load/Store
class of Instructions
Used
for
Branch
Instructions
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DESCRIPTION
Used for I-Type
Instructions(Alu
operation decided by the
opcode field of the
instruction)
3.6. ALU
3.6.1.
BLOCK DIAGRAM
Zero, not_equal,
ls_then,
gr_then,
ls_then_eq
ALU
Alu_out
overflow
B
Alu_cntl_ip
3.6.2.
3.6.3.
FUNCTIONS
Implements all the Arithmetic, Logical and Shift operations
Detects overflow for signed addition and subtraction operations
Generates conditions required for detecting branches like zero, not_equal_to,
less_then, greater_then and less_then_equal
PIN INTERFACE
PIN NAME
TYPE WIDTH
A
B
Alu_cntl_ip
Alu_res
Zero
Not_equal
Ls_then
Gr_then
Ls_then_eq
overflow
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
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32
32
4
32
1
1
1
1
1
1
DESCRIPTION
Operand A input to the ALU
Operand B input to the ALU
ALU control input from the ALU Controller
Result of the ALU Operation
Indicator for reg_A == reg_B
Indicator for reg_A != reg_B
Indicator for reg_A < reg_B
Indicator for reg_A > reg_B
Indicator for reg_A <= reg_B
Overflow Indicator for signed addition/subtraction
3.7. MEMORY_ACC
3.7.1.
BLOCK DIAGRAM
Mem_addr
Data_out
Mem_rd
DATA MEMORY
D
R
Mem_wr
Data_in
Alu_out
overflow
MEM/WB
3.7.2.
3.7.3.
FUNCTIONS
Performs read to the Data memory for Load Instructions
Performs write to the Data memory for Store Instructions
Implements the MEM/WB pipeline registers for alu_out, rt/rd instruction fields and
overflow
Implements the memory data register which stores the read data from data memory
PIN INTERFACE
PIN NAME
Clk
resetn
Alu_out
Mem_rd
Mem_wr
Mem_wr_data
Ex_mem_inst_20_16
Ex_mem_inst_15_11
Ex_mem_overflow
Mdr_data_out
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TYPE WIDTH
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
1
1
32
1
1
32
5
5
1
32
DESCRIPTION
Clock signal to the module
Active low reset signal
Effective memory address from ALU
Read signal to the data memory
Write signal to the data memory
Write data to the data memory
EX/MEM pipeline register for rt instruction field
EX/MEM pipeline register for rd instruction field
EX/MEM pipeline register for overflow indication
Memory data output register
PIN NAME
Mem_wb_alu_out_reg
Mem_wb_inst_20_16
Mem_wb_inst_15_11
Mem_wb_overflow
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TYPE WIDTH
OUT
OUT
OUT
OUT
32
5
5
1
DESCRIPTION
MEM/WB pipeline register for alu_out
MEM/WB pipeline register for rt instruction field
MEM/WB pipeline register for rd instruction field
MEM/WB pipeline register for overflow indication
3.8. MEMORY
3.8.1.
BLOCK DIAGRAM
clk
resetn
Data_out
Mem_addr
DATA MEMORY
Mem_rd
Mem_wr
Data_in
3.8.2.
3.8.3.
FUNCTIONS
This is a generic module and is instantiated for both instruction as well as data
memories
Implements a memory array
PIN INTERFACE
PIN NAME
TYPE WIDTH
Clk
resetn
Mem_addr
Mem_rd
Mem_wr
Data_in
Data_out
IN
IN
IN
IN
IN
IN
OUT
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1
1
32
1
1
32
32
DESCRIPTION
Clock signal to the module
Active low reset signal
Read address to the memory
Read signal to the memory
Write signal to the memory
Write data to the memory
Read data from memory
3.9. CNTL_PATH
3.9.1.
BLOCK DIAGRAM
Id_ex_alu_src_A
clk
Id_ex_alu_src_B
Id_ex_alu_op
resetn
Ex_mem_data_mem_rd
CONTROLLER
Inst_opcode
Ex_mem_data_mem_wr
Mem_wb_reg_file_wr_en
Mem_wb_reg_dst
Inst_funct
Mem_wb_mem_to_reg
3.9.2.
3.9.3.
FUNCTIONS
Generate the control signals to the various modules in the data path based on the
instruction opcode and the instruction function field
Implements the pipeline registers in the control path for the control signals
PIN INTERFACE
PIN NAME
TYPE WIDTH
Clk
resetn
Inst_opcode
Inst_funct
Id_ex_alu_src_A
IN
IN
IN
IN
OUT
Id_ex_alu_src_B
OUT
Id_ex_alu_op
OUT
1
1
6
6
1
3
2
Ex_mem_data_mem_rd
OUT
Ex_mem_data_mem_wr
OUT
Mem_wb_reg_file_wr_en
OUT
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1
1
1
DESCRIPTION
Clock signal to the module
Active low reset signal
Instruction opcode field
Instruction Function field
Select line for the ALU Input A select Mux
required in instruction execute stage
Select line for the ALU Input B select Mux
required in the instruction execute stage
Select line used to select the type of ALU
operation required. This control signal is required
in the instruction execution stage
Read signal to the data memory. This control
signal is required in the memory access stage
write signal to the data memory. This control
signal is required in the memory access stage
Register file write enable. This control signal is
required in the register writeback stage
PIN NAME
TYPE WIDTH
Mem_wb_reg_dst
OUT
OUT
Mem_wb_mem_to_reg
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DESCRIPTION
Select line to the write address select mux. This
control signal is required in the register writeback
stage
Select line to the write data select mux. This
control signal is required in the register writeback
stage.
4. RTL CODE
This section gives the RTL Code for each of the modules used in the design of the 32-bit
pipelined MIPS Processor
4.1. INST_FETCH.V
//-------------------------------------------------------------------//VERILOG CODE FOR INSTRUCTION FETCH CYCLE
//MODULE : inst_fetch,memory
//FILE NAME : inst_fetch.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 11 November 2008
//CODE TYPE : Behavioural
//DESCRIPTION : This Module fetches the Instruction from Instruction
//
memory using PC as address and stores the fetched inst
//
in the Instruction register. In addition it also
//
implements the PC Select MUX
//-------------------------------------------------------------------module inst_fetch (
clk
,
resetn
,
jr_inst
,
jr_offset ,
br_cond
,
branch_offset ,
data_out_31_26 ,
data_out_25_21 ,
data_out_20_16 ,
data_out_15_0 ,
if_id_pc_reg ,
inst_opcode ,
inst_funct
);
//Inputs
input
clk
; //Clk signal
input
resetn
; //active low reset signal
input
jr_inst ; //indication of jr instruction
input [31:0] jr_offset ; //jump offset for jr instruction
input
br_cond ; //branch condition indicator
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25 | P a g e
4.2. INST_DECODE.V
//-------------------------------------------------------------------//VERILOG CODE FOR A INSTRUCTION DECODE MODULE
//MODULE : inst_decode,reg_file
//FILE NAME : inst_decode.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module decodes the instruction and reads the reg
//
file to fetch the operands. This modules also generates
//
the jr instruction offset required in the instruction
//
fetch module. Sign extended imm are also generated in
//
this module. During the register write back stage this
//
module performs a writeback to the register file
//-------------------------------------------------------------------//Define module
module inst_decode (
clk
resetn
,
,
inst_read_reg_addr1 ,
inst_read_reg_addr2 ,
inst_wr_addr_1 ,
inst_wr_addr_2 ,
mdr_data_out
,
alu_data_out
,
reg_file_wr_en ,
reg_dst
,
mem_to_reg
,
inst_imm_field ,
if_id_pc_reg
,
if_id_inst_31_26 ,
mem_wb_overflow
reg_A
,
reg_B
,
imm_fld_wo_sign_ext ,
sign_ext_imm
,
sign_ext_ls_imm ,
id_ex_pc_reg
,
id_ex_inst_5_0 ,
id_ex_inst_31_26 ,
id_ex_inst_20_16 ,
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);
//Inputs
input clk
input resetn
; //Clock signal
; //active low reset signal
jr_inst
//Internal signals
reg [4:0] wr_addr_sel_mux_c ;
reg [4:0] wr_addr_sel_mux2_c ;
wire [31:0] wr_data_sel_mux_c ;
reg [31:0] wr_data_sel_mux2_c ;
wire [31:0] sign_ext_imm_c
;
wire [31:0] reg_file_rd_data1_c ;
wire [31:0] reg_file_rd_data2_c ;
wire
jr_inst_c
;
//Select the write address to the register file
//if reg_dst = 1 then wr_addr_sel_mux = inst_wr_addr_2
//else if reg_dst = 0 then wr_addr_sel_mux = inst_wr_addr_1
//else if reg_dst = 2 then wr_addr_sel_mux = 5'd31-for selecting r31 during jal
always @(inst_wr_addr_1 or inst_wr_addr_2 or reg_dst)
begin
case (reg_dst)
2'd0 : wr_addr_sel_mux_c <= inst_wr_addr_1 ;
2'd1 : wr_addr_sel_mux_c <= inst_wr_addr_2 ;
2'd2 : wr_addr_sel_mux_c <= 5'd31
;
default : wr_addr_sel_mux_c <= 0
;
endcase
end
//generate the wr_addr_sel_mux2_c which muxes between the above selected
//wr address and the overflow register write address(i.e. r30)
always @(mem_wb_overflow or wr_addr_sel_mux_c)
begin
if(mem_wb_overflow == 1'b1)
wr_addr_sel_mux2_c <= 5'd30;
else
wr_addr_sel_mux2_c <= wr_addr_sel_mux_c;
end
//Select the write data to the register file
//if mem_to_reg = 1 then wr_data_sel_mux_c = data from memory data reg
//
else wr_data_sel_mux_c = data from alu output reg
assign wr_data_sel_mux_c = mem_to_reg ? alu_data_out : mdr_data_out ;
//generate the wr_data_sel_mux2_c which muxes between the above selected
//wr data and the overflow indication to the register file
always @(mem_wb_overflow or wr_data_sel_mux_c)
begin
if(mem_wb_overflow == 1'b1)
wr_data_sel_mux2_c <= 32'b1;
else
28 | P a g e
29 | P a g e
30 | P a g e
4.3. REG_FILE.V
//-------------------------------------------------------------------//VERILOG CODE FOR A REGISTER FILE
//MODULE : reg_file
//FILE NAME : reg_file.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module implements the 32 General Purpose Registers
//
for the 32-bit pipelined MIPS processor. Each Register
//
is 32 Bits wide. This register bank has two read ports
//
and a single write port
//-------------------------------------------------------------------//Define module
module reg_file (
clk
,
resetn
,
reg_rd_addr1 ,
reg_rd_addr2 ,
reg_wr_en ,
reg_wr_addr ,
reg_wr_data ,
reg_rd_data1 ,
reg_rd_data2
);
//Inputs
input clk;
input resetn;
input [4:0] reg_rd_addr1 ; //Register file read address 1
input [4:0] reg_rd_addr2 ; //Register file read address 2
input reg_wr_en
; //Write enable to the register file
input [4:0] reg_wr_addr ; //Register file write address
input [31:0] reg_wr_data ; //Register file write data
//Outputs
output [31:0] reg_rd_data1; //Register file read data
output [31:0] reg_rd_data2; //Register file read data
//Define register array
reg [31:0] register_file[0:31];
//Internal signals
integer i;
//Write Process for Register file
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32 | P a g e
4.4. INST_EXECUTE.V
,
,
,
,
,
id_ex_inst_20_16 ,
alu_out
,
ex_mem_reg_B_data ,
ex_mem_inst_5_0 ,
ex_mem_inst_31_26 ,
ex_mem_inst_20_16 ,
ex_mem_inst_15_11 ,
ex_mem_overflow ,
br_cond
,
branch_offset
);
33 | P a g e
//Inputs
input clk
; //clock signal
input resetn
; //active low reset signal
input [31:0] pc_reg
; //Value from Program Counter Register
input [31:0] reg_A_data
; //Register A data from inst decode
input [31:0] reg_B_data
; //Register B data from inst decode
input [31:0] sign_ext_imm
; //Sign ext immediate number from instruction
input [31:0] sign_ext_ls_imm ; //Sign ext left shifted imm number
input [31:0] imm_fld_wo_sign_ext ; //Non sign extended immediate field
input [5:0] inst_reg_5_0
; //function field from instruction
input [5:0] inst_opcode
; //Opcode field in the instruction
input
alu_src_A
; //select line for src A of ALU
input [2:0] alu_src_B
; //select line for src B of ALU
input [1:0] alu_op
; //Type of ALU Op required from Main controller
input [4:0] id_ex_inst_20_16 ; //Pipeline register for rt field of instruction
//Outputs
output [31:0] alu_out
; //Registered ALU result
output [31:0] ex_mem_reg_B_data ; //pipeline register for reg_B data
output [5:0] ex_mem_inst_5_0 ; //pipeline register for inst funct field
output [5:0] ex_mem_inst_31_26 ; //pipeline register for the inst opcode field
output [4:0] ex_mem_inst_20_16 ; //Pipeline register for rt field of instruction
output [4:0] ex_mem_inst_15_11 ; //pipeline register for rd field of instruction
output
ex_mem_overflow ; //Overflow detected indication
output
br_cond
; //indicator for branch instruction
output [31:0] branch_offset ; //offset for branch instruction
reg
reg
reg
reg
reg
reg
reg
[31:0] alu_out
;
[31:0] ex_mem_reg_B_data ;
[5:0] ex_mem_inst_5_0 ;
[5:0] ex_mem_inst_31_26 ;
[4:0] ex_mem_inst_20_16 ;
[4:0] ex_mem_inst_15_11 ;
ex_mem_overflow ;
wire
br_cond
;
wire [31:0] branch_offset
//Internal Signals
wire [31:0] alu_src_A_mux_c ; //Muxed value for input A of ALU
reg [31:0] alu_src_B_mux_c ; //Muxed value for input B of ALU
wire [3:0] alu_cntl_ip_c ; //Control input for the ALU
wire [31:0] alu_res_c
; //Result from ALU operation
wire
zero_c
; //branch condition for beq
wire
not_equal_c ; //branch condition for bne
wire
ls_then_c
; //branch condition for bltz
34 | P a g e
gr_then_c
; //branch condition for bgtz
ls_then_eq_c ; //branch condition for blez
br_cond_c
; //cumulative branch condition
overflow_c ; //Overflow detected indication
36 | P a g e
37 | P a g e
4.5. ALU_CONTROLLER.V
//-------------------------------------------------------------------//VERILOG CODE FOR AN ALU CONTROLLER
//MODULE : alu_controller
//FILE NAME : alu_controller.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module generates the alu control inputs based on
//
instruction opcode, instruction function bits and the
//
alu operation field provided by the main controller
//-------------------------------------------------------------------//Define the module
module alu_controller (
inst_reg_5_0,
alu_op ,
inst_opcode ,
alu_cntl_ip
);
//Inputs
input [5:0] inst_reg_5_0 ; //Bits 5 to 0 from inst reg
input [1:0] alu_op
; //type of Alu op fm main controller
input [5:0] inst_opcode ; //Opcode field from the instruction
//Outputs
output [3:0] alu_cntl_ip ; //Control lines to the ALU
reg [3:0] alu_cntl_ip ;
//Generate the alu control input lines
//based on funct field and alu_op
always @(alu_op or inst_reg_5_0 or inst_opcode)
begin
case (alu_op)
2'b00 : alu_cntl_ip <= `ALU_ADD; //Perform Add for LW/SW operations
2'b01 : alu_cntl_ip <= `ALU_SUB; //Perform Sub for branch operatios
2'b10 :
begin
//alu ops implemented based on funct field of inst
case (inst_reg_5_0)
`FUNC_SLLV : alu_cntl_ip <= `ALU_SLLV ;
`FUNC_SRLV : alu_cntl_ip <= `ALU_SRLV ;
`FUNC_ADD : alu_cntl_ip <= `ALU_ADD ;
`FUNC_ADDU : alu_cntl_ip <= `ALU_ADDU ;
`FUNC_SUB : alu_cntl_ip <= `ALU_SUB ;
`FUNC_SUBU : alu_cntl_ip <= `ALU_SUBU ;
38 | P a g e
39 | P a g e
4.6. ALU.V
//-------------------------------------------------------------------//VERILOG CODE FOR AN ALU
//MODULE : alu
//FILE NAME : alu.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Behavioral
//DESCRIPTION : This module performs the arithmetic, logical and shift
//
operations. In addition it generates the overflow indi
//
for signed add and sub operations. It also generates
//
branch indicators like zero, not_equal, ls_then etc.
//-------------------------------------------------------------------//Define the module
module alu (
a
,
b
,
alu_cntl_ip,
alu_res ,
zero
,
not_equal ,
ls_then ,
gr_then ,
ls_then_eq ,
overflow
);
//Inputs
input [31:0] a
; //Input A to the ALU
input [31:0] b
; //Input B to the ALU
input [3:0] alu_cntl_ip ; //ALU control i/p used to sel operation
//Outputs
output [31:0] alu_res ; //Result of ALU Operation
output
zero ; //branch condition result
output
not_equal ; //set when rs!=rt, used in bne inst
output
ls_then ; //set when rs<0, used in bltz inst
output
gr_then ; //set when rs>0, used in bgtz inst
output
ls_then_eq; //set when rs<=0, used in blez inst
output
overflow ; //overflow detected indication
//Internal Signals
reg signed [31:0] alu_res_c ; //signed alu result
reg signed [31:0] signed_a ; //signed b input
reg signed [31:0] signed_b ; //Signed a input
40 | P a g e
43 | P a g e
4.7. MEMORY_ACC.V
//-------------------------------------------------------------------//VERILOG CODE FOR MEMORY ACCESS MODULE
//MODULE : memory
//FILE NAME : memory.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 11 November 2008
//CODE TYPE : Behavioural
//DESCRIPTION : This module implements the accesses to the data mem
//
It does a data memory read for load operations and a
//
data memory write for store operations. It also imple
//
ments the memory data register to store the data read
//
from the data memory
//-------------------------------------------------------------------//Define the module
module memory_acc (
clk
,
resetn
,
alu_out
,
mem_rd
,
mem_wr
,
mem_wr_data
,
ex_mem_inst_20_16 ,
ex_mem_inst_15_11 ,
ex_mem_overflow ,
mdr_data_out ,
mem_wb_alu_out_reg,
mem_wb_inst_20_16 ,
mem_wb_inst_15_11 ,
mem_wb_overflow
);
//Inputs
input
clk
; //Clock signal
input
resetn
; //Active low reset signal
input [31:0] alu_out
; //effective Memory address for data memory
input
mem_rd
; //Memory read signal
input
mem_wr
; //Memory write signal
input [31:0] mem_wr_data ; //Memory write data
input [4:0] ex_mem_inst_20_16; //Pipeline register for rt instruction field
input [4:0] ex_mem_inst_15_11; //pipeline register for rd instruction field
44 | P a g e
//Outputs
output [31:0] mdr_data_out
; //Memory read data output register
output [31:0] mem_wb_alu_out_reg ; //pipeline register for alu_out register
output [4:0] mem_wb_inst_20_16 ; //Pipeline register for rt instruction field
output [4:0] mem_wb_inst_15_11 ; //pipeline register for rd instruction field
output
mem_wb_overflow ; //pipeline register for overflow indication
reg
reg
reg
reg
reg
[31:0] mdr_data_out_r ;
[31:0] mem_wb_alu_out_reg ;
[4:0] mem_wb_inst_20_16 ;
[4:0] mem_wb_inst_15_11 ;
mem_wb_overflow ;
//Internal signals
wire [31:0] data_out_r
46 | P a g e
4.8. MEMORY.V
//-------------------------------------------------------------------//VERILOG CODE FOR A MEMORY
//MODULE : memory
//FILE NAME : memory.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 11 November 2008
//CODE TYPE : Behavioural
//DESCRIPTION : This module implements a generic memory having one
//
read and one write port.It has a depth of MEM_DEPTH,
//
address width of MEM_ADDR_WIDTH and data width of
//
MEM_DATA_WIDTH
//-------------------------------------------------------------------module memory (
clk ,
resetn ,
mem_addr ,
mem_rd ,
mem_wr ,
data_in ,
data_out
);
//Inputs
input
clk ; //Clock Signal
input
resetn ; //active low reset signal
input [`MEM_ADDR_WIDTH-1:0] mem_addr ; //address to the memory
input
mem_rd ; //memory read signal
input
mem_wr ; //memory write signal
input [`MEM_DATA_WIDTH-1:0] data_in ; //write data to memory
//Outputs
output [`MEM_DATA_WIDTH-1:0] data_out ; //read data
//Memory Array
reg [`MEM_DATA_WIDTH-1:0] mem [0:`MEM_DEPTH-1];
always @(posedge clk)
begin
if(!resetn)
begin
end
else
47 | P a g e
48 | P a g e
4.9. DATA_PATH.V
//-------------------------------------------------------------------//VERILOG CODE FOR DATAPATH TOP
//MODULE : inst_fetch,inst_decode,inst_execute,memory_acc
//FILE NAME : data_path.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 12 November 2008
//CODE TYPE : Structural
//DESCRIPTION : This module instantiates all the modules from the data
//
path and performs the port mapping. This module will be
//
instantiated in the mips_top.v
//-------------------------------------------------------------------//Define module
module data_path (
//Clock and Reset Signals
clk,
resetn,
//Control signals to the inst decode module
reg_file_wr_en,
reg_dst
,
mem_to_reg ,
//Control signals to the inst execute module
alu_src_A,
alu_src_B,
alu_op ,
//Control signals to the memory_acc module
data_mem_rd,
data_mem_wr,
inst_opcode ,
inst_funct
);
//Inputs
input
clk
; //Clock signal
input
resetn
; //Active low reset signal
input
reg_file_wr_en ; //Register File write enable signal
input [1:0] reg_dst
; //used to select the destination register address
input
mem_to_reg ; //used to select the write data going to register
input
alu_src_A
; //select line for src A of ALU
input [2:0] alu_src_B
; //select line for src B of ALU
input [1:0] alu_op
; //Type of ALU Op required from Main controller
49 | P a g e
//Outputs
output [5:0] inst_opcode ; //Instruction opcode field from instruction
output [5:0] inst_funct ; //Function field of the instruction
//Internal Signals
wire [31:0] alu_out_c
;
wire [31:0] reg_B_c
;
wire [31:0] reg_A_c
;
wire [5:0] data_out_31_26_c ;
wire [4:0] data_out_25_21_c ;
wire [4:0] data_out_20_16_c ;
wire [15:0] data_out_15_0_c ;
wire [31:0] mdr_data_out_c
;
wire [31:0] sign_ext_imm_c
;
wire [31:0] sign_ext_ls_imm_c ;
wire [31:0] imm_fld_wo_sign_ext_c;
wire
jr_inst_c
;
wire [31:0] jr_offset_c
;
wire
br_cond_c
;
wire [31:0] branch_offset_c ;
wire [31:0] if_id_pc_reg_c
;
wire [31:0] id_ex_pc_reg_c
;
wire [5:0] id_ex_inst_5_0_c ;
wire [5:0] id_ex_inst_31_26_c ;
wire [31:0] ex_mem_reg_B_data_c ;
wire [31:0] mem_wb_alu_out_reg_c ;
wire [5:0] ex_mem_inst_5_0_c ;
wire [5:0] ex_mem_inst_31_26_c ;
wire [5:0] inst_opcode_c
;
wire [5:0] inst_funct_c
;
wire [4:0] id_ex_inst_20_16_c ;
wire [4:0] ex_mem_inst_20_16_c ;
wire [4:0] mem_wb_inst_20_16_c ;
wire [4:0] ex_mem_inst_15_11_c ;
wire [4:0] mem_wb_inst_15_11_c ;
wire
ex_mem_overflow_c ;
wire
mem_wb_overflow_c ;
//Instantiate the Instruction Fetch Module
inst_fetch inst_fetch_inst(
.clk
(clk)
,
.resetn
(resetn)
,
.jr_inst
(jr_inst_c)
,
.jr_offset (jr_offset_c) ,
50 | P a g e
,
,
//assign outputs
assign inst_opcode = inst_opcode_c;
assign inst_funct = inst_funct_c;//ex_mem_inst_5_0_c;
endmodule
52 | P a g e
4.10. CNTL_PATH.V
//-------------------------------------------------------------------//VERILOG CODE FOR CONTROL PATH
//MODULE : cntl_path
//FILE NAME : cntl_path.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : behavioral
//DESCRIPTION : This module generates the control signals required by
//
various modules in the data path based on the inst opc
//
and inst function bits
//-------------------------------------------------------------------//Define module
module cntl_path (
//Clock and Reset Signals
clk,
resetn,
//Control signals to the inst execute module
id_ex_alu_src_A ,
id_ex_alu_src_B ,
id_ex_alu_op
,
//Control signals to the memory_acc module
ex_mem_data_mem_rd ,
ex_mem_data_mem_wr ,
//control signals to the write back module
mem_wb_reg_file_wr_en,
mem_wb_reg_dst
,
mem_wb_mem_to_reg ,
//Outputs of data path
inst_opcode ,
inst_funct
);
//Inputs
input
clk
; //Clock signal
input
resetn ; //Active low reset signal
input [5:0] inst_opcode ; //Instruction opcode field from instruction
input [5:0] inst_funct ; //Function field in an R-Type instruction
//Outputs
output
id_ex_alu_src_A
53 | P a g e
;
;
;
;
//Internal Signals
reg
if_id_alu_src_A_c ;
reg [2:0] if_id_alu_src_B_c ;
reg [1:0] if_id_alu_op_c
;
reg
if_id_data_mem_rd_c ;
reg
if_id_data_mem_wr_c ;
reg
if_id_reg_file_wr_en_c ;
reg [1:0] if_id_reg_dst_c
;
reg
if_id_mem_to_reg_c ;
reg [13:0] cntl_signals_bus
id_ex_mem_to_reg_r
reg
ex_mem_reg_file_wr_en_r ;
reg [1:0] ex_mem_reg_dst_r
;
reg
ex_mem_mem_to_reg_r ;
//Generate the control signals based on the instruction opcode
always @(inst_opcode or inst_funct)
begin
case (inst_opcode)
`R_TYPE
: begin
if(inst_funct == `FUNC_JR)
begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b10 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
else if(inst_funct == `NOP)
begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
else
begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b10 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b01 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
end
`L_TYPE
55 | P a g e
: begin
if_id_alu_src_A_c
<= 1'b1 ;
: begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b1 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`J_TYPE
: begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
`J_TYPE_JAL : begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b10 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`B_TYPE_EQ : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b01 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
56 | P a g e
`I_TYPE_ADDI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_SLTI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_ADDIU : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b010 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_ANDI : begin
if_id_alu_src_A_c <= 1'b1 ;
if_id_alu_src_B_c <= 3'b100 ;
if_id_alu_op_c
<= 2'b11 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b1 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b1 ;
end
`I_TYPE_ORI : begin
if_id_alu_src_A_c
if_id_alu_src_B_c
58 | P a g e
<= 1'b1 ;
<= 3'b100 ;
: begin
if_id_alu_src_A_c <= 1'b0 ;
if_id_alu_src_B_c <= 3'b000 ;
if_id_alu_op_c
<= 2'b00 ;
if_id_data_mem_rd_c <= 1'b0 ;
if_id_data_mem_wr_c <= 1'b0 ;
if_id_reg_file_wr_en_c <= 1'b0 ;
if_id_reg_dst_c
<= 2'b00 ;
if_id_mem_to_reg_c <= 1'b0 ;
end
endcase
end
<= if_id_mem_to_reg_r
61 | P a g e
4.11. CONSTANTS.V
//-------------------------------------------------------------------//VERILOG CODE FOR CONTROL PATH
//MODULE : //FILE NAME : constants.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : //DESCRIPTION : This module defines all the constants used in the RTL
//-------------------------------------------------------------------//Constants
`define MEM_ADDR_WIDTH 32
`define MEM_DATA_WIDTH 32
`define MEM_DEPTH 64
//Instruction Function encoding
`define FUNC_SLLV 6'h04
`define FUNC_SRLV 6'h06
`define FUNC_ADD 6'h20
`define FUNC_ADDU 6'h21
`define FUNC_SUB 6'h22
`define FUNC_SUBU 6'h23
`define FUNC_AND 6'h24
`define FUNC_OR 6'h25
`define FUNC_XOR 6'h26
`define FUNC_NOR 6'h27
`define FUNC_SLT 6'h2A
`define FUNC_SLTU 6'h2B
`define FUNC_JR 6'h08
`define NOP
6'h00
//Alu control line constants
`define ALU_SLLV 4'h0
`define ALU_SRLV 4'h1
`define ALU_ADD 4'h2
`define ALU_ADDU 4'h3
`define ALU_SUB 4'h4
`define ALU_SUBU 4'h5
`define ALU_AND 4'h6
`define ALU_OR 4'h7
`define ALU_XOR 4'h8
`define ALU_NOR 4'h9
`define ALU_SLT 4'hA
`define ALU_SLTU 4'hB
`define ALU_ADD_ZERO 4'hC
62 | P a g e
63 | P a g e
4.12. MIPS_TOP.V
//-------------------------------------------------------------------//VERILOG CODE FOR MIPS TOP
//MODULE : data_path,cntl_path
//FILE NAME : mips_top.v
//DESIGNER : SWAPNIL S LOTLIKAR
//DATE
: 13 November 2008
//CODE TYPE : Structural
//DESCRIPTION : This module instantiates the data_path and the cntl_path
//
and performs the port mapping between then. This is the
//
top most module in the hierarchy
//-------------------------------------------------------------------//define the module
module mips_top (
clk,
resetn
);
//Inputs
input clk;
input resetn;
//Internal Signals
wire [1:0] pc_source_c
;
wire
mem_wb_reg_file_wr_en_c ;
wire [1:0] mem_wb_reg_dst_c
;
wire
mem_wb_mem_to_reg_c ;
wire
id_ex_alu_src_A_c
;
wire [2:0] id_ex_alu_src_B_c
;
wire [1:0] id_ex_alu_op_c
;
wire
ex_mem_data_mem_rd_c ;
wire
ex_mem_data_mem_wr_c ;
wire [5:0] inst_opcode_c
;
wire [5:0] inst_funct_c
;
wire
wire
pc_wr_cond_c
br_cond_true_c
;
;
65 | P a g e
#21
$readmemh("Instruction_Mem_Load.dat",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.m
emory_inst.mem);
$readmemh("Data_Mem_Load.dat"
,mips_top_tb.mips_top_inst.data_path_inst.memory_acc_inst.memory_inst.mem);
$readmemh("Register_File_Load.dat"
,mips_top_tb.mips_top_inst.data_path_inst.inst_decode_inst.reg_file_inst.register_file);
//Dump Instruction/Data Memories and Register file after execution
//of hex code is complete
#500
$writememh("Instruction_Mem_Dump.txt",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.
memory_inst.mem);
$writememh("Data_Mem_Dump.txt"
,mips_top_tb.mips_top_inst.data_path_inst.memory_acc_inst.memory_inst.mem);
$writememh("Register_File_Dump.txt"
,mips_top_tb.mips_top_inst.data_path_inst.inst_decode_inst.reg_file_inst.register_file);
end//end of initial
//Display Statements
initial
begin
$monitor($time,"
NEW
INST
FETCHED
OPCODE
%h",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.data_out_31_26," FUNCT
%h",mips_top_tb.mips_top_inst.data_path_inst.inst_fetch_inst.data_out_15_0[5:0]);
end
always @(posedge mips_top_tb.mips_top_inst.resetn)
begin
if(mips_top_tb.mips_top_inst.resetn == 1'b1)
$display($time," SYSTEM OUT OF RESET");
end
endmodule //End of Test bench
67 | P a g e
BITS
=
=
6. MAIN CODE
This section gives the original contents in the instruction memory as present in the
Instruction_Mem_Load.dat file. These contents correspond to the assembly language Test
Code provided as a part of the project. Please note that the instruction memory is 64 Words
Deep.
ASSEMBLY CODE
addiu r1 ,r0 ,#0x0004
slt r4 ,r2 ,r3
sllv r6 ,r7 ,r5
sub r9 ,r8 ,r10
xor r13,r11,r12
beq r14,r15,#0x0004 (LOOP1)
nop
nop
addu r18,r16,r17
sltu r21,r19,r20
LOOP1:addiu r23,r22,#0xFFFF
jr
r25
Nop
addi r2 ,r2 ,#0x0004
xori r27,r26,#0x006C
bltz r8 , #0x0003 (LOOP2)
nop
nop
addi r6 ,r5 ,#0xFF21
LOOP2:addi r4 ,r3 ,#0x007F
lw r7 ,r0 ,#0x0004
jal
#0x0017 (LOOP3)
sub r15,r13,r14
LOOP3:bne r11,r12,#0x0006 (LOOP4)
Nop
Nop
sw r16,r28,#0x0007
blez r0 , #0x0003 (LOOP5)
Nop
nop
LOOP4:sltu r19,r17,r18
LOOP5:slti r21,r20,#0x0008
j
#0x0022 (LOOP6)
sllv r23,r25,r24
LOOP6:sltiu r25,r26,#0x0016
bgtz r27, #0x0004 (LOOP7)
nop
nop
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HEX CODE
24010004
0043202a
00a73004
010a4822
016c6826
11cf0004
00000000
00000000
02119021
0274a82b
26d7ffff
03200008
00000000
20420004
3b5b006c
05000003
00000000
00000000
20a6ff21
2064007f
8c070004
0c000017
01ae7822
156c0006
00000000
00000000
af900007
18000003
00000000
00000000
0232982b
2a950008
08000022
0319b804
2f590016
1f600004
00000000
00000000
38220023
00853022
00e84826
Since the implementation is with pipelining NOP instructions have to be inserted after every
Jump Register and Branch instruction in order to avoid control hazards. Branch instructions get
resolved by the end of execution stage. Therefore two NOP instructions are required after
every branch instruction. Jump Register instruction gets resolved by the end of Instruction
Decode stage when the Register File contents have been read. Therefore one NOP is
required after JR instruction. Normal Jump (J and JAL) Instructions however do not require any
following NOP instructions because the jump offset gets calculated by the end of Instruction
Fetch stage itself. Dedicated hardware has been put in the Instruction fetch stage to calculate
the Jump offset.
69 | P a g e
70 | P a g e
CONTENTS
00000000
00000004
00000027
fffffffe
0000007d
00000004
00000079
04050607
0ffffe14
0bfaf813
ffffffec
ffff1111
ffff1111
00000000
0ff00ff0
0ff00ff0
0facfe67
00089076
1a2b3c4d
00000018
ffffeefe
00000001
fe243567
fe243566
00080022
00000000
ffffff6c
ffffff00
00000001
00ef11ff
00000000
00000058
DATA MEMORY
CONTENTS
xxxxxxxx
04050607
0facfe67
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
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9. CONCLUSION
32-Bit MIPS CPU was designed and implemented using the standard 5-Stage pipeline
The Given assembly code was executed using the above implementation and the results
were compared to the execution on a non pipelined machine
No of Cycles required to implement the given Assembly code on a non pipelined 32-Bit
MIPS CPU = 108 Cycles
No of Cycles required to implement the same Assembly code on a standard 5-Stage
pipelined 32-Bit MIPS CPU = 39 Cycles
5-Stage Pipelined implementation of the 32-Bit MIPS CPU gives a considerable
improvement in terms of the number of cycles required to execute a set of instructions
as compared to the non pipelined MIPS multicycle CPU executing the same set of
instructions. For the given assembly code an improvement of 69 clock cycles is achieved
by pipelining the CPU
In the pipelined implementation instructions get executed almost at the rate of one
instruction per cycle, except for the first one. The First instruction takes more cycles
because of the pipeline fill up time.
In the current implementation of the 32-Bit Pipelined MIPS CPU, NOP instructions had
to be inserted after every branch and jump register instructions in order to avoid control
hazards.
10.
FUTURE IMPROVEMENTS
Static Branch prediction schemes like flushing, Predict Branch taken, Predict Branch not
taken, Branch Delay slots can be implemented to avoid control hazards
Dynamic branch prediction schemes can also be implemented to avoid control hazards
Early branch prediction scheme can be implemented to reduce the penalty for branch
instructions.
Forwarding can be implemented to avoid data hazards
Floating point operations can be implemented. It may be a little tough but we can
definitely give it a try
More instructions can be added to the instruction set
Automation can be done to generate the hexadecimal code by directly parsing the
assembly language instructions
11.
The waveforms and synthesized gate level schematic are attached along with this report.
72 | P a g e