Evaluation of High Speed Low Voltage Noise Immune CMOS Design Style

ENG499 CAPSTONE PROJECT REPORT
SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
EVALUATION OF HIGH SPEED LOW

VOLTAGE NOISE IMMUME CMOS DESIGN
STYLE
STUDENT
: TAN HUI SHAN (Y0707051)
SUPERVISOR
: DERRICK TIEW
PROJECT CODE : JAN09/BEHE/36
A project report submitted to SIM University

in partial fulfilment of the requirements for the degree of
Bachelor of Engineering
NOV 2009
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TABLE OF CONTENTS
PAGE
ABSTRACT............................................................................................ I
ACKNOWLEDGEMENT...........................................................................II
LIST OF FIGURES.................................................................................III
LIST OF TABLE....................................................................................IV
CHAPTER 1. INTRODUCTION.............................................................- 1 1.1
1.2
1.3
1.4
BACKGROUND........................................................................................PROJECT OBJECTIVE...............................................................................OVERALL OBJECTIVE...............................................................................PROPOSED APPROACH...........................................................................-
1
2
2
2
CHAPTER 2.LITERATURE REVIEW......................................................- 5 2.1 BACKGROUND OF CMOS........................................................................- 5 2.2 REVIEW OF CMOS CIRCUIT FAMILIES......................................................- 6 2.2.1 Static CMOS Circuit..........................................................................- 6 2.2.2 Ratioed Circuit.................................................................................- 7 2.2.3 Differential Cascode Voltage Switch Logic (DCVSL).........................- 8 2.2.4 Dynamic Circuit...............................................................................- 8 2.2.5 Summary......................................................................................... - 9 2.3 CMOS PROCESS TECHNOLOGY INVESTIGATION....................................- 10 2.4 STATIC POWER INVESTIGATION............................................................- 10 2.4.1 MOSFET Junction Theory................................................................- 12 2.5 DYNAMIC POWER INVESTIGATION........................................................- 14 2.5.1 Voltage Level.................................................................................- 15 2.5.2 Physical Capacitance.....................................................................- 15 2.5.3
Activity Factor..............................................................................- 17 CHAPTER 3.CIRCUIT ANALYSIS........................................................- 19 3.1 FULL ADDER......................................................................................... - 19 3.1.1 STATIC CMOS FULL ADDER....................................................................- 19 3.1.2 DCVSL FULL ADDER.............................................................................- 20 3.1.3 12T FULL ADDER..................................................................................- 21 3.1.4 N10T FULL ADDER...............................................................................- 22 3.1.5 P10T FULL ADDER................................................................................- 23 3.2 COMPLEX DESIGN................................................................................- 24 3.2.1
Carry Ripple Adder (CRA).............................................................- 24 3.2.2
4-Bit Braun Multiplier....................................................................- 25 3.2.3
Fanout-of-4 Inverter.....................................................................- 26 CHAPTER 4.MENTOR GRAPHIC TOOLS.............................................- 28 4.1 INTRODUCTION TO MENTOR GRAPHIC TOOLS (MG).............................- 28 4.2
DESIGN PLATFORM..............................................................................- 28 4.2.1
Schematic Capture Window.........................................................- 28 4.2.2
Simulation Window......................................................................- 30 4.2.3
EZwave Window..........................................................................- 31 CHAPTER 5.EVALUATION RESULTS...................................................- 33 5.1
5.2
5.3
EVALUATION ON VOLTAGE & PROCESS TECHNOLOGY...........................- 33 DESIGN EVALUTION ON FULL ADDERS.................................................- 35 COMPLEX CIRCUIT EVALUTION.............................................................- 37 -
iii
5.3.1
5.3.2
5.3.3
Carry Ripple Adder.......................................................................- 37 Braun Multiplier............................................................................- 38 Advanced Analysis (Scaling).........................................................- 39 -
CHAPTER 6.PROPOSED METHOD.....................................................- 42 6.1 PN RATIO SCALING...................................................................................- 44 6.2 IMPLEMENTING ON INVERTER..............................................................- 47 6.2.1 Optimize Ratio on Inverter.............................................................- 47 6.2.2 Scaling Width on Inverter..............................................................- 48 6.3 IMPLEMENTING ON CARRY RIPPLE ADDER............................................- 51 6.4 IMPLEMENTING ON BRAUN MULTIPLER.................................................- 53 6.5 COMPARING DELAY OF 3 CIRCUIT.........................................................- 55 6.6
COMPARING AVERAGE POWER CONSUMPTION....................................- 56 CHAPTER 7.PROBLEM FACED..........................................................- 57 CHAPTER 8.CONCLUSION...............................................................- 60 CHAPTER 9.RCOMMENDATION........................................................- 60 CHAPTER 10......................................................................................... REFLECTION
- 61 CHAPTER 11........................................................................................ REFERENCES
- 62 APPENDIX A: FULL ADDER TABULATION...........................................- 65 APPENDIX B: LOGICAL EFFORT CACULATION....................................- 66 APPENDIX C: STATIC CMOS SCHEMATIC & RESULTS..........................- 70 APPENDIX D: DCVSL SCHEMATIC & RESULTS...................................- 73 APPENDIX E: 12T SCHEMATIC & RESULTS........................................- 76 APPENDIX F: N10T SCHEMATIC & RESULTS......................................- 78 APPENDIX G: P10T SCHEMATIC & RESULTS......................................- 80 -
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ABSTRACT
With the advancement of technology, Integrated Chip (IC) has achieved smaller chip
size with more functions integrated. Through the usage of more transistors, it has lead
to an increase of power dissipation and undesired noise. As the design gets more
complex, this results in slower speed. Hence, the demand for low power, fast speed
and low noise designs are desired. Designers and researchers are developing new or
modifying existing designs to cater for this demand. The objective of this project is to
propose a method to overcome these limitations. Voltage reduction with width scaling
are implemented into static CMOS circuits and evaluated in this project. The static
CMOS circuitry is selected due to its ability to achieve low noise, power and fast
speed. Through simulation, the static CMOS circuitry performed better than the other
circuitry families (eg. DCVSL, 12T, N10T and P10T). The proposed method achieved
the objective of this project when implemented onto a complex design of smaller
process technology (less than 60nm).
ACKNOWLEDGEMENT
I would like to thanks my Tutor Mr. Derrick Tiew for his patience, suggestions and
guidance in the course of this project.
I would also like to express my appreciation to my lecturers, family and friends for
their support and understanding throughout the course in the project.
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LIST OF FIGURES
Figure 1 : Schematic of first Transistor.................................................................................................- 5 Figure 3: A Ratioed Circuit Pseudo NMOS.......................................................................................- 7 Figure 4: How Pseudo NMOS works....................................................................................................- 7 Figure 6: A Dynamic inverter................................................................................................................- 8 Figure 7: Inverter in Ideal Case...........................................................................................................- 11 Figure 8: Basic Structure of NMOS without Power Connection........................................................- 12 Figure 9: NMOS in Sub-threshold Mode............................................................................................- 12 Figure 10: NMOSFET showing types of leakage...............................................................................- 13 Figure 11: Capacitance in a MOSFET................................................................................................- 16 Figure 12: Load Capacitance at Output...............................................................................................- 17 Figure 13: Schematic of Static CMOS Full Adder..............................................................................- 20 Figure 14: Schematic of DCVSL Full Adder......................................................................................- 20 Figure 15: Schematic of 12T body-bootstrapped Full Adder..............................................................- 21 Figure 16: Schematic of N10T Full Adder..........................................................................................- 22 Figure 17: Leakage Occurrence When Inputs Are High.....................................................................- 23 Figure 18: Schematic of N10T Full Adder..........................................................................................- 23 Figure 19: Leakage Occurrence When Inputs Are Low......................................................................- 24 Figure 20: Block diagram of Carry Ripple Adder...............................................................................- 24 Figure 21: Concept of How Braun Multiplier works..........................................................................- 25 Figure 22: Schematic of Braun Multiplier..........................................................................................- 26 Figure 23: Concept of a FanOut-Of-4 inverter....................................................................................- 27 Figure 24: Main Window....................................................................................................................- 29 Figure 25: Creating Schematic............................................................................................................- 29 Figure 26: Simulation Window...........................................................................................................- 30 Figure 27: ASCILL Log file results....................................................................................................- 31 Figure 28: EZwave window with trise & tfall measurement (20%-80%)...........................................- 32 Figure 29: EZwave window with Delay measurement (50%)............................................................- 32 Figure 30: Static CMOS FA (Comparing Average Power).................................................................- 34 Figure 31: Static CMOS FA (Comparing Average Power w.r.t process technology)..........................- 35 Figure 32: Comparison of static CMOS and DCVSL in Carry Ripple Adder (Voltage Scaling).......- 40 Figure 33: Comparison of static CMOS and DCVSL in Braun Multiplier (Voltage Scaling)............- 41 Figure 34: Schematic of Fanoutof-4....................................................................................................- 44 Figure 35: Waveform measurement....................................................................................................- 45 Figure 36: Optimize ratio of FO-4 (Visual View)...............................................................................- 46 Figure 37: Delay using optimizing ratio on different voltages...........................................................- 48 Figure 38: Showing the delay of selected scaling...............................................................................- 50 Figure 39: Average power consumption of selected scaling...............................................................- 51 Figure 40: Delay of proposed method on carry ripple adder..............................................................- 52 Figure 41: Average power of proposed method on carry ripple adder................................................- 53 Figure 42: Delay of proposed method on Braun Multiplier................................................................- 54 Figure 43: Average power of proposed method on Braun Multiplier.................................................- 54 Figure 44: Comparing Delay characteristic on proposed method.......................................................- 55 Figure 45: Comparing Average Power characteristic on proposed method........................................- 56 Figure 46: Verification the theory of proposed method......................................................................- 57 Figure 47: Gang CMOS schematic.....................................................................................................- 58 Figure 48: FanOut-of 2 and 3..............................................................................................................- 58 Figure 49: Delay and Average of Proposed method on Carry Ripple Adder by external source........- 59 Figure 50: Delay and Average of Proposed method on Braun Multiplier by external source............- 59 -
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LIST OF TABLE
Table 1: Comparison Chart of Circuit Families....................................................................................- 9 Table 2: Semiconductor Process Technology......................................................................................- 10 Table 3: Voltage & Process Evaluation of Static CMOS FA...............................................................- 34 Table 4: Process Evaluation of Static CMOS FA................................................................................- 34 Table 5: Simulation Results of 5 Full Adders.....................................................................................- 36 Table 6: Static CMOS and DCVSL full adder in Carry Ripple Adder................................................- 37 Table 7: Static CMOS and DCVSL full adder in Braun Multiplier....................................................- 38 Table 8: Optimize ratio of the FO-4....................................................................................................- 46 Table 9: Optimize width setting..........................................................................................................- 47 Table 10: Results of Optimize ratio on different voltages...................................................................- 47 Table 11: Voltage and width scaling of proposed method...................................................................- 50 Table 12: Scaling width meet requirements........................................................................................- 50 Table 13: Proposed method on Carry Ripple Adder...........................................................................- 52 Table 14: Results of proposed method on carry ripple adder..............................................................- 52 Table 15: Proposed method on Braun Multiplier................................................................................- 53 Table 16: Results of proposed method on Braun Multiplier...............................................................- 54 -
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CHAPTER 1. INTRODUCTION
1.1
BACKGROUND
Over the years, low power consumption, high speed and low noise have always been
important factors in designing a chip. With the advancement in process technology,
some of the designs that served well in earlier technologies may not be suitable now.
Power consumption come in two forms; static and dynamic power. With the latest
process technology, static power can easily exceed dynamic power consumption. So,
new design or modifying earlier designs is essential to ensure all reliability issues are
solved.
Power consumption is critical at the chip level as excess power is dissipated as heat.
IC chips with limited dissipation capacity can cause overheating issue and become
damaged. If the level of activity generated increases, excessive power can cause
unreliability issues in the chip. This excessive power consumption will affect the
amount of transistors to be effectively placed on a single chip.
With the reduction of IC chip, it is more susceptible to noise. Noise is generated in
many different ways. One of the main causes is due to interconnect. With current
technology, a delay going through a wire may take longer time than the gate driving
through it. The parasitic components of the wire are so great that crosstalk may occur
between signals and create problems.
With this, CMOS chip designer need to understand the close relationship in creating
different circuit topologies for addressing power consumption, speed and noise issues.
1.2
PROJECT OBJECTIVE
The objective of this project is to propose a method to overcome the limitations of a

chosen CMOS circuit design for high speed, low voltage and noise immune
application. This project includes the initial analysis of existing circuit designs to
evaluate its pros and cons. Based on the analysis result, a design circuit is chosen and
the propose method will be applied to address the limitations. Then, the improved
method circuit are to be tested out on complicated design and output load.
1.3
OVERALL OBJECTIVE
With the advancement in technology and the reduction of process technology

parameters, maintaining Integrated Circuit (IC) performance and continuous
improvement of circuit design are essential.
When the project objective has been achieved, it will benefit both the users and the
Environment. Portable devices can achieve longer battery life and stationary devices
in factory or home can achieved a cost saving environment. With the drop in
unnecessary power dissipation, less energy is used. This created an eco-friendly
Environment.
1.4
PROPOSED APPROACH
The first approach of this project is to do a literature study on the history of CMOS
circuit design and an intense background study of low power design methodologies.
In this project, all evaluation of circuits uses the SPICE simulation using Mentor
Graphic Tools.
Several design circuit styles have been identified, i.e. static CMOS logic, no race
dynamic CMOS logic (NORA), differential cascode voltage switch logic (DCVSL),
CMOS non-threshold logic (CNTL), enable/disable CMOS differential logic (ECDL),
enhancement source coupled logic (ESCL).
The circuit style is first implemented on a full adder. Functionality of the full adder is
first checked. Glitches and abnormality of the results are corrected. Then, the various
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circuit parameters will be measured, i.e. peak switching current, average current,
propagation delay, transistors count, etc. The full adder is then cascaded to form a 16bit ripple carry adder and 4-bit braun multiplier to evaluate the speed and performance
of the critical path, and power consumption of the circuit design style.
The investigation of the proposed method is executed. It will be carried out on the
FanOut of 4 circuit and the inverter gate. When the theory of the proposed method has
been achieved, the scaling method will then be implemented into more complex
designs and output load for verifications. Results will be assessed and concluded.
A summary of the proposed approach is shown in the following flowchart:
Literature
Literature Study
Study
Not suitable
Circuit
Circuit Model
Model
selection
selection
Selected suitable design
dd
Draw
Draw Designs
Designs
Parameters
Parameters settings
settings
Measurements
Measurements
Poor
Good
Identify
Identify Pros
Pros and
and
Cons
Cons
No
Yes
Selected
Selected Designs
Designs
Implement
-Adder
-Adder
-Multiplier
-Multiplier
Poor
Measurements
Measurements
Method
Method suggested
suggested
based
based on
on Research
Research
Journal
Journal
Selected
Good
Selected
Selected Method
Method
-FanOut
-FanOut Of-4
Of-4
-Inverter
-Inverter
Fail
Investigate
Investigate
Proved
Troubleshoot
Troubleshoot
-Adder
-Adder
-Multiplier
-Multiplier
Fail to meet
criteria
Measurements
Measurements
Meet criteria
Conclusions
Conclusions
CHAPTER 2. LITERATURE REVIEW

2.1
BACKGROUND OF CMOS
In 1963, Frank Wanlass from Fairchild Semiconductor originated the idea of

combining PMOS and NMOS. This combination of transistor earns the name of
Complementary Metal Oxide Semiconductor, or CMOS [9][25].With this concept of
CMOS, this has created a breakthrough in technology.
The field effect transistor theory was first patented in 1925 by a physicist Julia Edgar
Lilienfield. However, no research articles were published. Thus, another physicist, Dr.
Oskar Heil, patented it in 1934.
Figure 1 : Schematic of first Transistor

Source: (A History of the Invention of the Transistor and Where It Will Lead Us)
The invention of transistor has lead to more evolution of transistor types. Bipolar
Junction Transistor was one of the earliest and is still one of the important
technologies being used in current switching applications. When implemented into an
IC, it is more reliable and power efficient. One downfall of Bipolar Junction
Transistor is that the maximum number of transistors to be integrated in a single die is
limited by quiescent power dissipated. This posed a difficulty in Large Scale
Integration.
This has led to another evolution in transistor types; Metal Oxide Semiconductor
Field Effect Transistors (MOSFET) which was developed shortly. MOSFET
consisted of an n-type and p-type channel; NMOS and PMOS. MOSFET offers the
advantages of operating at high voltages.
PMOS was commonly used when MOSFET when formed. However, due to its poor
performance and reliability, NMOS was widely used. Though NMOS is cheaper but
its setback was drawing current even in its idle state. This has posed a problem when
the demand of implementing hundreds of thousands of transistors, Very Large Scale
Integration (VLSI) into a die increases. This results in an increment of total power
consumption and causes overheating issue. In the 1980s, this became a major concern
in the semiconductor industry.
Though CMOS was developed in the 1960s, its processes were only widely adopted
in the 1980s to overcome the power consumption issues. CMOS has the advantage of
zero quiescent power dissipation. CMOS logic greatly reduces the heat dissipation
and power consumption.
The usage of CMOS processes has eventually replaced. Till date, CMOS is still
widely used in integrated circuits.
2.2
REVIEW OF CMOS CIRCUIT FAMILIES
This section discussed about various types of circuit families available and review.
2.2.1 Static CMOS Circuit

Static CMOS circuits consisted of a complementary PMOS as pull-up and NMOS as
pull-down networks. Majority of the circuit designs are still using this as it provides
low noise, low power and fast speed. Due to its highly adopted design, it is widely
supported by CAD tools.
Figure 2: A Static CMOS inverter
2.2.2 Ratioed Circuit

Ratioed circuit replaced the pull-up PMOS network by connecting it to a ground. By
connecting PMOS to a ground, there is a great reduction in the pull-up transistors
used when used in a complex design. This method also brings down the capacitance
of the input by using a single resistance. However, it faces the disadvantages of slow
rising transitions and static power dissipation.
One example of a ratioed circuit is the pseudo NMOS in an inverter gate.
Y
A
Figure 3: A Ratioed Circuit Pseudo NMOS

VDD
VDD
Always ON
Y
A=low
Y=VDD
A=high
Y=GND
Direct
Path
Figure 4: How Pseudo NMOS works
When A is low, NMOS is off and a strong PMOS take place, the gate output Y will
follow VDD. When A is high, both NMOS and PMOS are on. Output voltage
depends on the stronger network.
As PMOS is always turned on and when the NMOS is also turn on, a conducting path
exists between VDD and ground. This consumes static power.
The pseudo-NMOS are considered in a circuit design where the sizing and wiring
complexity are a major concern.
2.2.3 Differential Cascode Voltage Switch Logic (DCVSL)

Differential Cascode Voltage Switch Logic strives to counter the static power
dissipation in a ratioed circuit. This circuit create true and complementary output. The
pull-up network is not connected to ground but to its complementary output.
Advantage of this design is faster as only NMOS is used in all logic performance
however it require its complementary input to function which lead to more transistor
used.
VDD
Y not
F not
Figure 5: A Differential Cascode Voltage Switch Logic circuit
2.2.4 Dynamic Circuit

Dynamic circuit is similar to Ratioed circuit but the PMOS is tied to a clock. PMOS is
not always on as it is controlled by the carefully planned clock.
CLK
Y
A
Figure 6: A Dynamic inverter
When clock is low, PMOS is on. It has a fast switching speed but it requires precise
clocking and is sensitive to noise.
2.2.5 Summary
Families
Static CMOS
Ratioed
DCVSL
Dynamic
Fast
Low power
Noise Sensitivity
Table 1: Comparison Chart of Circuit Families
The above 4 circuit families discussed have low power advantages. Ratioed, DCVSL
and dynamic families uses less pull-up network, this brings down the overall power
consumption. However, other power consumption (e.g. static power dissipation in
ratioed families) adds on to the power consumption.
Static CMOS circuit is astonishingly efficient for their usage of power in logic
computation and is widely used for high noise margin design. However, it requires
higher number of transistors used as it requires the same number of PMOS and
NMOS. The major disadvantage of a static CMOS circuit is its limitation to run at
high clock speed.
Though ratioed circuit reduce area, its static power dissipation will create a major
problem when design gets complex.
DCVSL is suitable for evaluation as it resolves the issue of static power dissipation
and has good noise margins.
Dynamic circuit has a few advantages over the static CMOS and ratioed circuit. It
does not require the same number of transistor pairs which reduces the surface area
and is able to run at high clock speed applications.
The advantages of dynamic circuit do not come without a cost. Due to the nature of
dynamic CMOS logic, undesired effects like noise can occur within the circuit unless
extra effort is put during the engineering design.
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2.3
CMOS PROCESS TECHNOLOGY INVESTIGATION
The CMOS process technology plays an important part in IC design. With the
progress of the process technology, it is possible to create IC of smaller area.
In the 1970s, process technology started at 10um. Till present, the technology is kept
at 32nm. Following the trend of technology, it is estimated that by year 2015, process
technology will hit 11nm. With the decreasing nanometre process, smaller ICs can be
created. However, it will be harder to control the characteristics of the devices. While
smaller IC is in creation, power dissipation will become more critical as the threshold
voltage (Vth) decreases.
Semiconductor manufacturing
Processes
10 m
3 m
1.5 m
1 m
800 nm (0.80 m)
600 nm (0.60 m)
350 nm (0.35 m)
250 nm (0.25 m)
180 nm (0.18 m)
130 nm (0.13 m)
90 nm
65 nm
45 nm
32 nm (Double Patterning)
22 nm (End of Planar Bulk CMOS)
16 nm (Transition to Nanoelectronics)
11 nm (Nanoelectronics)
Table 2: Semiconductor Process Technology
Source: (http://en.wikipedia.org/wiki/32nm)
2.4
STATIC POWER INVESTIGATION
Static power in earlier technologies is negligible and can be ignored. But static power
is important in today technology due to VLSI integration and smaller process
technology. Static power dissipation can even exceed the dynamic power
consumption. Due to its importance, static power is being analyzed when
implementing new design.
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In an ideal case, CMOS circuits do not produce any static power. It is constructed to
turn on one MOS at a time. With the logic of turning one MOS each at a time, there
will not be a direct short circuit path between voltage source and ground.
This logic can be is best explained by using an inverter gate.
Source
A
VDD
VDD
Y
A=low
Y=VDD
A=high
Y=GND
Source
(a)
(b)
(c)
Figure 7: Inverter in Ideal Case
In the case of an inverter gate, it consisted of one NMOS and PMOS. The source of
the PMOS is tied to a voltage supply (Fig.7a). PMOS turned on only when the
applied input is low. Similarly for NMOS, its source is tied to ground and will only be
turned on when a high input is applied.
From Fig.7b, when a low is applied at the input, the PMOS is turn on. Therefore, the
output will switch to VDD. Likewise, in Fig.7c, when a high input is applied, NMOS
is turn on and the output will switch to ground.
As a result, it can be seen that there is no direct path from VDD to GND during
switching. Thus, it can be said in an ideal case, there is zero power dissipation when
there is no switching.
However in practical applications, small leakage current from various source, Istatic
exists. It can be said that Pstatic is a sum up of sub-threshold conduction in OFF
transistors and leakage occurring through reverse junction diode. Static power can be
described as consuming power even when the gate is quiet and output is unchanged.
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Static power dissipation, if not taken care during design phase can cause undesired
output.
2.4.1 MOSFET Junction Theory

There are a few types of leakage that occur in a MOSFET which results in static
power dissipation.
Basically, current leakage is causes by sub-threshold conduction, gate tunnelling and
reverse-biased diode leakage.
The below illustration explains NMOS junction.
S o u rce
S
G a te
G
D ra in
D
M e ta l e le c tro d e s
D
S iO
in s u la tio n
H e a v ily d o p e d G
n -re g io n
p -ty p e su b str a te
B lk
S
D e p le tio n la y e r
B lk
B u lk (S u b s tra te )
Figure 8: Basic Structure of NMOS without Power Connection
Ideally, NMOS turn on and current flows only when Vgs> Vth.
In reality, current does not cut off when Vgs is lower than Vth. If Vds>0 existed. This is
called sub-threshold conduction. It causes leakage in a transistor and contributed to
static power dissipation.
Figure 9: NMOS in Sub-threshold Mode
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Fig.9 shows NMOS in sub-threshold mode. It can be observed that when Vds is
greater than ground, a conduction occurs and depletion region is formed. Current
flows through from the source to the drain.
Using the case of an inverter NMOS, the source and drain gates are attached to its
relevant supply. Though there is no activity, a depletion layer existed at the n+ region.
Diffusion between electrons and holes take place.
GND
GND
GIDL
VDD
M etal electrodes
D
S iO
n +
n +
insulation
B lk
H eavily doped G
n-region
S
Subthreshold
leakage
B lk
Ijunction
Depletion layer
(In practical)
Gate directtunnelling leakage

Figure 10: NMOSFET showing types of leakage
Fig.10 shows an inverter NMOSFET with 4 types of leakages in static mode (no
switching action). The drain is tied to VDD and the source and gate to the ground.
Then Tte NMOS is turn off. In reality, there is an imperfect depletion region (see
curve depletion layer at Fig.10) formed at the junction region.
Sub-threshold leakage is an unwanted current flow between source and drain in the
sub-threshold region when Vgs><Vth (see Fig.9). The depletion region is formed
between 2 n-type substrate when Vgs < Vth and Vds > 0. It is dependent to
temperature variation and process technology size.
Reversed-biased P-N junction creates junction leakage. Dependent on the doping
level, a diode is formed between n-type and p-type substrate. The substrates are tied to
a power supply and ground in reversed-biased mode. Nevertheless, reverse-biased
diode still produces a small amount of current.
13
Gate direct tunnelling leakage is a direct tunnelling between gate oxide and substrate.
When the gate oxide is thin, the electrons tunnel through and current flows into the
gate. This occurrence is not significant in earlier process technology but important
when process got smaller.
Gate induce drain leakage (GIDL) happens when the gate voltage is at a low bias and
drain voltage is at high bias. This happens near the depletion region of the drain gate
and the gate oxide, where the movements of electrons and holes injected across.
GIDL increases exponentially with the gate oxide thickness. With the advancement of
process technology, this gate oxide leakage can be on par with sub-threshold current.
The summation of I gidl , I junction , I direct tunnelling & I sub threshold produces the static power
dissipation when both transistors are OFF.
I static I gidl I junction I sub threshold I direct tunnelling
The static power dissipation is the product of total leakage current and supply voltage.
Pstatic I staticVDD .
With today technology of achieving threshold voltage at 0.2V, leakage current reached
may exceed by half of the overall power consumption in a circuit. Therefore, it is
advisable to create a low power design circuits to tackle the static and short-circuit
power dissipation. Therefore, Engineers include the concept of low power in today
design.
2.5
DYNAMIC POWER INVESTIGATION
When a low power design circuit is achieved, the static power can be considered as
negligible as there is another power dissipation that occurs when load capacitance
charges and discharges during switching. Dynamic power is consumed when the gates
drive their output to a new value. It plays a dominant role in total power dissipation.
There are a few contributing factors that lead to an increase in the power dissipation.
Designers and researchers have narrowed the factors to three main categories.
The factors are:
1. Voltage Level
14
2. Physical Capacitance
3. Activity Factor
2.5.1 Voltage Level

Voltage has a direct relationship with Power. P=IV (Watts). In dynamic power, it is
proportional to (VDD2) whereas the static power is dependent on the VDD. It is
believed that by reducing the supply voltages in CMOS, the power dissipation can be
reduced. Past circuit designs uses 5V. With the improvement of technology, choice of
voltages has evolved. The most commonly used voltages are 5V, 3.3V and 1.8V. Since
supply has a direct relationship with power dissipation, by scaling the voltage level
can create an impact in the power dissipation. However, there are a few factors such
as maintaining the performance and compatibility issues to be considered during
voltage reduction.
When the voltage decreases, there is a possibility that delays may occur. With the
occurrence of delays, system performance dropped. Ways have to be implemented to
compensate for this drop of performance. To be safe, it is suggested to limit the range
of voltages supply to a minimum of two times the threshold voltage (Vth).
It is essential to scale the threshold voltage to satisfy the system performance. In spite
of this, this will lead to an increase in leakage power. Thus, extra care is needed when
voltage scaling is performed.
2.5.2 Physical Capacitance

There are a few types of capacitance. Parasitic capacitance occurs in all transistors
and power is required to charge the capacitor. When the capacitance of a design
increases, more power is needed. This increases the overall power consumption.
One type of the capacitance comes from transistor. Capacitance is proportional to the
width of transistor; the input capacitance is the sum of all the inputs width. When a
circuit design get complex, the amount of capacitance increases. The size of
capacitance affects the amount of power drawn due to charging. However, size of load
capacitance is determined by calculating the transistor size for a balanced circuit.
15
Ways to counter the increment in capacitance is to use less logic. Thus, resources
sharing and gate sizing can help to reduce the load capacitance.
Figure 11: Capacitance in a MOSFET
Another type of capacitance that exists in a circuit is the wire linking the transistors
together which is called Interconnect. It adds on to the loading capacitance and may
account to a large amount of power. Therefore, careful planning of the routing is
required to minimize the length of wires.
Nevertheless, there are also factors to be considered as reducing the capacitance
reduces its current driving capability which could lead to slower operating system.
16
2.5.3 Activity Factor

Analysis is shown using an inverter with a capacitor connected to its output.
VDD
A=low
VDD
A=high
Y=VDD
CL
Y=GND
CL
CL
CL = Charged
(a)
(b)
CL = Discharged
(c)
Figure 12: Load Capacitance at Output
When the input goes low Fig. 12b, output is set to VDD, the load capacitor is
charged. An Energy of Q=CVdd2 is executed. When the input is set to high, the
capacitor is discharged to ground. The transition of input (switching activity) from
high to low produces charging and discharging, which results in power dissipation.
This can be concluded that when switching activity occurs within a clock cycle,
power dissipation happens.
2
To calculate dynamic power dissipation, Pdynamic CVdd f
where
= activity factor
CVdd 2 = energy of load capacitance drawn
f
= system clock frequency
Assuming that a load capacitance experiences switching over a certain average

frequency of fsw in a period of time T. It means that a load capacitance is being
charged and discharged in Tfsw times. But majority of gates do not switch at every
clock cycle. When no switching occurs, it will not dissipate any dynamic power.
17
As mentioned that gates do not switched at every clock cycle, another way to express
this phenomenon is to express it as f . Where
is the activity factor and
is the
clock frequency.
A 1 cycle clock (1 rising and 1 falling transition) has an activity factor of 1. Data will
have a limit of 0.5 as it transits once per cycle.
1 cycle
There is no actual way to calculate an activity factor. But it can be observed by seeing
if there is any glitch that results from it when there is an unbalanced propagation
delays. Glitch can cause power consumption during transition and should always be
avoided.
18
CHAPTER 3. CIRCUIT ANALYSIS

This chapter discuss about the various circuit families that have been applied in this
project. Their advantages and disadvantages will be discussed in detail. Circuits
analyzed consist of Static CMOS, DCVSL, 12T, P10T and N10T full adder. Complex
circuits consist of 16-bit ripple carry adder, 4 bit braun multiplier and Fanout-of-4.
3.1
FULL ADDER
Full adder is commonly used in circuit design research with the ability to perform
binary addition. Basic adders compute a 1-bit sum and carry from the two input with a
carry-in.
It has the equation of:
Sum abc abc abc abc
Carry ab ( a b) c
Demonstration of the equation is shown in Appendix A
3.1.1 Static CMOS Full Adder

Static CMOS is commonly used in most application and is made up of
complementary pull-down NMOS and pull-up PMOS to drive high and low input.
This is to ensure that either power or ground is always supplied to the output.
It has the advantages of producing good noise margins, fast speed and low power
circuit. As this design requires the same number of PMOS and NMOS, this causes
layout area restrictions which led to the usage of other circuit families.
19
Figure 13: Schematic of Static CMOS Full Adder
Fig.13 shows a full adder circuit for a static CMOS design. Another 3 inverters (6
transistors) are used for producing A,
B and C
. A total of 32 transistors are used.
3.1.2 DCVSL Full Adder
Figure 14: Schematic of DCVSL Full Adder
20
By replacing the PMOS of a cascode voltage switch logic (CVSL) of ratioed family,
differential cascade voltage switch logic (DCVSL) is formed. The cross coupled pair
of the PMOS acts a differential pair which helps to speed up transitions.
It belongs to the static family similar to pseudo-NMOS logic but of a different
structure. A latch structure is used for the pull-up and has the ability to eliminate nonleakage power consumption. This design produced true and complements outputs.
In contrast with static CMOS design, this requires lesser transistors.
3.1.3 12T Full Adder

Previously designed 12T adder does not operate correctly when applied in a multiplier
[24]. The reason for the failure is due to the threshold voltage losses which in turn
causes error at the output.
Figure 15: Schematic of 12T body-bootstrapped Full Adder

Source: (12T Body-bootstrapped-buffer_circuit_for_CMOS_static_power_reduction)
In Fig.15, this new design (12T Body-booted-buffer) is extracted from a research

journal [14]. It increases the threshold voltage to reduce power dissipation. It ensures
that the value for ground is kept negative and positive for power.
21
It uses transmission gate to produce Cout. Although it has the advantages of improving
area, speed and power consumption, it accumulates noise which an inverter is
recommended to be added to the output. However, it requires another 2 inverters to
revert it back to Cout.
Due to its low threshold voltage, 12T full adder is susceptible to noise.
3.1.4 N10T Full Adder
Figure 16: Schematic of N10T Full Adder

Source: (Low_power_n-bit_adders_and_multiplier_using_lowest-number-of-transistor)
Most 10T adders experience threshold voltage loss at the output voltage level when
tested at 180nm and subsequent process technology. This error was not critical in
earlier technologies. As process technology progress, this creates problems.
N10T is designed to ensure that the critical part of an adder, carryout, is able to have a
full swing output. As seen in Fig.16, the output, SUM, experiences loss. Although it
does not operate fully, the reduction of transistors saved area space.
The input Cin is tied to NMOS. When A=B=VDD, PMOS of inverter does not turn off
and create unwanted leakage. It has the advantages of operating properly when one of
the XOR gate has threshold loss.
22
Figure 17: Leakage Occurrence When Inputs Are High

3.1.5 P10T Full Adder
Figure 18: Schematic of N10T Full Adder

The concept of P10T Full Adder is the same as N10T except that the input Cin is tied
to PMOS.
When A=B=ground, NMOS of inverter not turn off and create unwanted leakage
23
Figure 19: Leakage Occurrence When Inputs Are Low
3.2
COMPLEX DESIGN
When the 5 full adders of the previously mentioned have been evaluated, the selected
design will be further integrated into a more complex circuitry. Theoretically,
multiplier consumes more power than an adder. Therefore, by implementing a full
adder design into a ripple carry adder and a braun multiplier, help in ensuring that the
proposed method in creating low power, high speed, low noise design. Hence, based
on the selected full adder, 16-bit ripple carry adder and 4 bit braun multiplier were
designed.
3.2.1
Carry Ripple Adder (CRA)
Figure 20: Block diagram of Carry Ripple Adder
N-bit carry ripple adder is created by cascading n 1-bit full adder. As carry ripple
adder is easy to design and efficient, it provides a good platform in evaluating a full
24
adder design. The disadvantage of having large n cascade of adders is longer

propagation delay. Each carryout, carry, of a full adder is connected to the carry-in, C,
of the next adder. Gate delay is measured by comparing the final carry-out (Cout) of
the last adder with the first carry-out of first adder (C0) as seen in Fig.20. It needs to
wait for the carry bit of the previous adder before calculating its sum.
This project uses a 16-bit carry ripple adder. Thus, it requires 15 carry computations
and final sum calculation. Total gate delay 15*2 +1 =31 gate delays
The critical path of a ripple carry adder is usually the path from Cin to Cout. A good full
adder design has fast carry delay.
3.2.2
4-Bit Braun Multiplier
Figure 21: Concept of How Braun Multiplier works
25
Figure 22: Schematic of Braun Multiplier
Since addition and multiplication are essential arithmetic operation and multiplier
consumes more power. Multiplication verification needs to be done as this will ensure
that the power consumption has been tackled from all forms of operation.
Multiplication can be used for DSP applications [25] such as filtering and fast Fourier
transform. Parallel multiplier is widely used to achieve high execution speed.
An array implementation of parallel multiplier is braun multiplier. Its last adder has a
carry chain. It has the advantages of low capacitance and fast speed. However, its
small swing gives rise to high current.
3.2.3
Fanout-of-4 Inverter
Fanout-of-4 drives a load with many transistors by using a gate input. It simulates an
environment where one input is connected to several gates inputs and drive a complex
output made up of many logic gates.
26
This design is applied in the proposed method section where the best PN ratio of the
transistors is measured.
Device
Under
Test
Shape input
2
X1
1
8
X2
4
Load
Load on
Load
32
128
512
d
e
f
X3
X4
X5
16
64
256
Figure 23: Concept of a FanOut-Of-4 inverter
27
CHAPTER 4. MENTOR GRAPHIC TOOLS

This chapter introduces and describes Mentor Graphic Tools (MG) software. Mentor
Graphic Tools has been widely used for IC design, schematic placement, layout
routing and simulation. It offers the evaluation and verification of circuit design.
Carrying out a simulation before fabrication allows designers to verify the circuit
performance and predict its behaviour.
4.1
INTRODUCTION TO MENTOR GRAPHIC TOOLS (MG)
Mentor Graphic Tools (MG) is a powerful software system for electronic design
operated in Linux system. It provides a complete set of designing circuit at the lowest
hierarchy, circuit simulators and layout (with Design Rule Check) tools.
4.2
DESIGN PLATFORM
All designs are executed within the framework of MG. Designer starts with schematic
capture, followed by simulation and layout. The software allows designer to be
informed of any discrepancies before proceeding to next procedure. MG provides the
flexibility to link back schematic while doing simulation and layout.
Files can be transferred by using Linux command (root folder) and editing the root
settings. This creates a flexibility environment from changing one workstation to
another.
4.2.1
Schematic Capture Window
The creation of project and designs are created in this window.
28
New Design
Figure 24: Main Window

Library Plaette
Transistors
Figure 25: Creating Schematic
29
The following functions are available from the schematic window:
Create and design schematic
Setting of width/length parameters
Open multiple schematics
Set power sources and its parameter
Checking of design
Generate symbol
4.2.2
Simulation Window
The simulation settings are done in this window. Results are viewed from the log file
where leakage current and selected measurements are recorded. Waveforms are
viewed using EZwave.
Simulation Paleette
Figure 26: Simulation Window
Simulation Palette:
Lib/Temp/Inc Temperature setting and include the process technology model

file (180nm) to be used
30
Analysis Setting of transient period for the whole simulation
Measurements Measure max/ average current / power.
ASCII files Log file of Measurement and leakage current results
View Waves Viewing of waveform with EZwave
Figure 27: ASCILL Log file results
4.2.3
EZwave Window
EZwave window show the waveform after simulation. It has a wide range of
measurement tools. The commonly used measurements tool for this project is the rise
time, fall time and delay.
31
Figure 28: EZwave window with trise & tfall measurement (20%-80%)
Figure 29: EZwave window with Delay measurement (50%)
32
CHAPTER 5. EVALUATION RESULTS

This chapter discussed about the investigation carried out on the full adder of the 5
circuit families (static CMOS logic, differential cascade voltage switch logic
(DCVSL), 12T, P10T and N10T). The circuits are drawn and evaluated.
The initial evaluation compares the results of different voltages and process
technology used. All circuits have passed their logic verification.
With the implementation of design, there are a few factors to be considered:
1. Transistor Sizing
2.
Process technology
3. Power supply
4. Logic Verification
Terms:
Average Current: The average current consumption over the range of simulation period
Peak Current: The maximum current spike obtained during the simulation period.
Leakage Current: The current consumption when circuit is in static mode. This determine the static
power consumption
5.1
EVALUATION ON VOLTAGE & PROCESS

TECHNOLOGY
Initial step of the evaluation include assessing how the process technology and
voltage supply will affect the power consumption. Static CMOS are used for
evaluation for this section.
33
Static CMOS Full Adder:

Type:
Process
Voltage
Paverage (uW)
Iaverage (uA)
Static CMOS FA
350nm
5V
3.3V
10981
1533.4
2196.3
464.654
1.8V
98.6472
54.804
Table 3: Voltage & Process Evaluation of Static CMOS FA
** Logic Verification passed
Figure 30: Static CMOS FA (Comparing Average Power)
Analysis:
Fig.30 shows that voltages applied will affect the overall power consumption. Since
5V has the highest power consumption, it will be removed from future investigation.
Type:
Static CMOS FA
Process
180nm
Voltage
3.3V
1.8V
Paverage (uW)
9.5296
0.8016
Iaverage (uA)
2.8878
0.4453
** Logic Verification passed
Table 4: Process Evaluation of Static CMOS FA
34
Figure 31: Static CMOS FA (Comparing Average Power w.r.t process technology)
Analysis:
Comparing the difference in the power consumption between 3.3V and 1.8V (Fig.31),
3.3V draws the most. As observed in table. 3 and 4 at the 1.8V supply, average power
drops from 98uW to 0.8uW (122 times) when process technology reduces to 180nm.
With the above analysis, 1.8V with 180nm process technology will be implemented
for evaluation of family circuits.
5.2
DESIGN EVALUTION ON FULL ADDERS
All 5 designs are evaluated based on1.8V and 180nm process technology. Their width
settings are calculated based on the logical effort (APPENDIX B). The aim of this
evaluation is to select 2 designs for the implementation on complex design.
35
Legend
Worst
Good
Type:
Process
Voltage
Paverage (uW)
Iaverage (uA)
Prms(uW)
Pmax (uW)
Irms(uA)
Imax(uA)
Delay(ps)
Static CMOS FA DCVSL FA 12T FA NT10FA P10T FA

180nm
1.8V
0.574
0.9616
0.57816 0.4636
0.10515
0.3189
0.5342
0.3212 0.25755 0.05841
49.18
44.537
3.4978
2.7598
1.092
1020
308.96
87.4695 68.6133 31.5401
27.3249
24.743
1.9432
1.5332 606.6701
566.6418
171.6457
48.5942 38.1185 17.5223
35.503
56.288
69.2689 155.36
138.405
Table 5: Simulation Results of 5 Full Adders
Analysis:
The main criterion in selecting the 2 designs is based on low power and high speed.
From Table.5, Static CMOS achieve the fastest speed which fulfilled the criteria of a
high speed design. P10T has the lowest average power consumption. Recalling
section 3.1.5, P10T faces the loss of threshold voltage.
As mentioned in section 3.1.3, 12T full adder faces noise issues due to the low
threshold which also contribute to more current leakage. Though DCVSL full adder
has the highest average power consumption, it met the low speed criteria.
By weighing the pros and cons of DCVSL and 12T full adder and comparing its
results, DCVSL is preferred as it does not face the noise issue which is also critical in
this project.
Therefore, it is concluded that Static CMOS and DCVSL full adder are selected for
complex design implementation.
5.3
COMPLEX CIRCUIT EVALUTION
Static CMOS and DCVSL are applied in the more complex design. Further evaluation
is done to identify the traits of circuit in different variations.
36
In this analysis, leakage current is included in the analysis. When a design is

integrated into more complex designs, the increment of transistors gives a rise to static
power dissipation which may exceed the dynamic power dissipation. Thus
observation has to be made when designing a low power design.
5.3.1
Carry Ripple Adder

Type:
Static CMOS
DCVSL
Process
180nm
Voltage
1.8V
Paverage (uW)
9.3938
17.2216
Iaverage (uA)
5.2193
9.5676
Prms(uW)
248.7885
211.8557
Pmax (uW)
349.0805
174.7515
Irms(uA)
138.2193
117.6976
Imax(uA)
193.9336
97.0841
Standby Dissipation
Pleakage(nW)
3.7367
4.5386
Ileakage (nA)
2.0759
4.1881
Tpd(ns)
2.7985
3.5
Table 6: Static CMOS and DCVSL full adder in Carry Ripple Adder
Analysis:
Static CMOS has the lowest power consumption and fastest delay but it has 2 times
the maximum power occurring than DCVSL.
37
5.3.2
Braun Multiplier
Type:
Process
Voltage
Paverage (uW)
Iaverage (uA)
Pleakage (pW)
Ileakage (pA)
AND GATE
180nm
1.8V
0.232857
0.129365
7.6171
4.2317
Type:
Static CMOS
DCVSL
Process
180nm
Voltage
1.8V
Paverage (uW)
0.8506
0.8548
Iaverage (uA)
0.4726
0.4745
Prms(uW)
110.6801
94.2916
Pmax (uW)
561.7971
561.797
Irms(uA)
64.489
52.5347
Imax(uA)
312.1095
312.1094
Standby Dissipation
Pleakage(nW)
3.8131
4.6547
Ileakage (nA)
2.1184
2.5859
Tpdr(ps)
555.47
555.2
Table 7: Static CMOS and DCVSL full adder in Braun Multiplier
Analysis:
Both designs have the same speed delay and power consumption but static CMOS full
adder has a lower leakage power
Overview:
In the carry ripple adder, static CMOS fulfilled the 2 criteria of high speed and low
power. As observed in Braun multiplier, both designs have the same performance.
With the above analysis, the proposed method will be implemented using static
38
CMOS full adder. As static CMOS has higher maximum power consumption,
observation will be done when proposed method is implemented.
5.3.3
Advanced Analysis (Scaling)
This section performed further analysis to determine the static CMOS and DCVSL
performance. By scaling the voltages of the 2 designs, their delay, average power and
leakage power are measured. These data are implemented into graph to have a visual
view of both circuit performances.
Various voltage supplies are used to record the power consumption and delay.
Voltage Scaling:
1) 3.3V
2) 3.0V
3) 2.5V
4) 2.0V
5) 1.8V
6) 1.5V
16 Bit Carry Ripple Adder (Pavg)
39
16 Bit Carry Ripple Adder (Pleakage)
16 Bit Carry Ripple Adder (Delay)
Figure 32: Comparison of static CMOS and DCVSL in Carry Ripple Adder (Voltage Scaling)
Analysis:
From Fig.32, the 3 graphs showed that Static CMOS perform better than DCVSL in
terms of leakage, average power and speed. Both the leakage and average power
consumption show a great drop when voltages scale down. With current technology,
using higher power supply will lead to a rise in the power consumption. However,
decreasing a voltage supply will cause a rise in the delay. The delay shows a sharp rise
when voltage scales down from 1.8V to 1.5V. This will pose a problem if 1.5V is
applied using 180nm as it may not be able to support the optimization.
40
Figure 33: Comparison of static CMOS and DCVSL in Braun Multiplier (Voltage Scaling)
Analysis:
The delay is not shown in the above analysis as they have the same speed. Both
designs achieved the same average power consumption when voltage scaling drops
below 3V. However, static CMOS perform better in terms of leakage power
consumption.
Overview:
With the above analysis, it can be observed that Static CMOS performed best. The
proposed method will be done on static CMOS.
41
CHAPTER 6. PROPOSED METHOD

With careful consideration, the proposed method will concentrate on voltage
reduction techniques to achieve a low power, high speed and low noise immunity
devices.
The initial step is to find the best PN ratio between the MOSFET followed by width
scaling.
This evaluation is based on
Delay
C LV DD
W
0 C ox
(V DD VTH )
L
Where
=Process Technology (180nm)

CL = Load Capacitance
C ox = Capacitance per unit area of the gate
0 = mobility
Theoretically, decreasing the voltage supply increase the delay. Hence, it is essential
to ensure that when the power consumption is reduced it needs to maintain or reduce
its delay speed. To ensure that the delay is unchanged while voltage scaling is done,
width (W) of PMOS and NMOS are adjusted with the same scaling factor.
42
Flowchart of the proposed method evaluation:

Proposed
Proposed
Method
Method
Ratio
Ratio
Optimization
Optimization
FanOutOf-4
FanOutOf-4
Not Suitable
Measurements
Measurements
Suitable
Selected
Selected Ratio
Ratio
Inverter
Inverter
Implement
No
Not Feasible
Yes
Measurements
Measurements
Troubleshoot
Troubleshoot
Feasible
Implement
Selected
Selected
Width
Width &
&
Voltage
Voltage
Implement
Ripple
Ripple Carry
Carry
Adder
Adder
Ripple
Ripple Carry
Carry
Adder
Adder
Fail to meet
criteria
Fail to meet
criteria
Measurements
Measurements
Measurements
Measurements
Meet criteria
Conclusions
Conclusions
43
6.1
PN Ratio Scaling
The fanout-of-4 is used in determining the best PN ratio as it created an environment

of driving a load. Due to the limitation of MG tools used, it is able to support up to 4
levels for fanout-of-4.
In the design rules, transistor dimension sizing is based on the width and length. The
required minimum sizing of 1 unit is 4 / 2 . As this evaluation is conducted in
180nm technology, the minimum width is set at 0.36um (0.18umx2) and 0.18um
length.
Figure 34: Schematic of Fanoutof-4
As PMOS is slower than NMOS, it requires 2 times the width setting as NMOS to
provide an equal rise delay. By setting PNMOS and NMOS with a ratio of 2 is called
a balanced circuit. This is called an unskewed gate.
44
In this section, the theory of balanced ratio is ignored and evaluation is done to find
the ratio for best optimization. With this new ratio, all the width will follow the new
values regardless of logical effort.
To cater for the optimum results, the PN scaling will evaluate based from LO-skew to
HI-skew gates.
The results are obtained by measuring the rise and fall time (20%-80%) on Device
Under Test (DUT). The ratio with the smallest difference between the rise and fall
time is chosen.
Testing parameter:
Technology=0.18um
Starting width of PMOS: 0.36um
Fixed width of NMOS: 0.36um
Figure 35: Waveform measurement
45
Based on FO-4
DUT
20%
80%
P=0.36
N=0.36
ABS
Ratio
1
1.5
2
2.5
3
3.5
4
Vdd
1.80
1.80
1.80
1.80
1.80
1.80
1.80
fw
1
1
1
1
1
1
1
tpdr (ps) tpdf (ps)

122.0300 77.4890
115.1100 84.8440
111.2000 92.5200
110.4700 101.1400
110.27
109.83
111.32
118.87
112.97
128.13
tdiff (ps)
44.5410
30.2660
18.6800
9.3300
0.4400
7.5500
15.1600
P
0.36
0.54
0.72
0.90
1.08
1.26
1.44
N
0.36
0.36
0.36
0.36
0.36
0.36
0.36
Table 8: Optimize ratio of the FO-4
Figure 36: Optimize ratio of FO-4 (Visual View)
From the above evaluation, the best optimized ratio is 3:1. Thus, P=1.08 and N= 0.36
is used.
Previous
Optimize
2
1
1.08
0.36
Inverter
Pwidth
Nwidth
46
Sum
Pwidth
Nwidth
6
3
1.08
0.36
Carry
Pwidth
4
1.08
Nwidth
2
0.36
Table 9: Optimize width setting
6.2
IMPLEMENTING ON INVERTER
The new width is implemented on an inverter with voltage reduction.
6.2.1 Optimize Ratio on Inverter

The optimization method is catered for 2.5V. With the proposed method, scaling down
of power consumption is done.
VDD
2.5
2.1
1.8
1.5
Fw
1
1
1
1
tp(ps)
42.749
51.774
59.986
69.033
Ileak(pA)
20.2471
15.7406
12.9023
10.4562
Iave(nA)
7.692
4.2971
2.3045
0.916
Pavg(nW)
19.23
9.02391
4.1481
1.374
Table 10: Results of Optimize ratio on different voltages
Figure 37: Delay using optimizing ratio on different voltages
Analysis:
47
Ipeak(uA)
6.8302
5.7415
4.9125
4.0871
The above analysis is done to verify that with the scaling down of voltages, delay
increases. Note that there is also a drop in the average and leakage power
consumption. By implementing this method into carry ripple adder and braun
multiplier, the overall power consumption drop will be more significant.
6.2.2 Scaling Width on Inverter

This section aims to scale down voltage and maintains the same speed delay. As
mentioned, reducing voltages increases the delay, thus it is compensated with a width
increment.
In this section, delay of the rise and fall time is measured.
Parameter Settings of Simulation:
Length=0.18um
Process: 180nm
Width=4.999us
Period: 10us
Delay=1us
With the usage of 2.5V as benchmark, the new width of MOSFET is implemented.
Scaling of width for PMOS and NMOS are done proportionally when voltage
reduces.
VDD
2.5
2.3
2.3
2.3
2.3
2.3
2.1
2.1
2.1
2.1
2.1
2.1
2.1
SW
1
1.5
1.05
1.08
1.07
1.06
1
1.05
1.5
1.8
2
2.3
2.2
Slowest
tp(ps)
42.749
36.837
43.015
42.464
42.675
42.897
51.774
51.147
46.839
44.857
43.791
42.473
42.88
Ileak(pA)
20.2471
18.2321
17.8165
17.7934
17.7999
17.8075
15.7406
15.7041
16.1974
16.9215
17.4836
18.3988
18.0861
Iave(nA)
7.692
8.0965
6.0578
6.1935
6.1482
6.101
4.2971
4.4627
5.9611
6.9666
7.6489
8.6179
8.2898
48
Pavg(nW)
19.23
18.62195
13.93294
14.24505
14.14086
14.0323
9.02391
9.37167
12.51831
14.62986
16.06269
18.09759
17.40858
Ipeak(uA)
6.8302
9.4654
6.605
6.7957
6.7321
6.6643
5.7415
6.032
8.6454
10.387
11.5478
13.2889
12.7085
P
1.08
1.62
1.134
1.1664
1.1556
1.1448
1.08
1.134
1.62
1.944
2.16
2.484
2.376
N
0.36
0.54
0.378
0.3888
0.3852
0.3816
0.36
0.378
0.54
0.648
0.72
0.828
0.792
2.1
2.1
2.1
2.1
1.9
1.9
1.9
1.9
1.9
1.9
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.5
2.15
2.25
2.24
2.23
1.5
2.5
2
2.4
2.39
2.38
1
1.5
2.5
3.5
4.5
5
8
10
1
43.095
42.673
42.714
42.858
47.4
42.328
44.315
42.667
42.702
42.738
59.986
56.358
52.583
50.621
49.434
49.006
47.561
47.125
69.033
17.9324
18.2416
18.2104
18.3988
14.3331
16.9718
15.541
16.6754
16.646
16.6166
12.9023
13.4603
15.9967
18.9638
22.0553
23.6229
33.1557
39.5633
10.4562
8.1242
8.4554
8.4223
8.5212
3.9613
6.1226
5.0448
5.9072
5.8856
5.8641
2.3045
3.1639
4.89
6.6011
8.3029
9.151
14.2118
17.5622
0.916
17.06082
17.75634
17.68683
17.89452
7.52647
11.63294
9.58512
11.22368
11.18264
11.14179
4.1481
5.69502
8.802
11.88198
14.94522
16.4718
25.58124
31.61196
1.374
12.4184
12.9987
12.9407
12.9253
7.8059
13.0405
10.4235
12.5171
12.4648
12.4125
4.9125
7.3922
12.3493
17.3041
22.2569
24.7326
39.605
49.549
4.0871
2.322
2.43
2.4192
2.4084
1.62
2.7
2.16
2.592
2.5812
2.5704
1.08
1.62
2.7
3.78
4.86
5.4
8.64
10.8
1.08
0.774
0.81
0.8064
0.8028
0.54
0.9
0.72
0.864
0.8604
0.8568
0.36
0.54
0.9
1.26
1.62
1.8
2.88
3.6
0.36
Table 11: Voltage and width scaling of proposed method
Analysis:
From the above findings, 2.3V, 2.1V and 1.9V manage to obtain the same delay speed
with different width scaling.
However, 1.8V and 1.5V was not able to achieve same speed when voltage scales
down. It can be explained that 180nm process technology is not optimize for 1.8V.
Thus, 1.9V is the lowest voltage scaling to be achieved.
Selected scaling width and voltage:
Voltage
2.5 (1)
2.3(1.07)
2.1 (2.24)
1.9 (2.38)
Delay
42.749
42.675
42.714
42.738
Avg Power
7.692
6.1482
18.2104
16.6166
Table 12: Scaling width meet requirements
49
Figure 38: Showing the delay of selected scaling
Figure 39: Average power consumption of selected scaling
Summary:
The scaling of width meets the delay speed of the 2.5V benchmark. If an inverter was
to achieve a low power, fast speed criteria, 2.3V of scaling with 1.07 is recommended.
6.3
IMPLEMENTING ON CARRY RIPPLE ADDER
This section applies the theory of proposed method to carry ripple adder. The
simulation setting is done to show only 1 rising transition.
Parameter Settings:
Length=0.18um
Process: 180nm
Width=9.999us
50
Period: 20us
Delay=1us
VDD
2.5
2.3
2.3
2.3
2.1
2.1
1.9
1.9
1.8
SW
1
1
1.07
1.5
2.24
1
1
2.38
1
tp(ps)
1.4208
1.5131
1.5334
1.6289
1.8508
1.6391
1.8238
2.0579
1.941
16-bit
Carry
Ripple
Adder
Ileak(nA)
1.6124
1.4481
1.455
1.5448
1.5991
1.2957
1.1542
1.4767
1.0872
Iave(nA)
65.9655
58.2434
61.9668
85.5494
109.6092
50.5599
43.3505
100.1186
40.0612
Pavg(nW)
164.9138
133.9598
142.5236
196.7636
230.1793
106.1758
82.36595
190.2253
72.11016
Ipeak(UA)
24.9959
24.4641
43.0617
27.1075
23.9187
19.006
15.0966
23.3683
10.196
P
1.08
1.08
1.1556
1.62
2.4192
1.08
1.08
2.5704
1.08
Table 13: Proposed method on Carry Ripple Adder
Analysis:
Voltage
2.5 (1)
2.3 (1.07)
2.1 (2.24)
1.9 (2.38)
Delay (ns)
1.4208
1.5334
1.8508
2.0579
Avg Power(uW)
164.9138
142.52364
230.17932
190.22534
Table 14: Results of proposed method on carry ripple adder
51
N
0.36
0.36
0.3852
0.54
0.8064
0.36
0.36
0.8568
0.36
FAIL
FAIL
FAIL
Figure 40: Delay of proposed method on carry ripple adder
Figure 41: Average power of proposed method on carry ripple adder
The proposed method is applied to the carry ripple adder but it was not able to meet
the delay of the 2.5V benchmark. More analysis on the width scaling is done
(Table.13). A phenomenon of delay increasing with the increment of scaling width
occurs. Fig.41 shows the abnormal rise of delay when scaling width increases.
Scaling benchmark selected fails to achieve the same delay speed as compared with
2.5V.
Troubleshooting is done and discussed in chapter 7.
52
6.4
IMPLEMENTING ON BRAUN MULTIPLER

4- bit Braun ultiplier
VDD
2.5
2.3
2.3
2.1
2.1
1.9
1.9
1.8
SW
1
1
1.07
2.24
1
1
2.38
1
tp(ps)
255.65
273.48
277.78
333.48
297.48
329.11
370.99
348.71
Ileak(nA)
0.7466
0.6874
0.70059
0.8687
0.6306
0.5752
0.8198
0.5471
Iave(nA)
159.7125
133.383
141.8252
236.9107
110.329
91.2288
215.7651
82.8565
Pavg(nW)
399.2813
306.7809
326.198
497.5125
231.6909
173.3347
409.9537
149.1417
Ipeak(UA)
209.6391
192.8078
206.4391
396.3163
175.9559
159.0934
380.7964
150.654
P
1.08
1.08
1.16
2.42
1.08
1.08
2.57
1.08
Table 15: Proposed method on Braun Multiplier
Analysis:
Voltage
Delay (ns)
2.5 (1)
255.65
2.3 (1.07)
277.78
2.1 (2.24)
333.48
1.9 (2.38)
370.99
Avg Power(uW)
399.28125
326.19796
497.51247
409.95369
Table 16: Results of proposed method on Braun Multiplier
Figure 42: Delay of proposed method on Braun Multiplier
53
N
0.36
0.36
0.3852
0.8064
0.36
0.36
0.8568
0.36
FAIL
FAIL
FAIL
Figure 43: Average power of proposed method on Braun Multiplier
The proposed method fails to meet the delay of the 2.5V benchmark. More date were
analyzed (Table.15) and the phenomenon of delay increasing occurs. Fig.42 shows
the abnormal rise of delay when scaling width increases.
Once again, scaling benchmark selected fails to achieve the same delay speed as
compared with 2.5V
6.5
COMPARING DELAY OF 3 CIRCUIT
Visual analysis is done to observe the characteristic of delay occurring in with the
proposed method.
Carry Ripple Adder
54
Figure 44: Comparing Delay characteristic on proposed method
Both carry ripple adder and braun multiplier shows the same trend in increasing delay
when the width increase. However, this increasing trend is abnormal and does not fit
the equation as discussed in Chapter 6.
55
6.6
COMPARING AVERAGE POWER CONSUMPTION

Carry Ripple Adder
Figure 45: Comparing Average Power characteristic on proposed method
All 3 designs showed the same trend of rise and fall power consumption with the
usage of proposed method.
56
CHAPTER 7. PROBLEM FACED

Throughout the course of this project, some problems were encountered. The
proposed method was integrated into complex circuits, delay measurements obtained
does not tally with the results when compared with an inverter.
Verification:
The results of 2.1V of an inverter were extracted to prove the theory of proposed
method. It can be seen that by scaling the MOSFET width, the delay drop and the
average power increase.
Figure 46: Verification the theory of proposed method
Detailed checking of the schematic was conducted and no error was found.
Troubleshooting procedure:
1. Checking of schematic
2. Verifying the RCA/Braun simulation on 180nm, 250nm and 350nm process
technology.
57
3. Using Ganged CMOS method by pairing the input inverter on RCA to obtain a
stronger output.
Not A
Figure 47: Gang CMOS schematic
4. Implementing on FanOut-of- 2, 3 and 4
Figure 48: FanOut-of 2 and 3
58
The above verification still shows an increment in delay in carry ripple adder and
braun multiplier.
Thus, verification was done by an external source at a chip company which uses an
advance process technology of less than 60nm. The same evaluations were carried out
using carry ripple adder and braun multiplier.
The following graphs showed the results obtained from external source:
Average Power of Carry Ripple Adder
Delay of Carry Ripple Adder
Figure 49: Delay and Average of Proposed method on Carry Ripple Adder by external source
Figure 50: Delay and Average of Proposed method on Braun Multiplier by external source
The above verification fulfilled the theory of the proposed method. It matches the
characteristic of the delay in an inverter. As the power supply used is low, the overall
average consumption reduces greatly.
It is suspected that the model file in the MG tools was corrupted or this proposed
method does not support the process technology of 180nm and earlier (since
verification done externally on less than 60nm shows a drop in delay).
59
CHAPTER 8. CONCLUSION
The objective of this project is to propose a method to overcome the limitations of a
chosen CMOS design style.
An intensive background study was carried out and five designs were evaluated. With
the selected design, the proposed method which consisted of obtaining the best PN
ratio and width scaling was executed.
The proposed method succeeded in showing a trend in power reduction and
maintaining the high speed when implemented in an inverter.
Some problems were encountered during the course of evaluation. Verifications
showed that the proposed method succeeded when applied in complex circuit of lower
process technology.
Majority of the project objective has been achieved.
CHAPTER 9. RCOMMENDATION
There are areas for improvement. The evaluation can be done by evaluating more
circuit families and evaluating on a process with smaller technologies. The followings
recommendations are:
- Evaluating dynamic families with footed and non-footed designs
- Testing out the proposed method using smaller process technology
- Test and improve on the noise immunity
- Testing on more complex circuits
60
CHAPTER 10. REFLECTION

Throughout the process of this project, I have gain knowledge of understanding how
the ICs are designed at the lowest hierarchy. I learnt that there are many techniques to
be applied in designing a circuit and why researchers are constantly improving and
create new design to meet the changing process technology.
Due to my work environment and contact with VLSI module, I am familiar with the
usage of software tools. However, my work only exposed me to draw schematics from
the circuit topology thus this project is a new learning experience.
Due to my familiarity of the MG tools, it has actually leads me to committing careless
mistake. In the starting phase of the project, careless mistakes were done during
schematic drawing and luckily with the tutor guidance, the mistakes were found and
rectified. I realised that every design is critical that with any wrong connections,
results varies and previous evaluation results will come to a waste. Thus, having
ample knowledge of how the circuit performs can aid me in identifying abnormal
results.
61
CHAPTER 11. REFERENCES

[1]
Al-Sheraidah, A., Jiang, Y., Wang, Y., & Sha, E. (2001). A Novel Low Power
Multiplexer-Based Full Adder. ECCTD01 - European Conference on Circuit Theory
and Design. Espoo, Finland.
[2]
Arns, R. G. (1998). The other transistor: early history of the metal-oxidesemiconducor field-effect transistor. Engineering Science and Education Journal 7
(5) .
[3]
Brinkman, W. F., Haggan, D. E., & Troutman, W. W. (1997). A History of the
Invention of the Transistor and Where It Will Lead Us. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 32, NO. 12, .
[4]
Brinkman, W., Haggan, D., & Troutman, W. (1997). A history of the invention of the
transistor and where it will lead us. Solid-State Circuits, IEEE Journal of Volume 32,
Issue 12 .
[5]
Chandrakasan, A. P., Sheng, S., & Robert W. Brodersen. (1992). Low Power CMOS
Digital Design. IEEE Journal of Solid -State Circuits, Vol 27. No.4 .
[6]
Ding, L., & Mazumder, P. (2004). Noise-Tolerant Quantum MOS Circuits Using
Resonant Tunneling Devices. IEEE TRANSACTIONS ON NANOTECHNOLOGY,
VOL. 3, NO. 1 .
[7]
Ding, L., & Mazumder, P. (2004). On Circuit Techniques to Improve Noise Immunity
of CMOS Dynamic Logic. IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 9 .
[8]
Dongyan, H., Ming, Z., & Wei, Z. (n.d.). Design Methodology of CMOS Low Power.
62
[9]
IC Knowledge - History of the Integrated Circuit - 1960s. (n.d.). Retrieved September
2009, from http://www.icknowledge.com/history/1960s.html
[10]
Javier Castro, A. J., & Vesterbacka, M. Geometry optimization in basic CMOS cells
for improved power; leakage, and noise performance. International Conference on
Advances in Electronics and Micro-electronics.
[11]
Kang, S.-M., & Leblebici, Y. (2005). CMOS Digital Integrated Circuit (Analysis and
Design). Singapore: McGraw-Hill.
[12]
Kawa, J. (2008). Low Power and Power Management for CMOSAn EDA
Perspective. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1 .
[13]
Lee, P.-M., & Chen, W.-P. (n.d.). 12-T full adders using deep sub-micron CMOS
process.
[14]
Loeckx, J., & Gielen, G. (2008). Very fast methodology for the simulation of CMOS
combinatorial circuits including noise. Electromagnetic Compatibility - EMC Europe,
2008 International Symposium , 1-4.
[15]
Loy, L.-Y., Zhang, W., Kong, Z.-H., Goh*, W.-L., & Yeo, K.-S. (n.d.). BodyBootstrapped-Buffer Circuit for CMOS Static Power Reduction.
[16]
Lury, S., Xu, J., & Zaslavsky, A. Future Trends in Microelectronics- The Nano
Millennium. 2002.
[17]
MOSFET - Wikipedia, the free encyclopedia. (n.d.). Retrieved October 2009, from
Wikipedia, the free encyclopedia: http://en.wikipedia.org/wiki/MOSFET
[18]
Pant, P., De, V. K., & Abhijit Chatterjee. (1998). IEEE TRANSACTIONS ON VERY
LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 4 .
63
[19]
Rabaey, J. M., & Pedram, M. (1996). Low Power Design Methodologies. United
States of America: Kluwer Academic Publishers.
[20]
Raja, T., Agrawal, V. D., & Bushnell, M. L. (2004). CMOS Circuit Design for
Minimum Dynamic Power and highest speed. Proceedings of the 17th International
Conference on VLSI Design (VLSID04).
[21]
Srivastava, A., Kachru, T., & Sylvester, D. (2007). IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL.
26, NO. 1 .
[22]
Subthreshold Conduction - Wikipedia, the free encyclopedia. (n.d.). Retrieved October
2009, from Wikipedia, the free encyclopedia:
http://en.wikipedia.org/wiki/Subthreshold_leakage
[23]
Transistor - Wikipedia, the free encyclopedia. (n.d.). Retrieved February 2009, from
http://en.wikipedia.org/wiki/Transistor
[24]
Vasefi, F., & Abid, Z. (2005). LOW POWER N-BIT ADDERS AND MULTIPLIER
USING LOWEST-NUMBER-OF-TRANSISTOR 1-BIT ADDERS.
[25]
Wen, M.-C., Wang, S.-J., & Lin, Y.-N. (2005). Low-power parallel multiplier with
column bypassing. ELECTRONICS LETTERS Vol. 41 No. 10 .
[26]
WESTE, N. H., & HARRIS, D. (2005). CMOS VLSI DESIGN. Pearson Education.
Wolf, W. (2009). Modern VLSI Design (IP-Based Design). United States of America:
Pearson Education.
64
APPENDIX A: FULL ADDER TABULATION

Logic Table and Equation of Full Adder
For this design, there are 3 inputs which total up to 8 bits.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
Carry
0
0
0
1
0
1
1
1
Based on the circuit, the equation of the adder is:

Sum abc abc abc abc
Sum abc abc abc abc abc abc abc abc
Carry ab (a b) c
Carry ab (a b) c ab ( a b) c
65
APPENDIX B: LOGICAL EFFORT CACULATION

Due to the higher mobility of electrons in NMOS, NMOS transistor is faster than
PMOS by 2~3 times. It is important to set the sizing of width in PMOS to be at least 2
times bigger than NMOS so as to achieve the same transition timing to minimize
power dissipation. This can be done by using a resistor of a lower value. When both
transistors achieve the same ratio, this is a well-balanced design.
The process technology selected will be in 0.18um technology. Thus, the length of
1
PMOS and NMOS are set to L=0.18. Note that R W , therefore n 2 p

Inverter:
The inverter is commonly used in all designs as it can invert the input or output value
for further evaluation.
Wn :
Width of nMOS to achieve R, since there are only 1 nMOS.

R
Wn
R
1 W n 1
R
Wn
Wp :
Wp 2
a
Width of pMOS to achieve R to balance the ratio with Wn .

Thus,
2R
W
p
R,
2R
2 W p 2
R
Wn 1
Wp
Carry:
Setting the width of the MOS is split into 2 sections. The left hand side of the
carry
VDD
circuit is disscussed first.
b Wp 4
Left hand side of carry circuit:

There are 2 nMOS connected in series.
a Wp 4
Wn :
Width of nMOS to achieve R:
a Wn 2
66
b Wn 2
R
R
Wn Wn
2R
2 Wn 2
R
Wn
Wp :
Width of pMOS to achieve R to balance the ratio with Wn .

Thus,
2R 2R
R,
W
p
p
4R
4 W p 4
R
Wp
Right hand side of carry circuit:

In a situation where there is parallel MOS, it is assumed that one side of the MOS is
turn off. Thus, the circuit for width calculation becomes:
VDD
VDD
Wp 4 b
Wp 4 c
Wn 2 c
Wn 2 b
VDD
VDD
After the assumption, R.H.S of the carry circuit is same as the L.H.S. Thus, it can be
concluded that
Wn 2
W
b
Sum:
Setting the width of the MOS is spilt into 2 sections. Assuming one of the MOS is
turn on for MOS in parallel. The L.H.S and R.H.S of the sum circuit has the same
a
configuration.
b
a
67
b
c
Wp 6
Wp 6
Wp 6
Wp 6
Wp 6
Wp 6
Wn 3
Wn 3
Wn 3
Wn 3
Wn 3
Wn 3
L.H.S
R.H.S
There are 3 nMOS connected in series.

Wn :
Width of nMOS to achieve R:

R
R
R
Wn Wn Wn
3R
3
R
Wn
Wn 3
Wp :
Width of pMOS to achieve R to balance the ratio with Wn . Thus,

2R 2R 2R
R,
W
W
p
p
p
6R
6 W p 6
R
Wp
68
APPENDIX C: STATIC CMOS SCHEMATIC & RESULTS
Static CMOS Full adder schematic
Static CMOS in 16 bit Carry Adder
69
Static CMOS in 4 Bit Braun Multiplier
Static CMOS Logic Verification

70
Static CMOS in Carry Ripple Adder (Current Verification)
71
APPENDIX D: DCVSL SCHEMATIC & RESULTS
DCVSL Full Adder schematic
72
DCVSL in 16 Bit Carry Ripple Adder
DCVSL in 4 Bit Braun Multiplier

73
DCVSL Braun Multiplier (Logic Verification)
DCVSL Braun Multiplier (Current Verification)
74
APPENDIX E: 12T SCHEMATIC & RESULTS
Schematic of 12T full adder
12T carryout waveform

75
12T Sum waveform with threshold loss
76
APPENDIX F: N10T SCHEMATIC & RESULTS
N10T Full Adder schematic
77
N10T Sum waveform with threshold loss
N10T output waveform

78
APPENDIX G: P10T SCHEMATIC & RESULTS
P10 Full Adder Schematic
79
P10T sum voltage swing
P10T output waveform

80

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