DOC/LP/01/28.02.

02
LESSON PLAN

LP AP9212
LP Rev. No: 00

UNIT I

Sub Code & Name: AP9212 Advanced Digital System Design

Date: 07/09/12

Unit : I

Page 01 of 06

Branch : ME-MAE

Semester: I

SEQUENTIAL CIRCUIT DESIGN

Analysis of clocked synchronous sequential circuits and modeling- State diagram, state
table, state table assignment and reduction-Design of synchronous sequential circuitsdesign of iterative circuits-ASM chart and realization using ASM.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

1.

Analysis of clocked sequential circuits- Introduction

50m

BB

2.

Design of an Sequential parity checker, Analysis of Moore

and Mealy sequential circuit by signal tracing and timing
charts

50m

BB

3.

Method of constructing state table and state graphs for

Moore and Mealy machines

50m

BB

4.

General Models for a clocked Mealy and Moore sequential

circuits.

50m

BB

5.

Design of a sequence detector for Mealy and Moore

machines

50m

BB

6.

Reduction of state table using state assignment

50m

BB

7.

Determination of state equivalence and circuit equivalence

using an implication table

50m

BB

8.

Incompletely Specified State tables and derivation of flipflop input equations

50m

BB

9.

Guidelines for state assignments, one hot state assignment

50m

BB

10.

Design of itrative circuits, Design of a comparator

50m

BB

11.

State Machine (SM) Charts- Drivation and realization of

SM charts

50m

BB

DOC/LP/01/28.02.02
LESSON PLAN

LP AP9212
LP Rev. No: 00

UNIT II

Sub Code & Name: AP9212 Advanced Digital System Design

Date: 07/09/12

Unit : II

Page 02 of 06

Branch : ME-MAE

Semester: I

ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

Analysis of asynchronous sequential circuit flow table reduction-races-state

assignment-transition table and problems in transition table- design of asynchronous
sequential circuit-Static, dynamic and essential hazards data synchronizers mixed
operating mode asynchronous circuits designing vending machine controller.

Session
No.

Topics to be covered

Time

Ref

Teaching
Method

12.

Analysis of Asynchronous sequential circuit - Design of

Fundamental mode sequential circuit - Primitive state
table, state table reduction and state assignment

50m

1,2

BB

13.

Design of Pulse mode sequential circuit- Primitive state

table, state table reduction and state assignment

50m

1,2

BB

14.

Problems in Asynchronous sequential circuits Cycles,

Critical race and Non- Critical race

50m

1,2

BB

15.

Hazards- Static, Dynamic and Essential Hazards

50m

1,2

BB

16.

Design of Hazard free switching circuits- Static Hazard

and Essential Hazard elimination

50m

1,2

BB

17.

Problems on Hazard free circuit Static and Essential

Hazard

50m

1,2

BB

18.

Working principle of Data synchronizer

50m

1,2

BB

19.

Design of mixed operating mode asynchronous circuit

50m

1,2

BB

20.

Design of Vending machine controller- Description/

Specification, FSM design steps, State diagram and state
table

50m

1,2

BB

CAT I

75m

DOC/LP/01/28.02.02
LESSON PLAN

LP AP9212
LP Rev. No: 00

Sub Code & Name: AP9212 Advanced Digital System Design

Unit : III
UNIT III

Branch : ME-MAE

Date: 07/09/12

Semester: I Page 03 of 06

FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS

Fault table method-path sensitization method Boolean difference method-D algorithm

-Tolerance techniques The compact algorithm Fault in PLA Test generation-DFT
schemes Built in self test.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

21.

Fault Models- Stuck-at fault, Bridging fault, stuck-open fault

and Temporary faults

50m

BB

22.

Fault Diagnosis of Digital systems- Test generation for

combinational logic circuits- one dimensional path
sensitization

50m

BB

23.

Boolean Difference method

50m

BB

24.

D-Algorithm- Singular cover, Propagation D-cubes, Primitive

D-cube of a fault, D- intersection

50m

BB

25.

Tolerance techniques- Static redundancy, Dynamic redundancy,

and Hybrid redundancy

50m

BB

26.

Self- purging redundancy, Sift-out modular redundancy

50m

BB

27.

Fault in PLA and totally self-checking PLA design

50m

BB

28.

Test generation- Controllability and observability, Design of

testable combinational logic circuits

50m

BB

29.

Design of testable sequential circuits

50m

BB

30.

Built in self test- Built-in Digital circuit Observer (BIDCO),

Built in test for VLSI chips

50m

BB

DOC/LP/01/28.02.02
LESSON PLAN

LP AP9212
LP Rev. No: 00

Sub Code & Name: AP9212 Advanced Digital System Design

Unit : IV

Branch : ME-MAE

Date: 07/09/12

Semester: I Page 04 of 06

UNITIV SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES

Programming logic device families Designing a synchronous sequential circuit using

PLA/PAL Realization of finite state machine using PLD FPGA Xilinx FPGAXilinx 4000.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

31.

Programmable Logic Devices (PLD)- Notations for

PLD, Design methodology using PLDs

50m

BB

32.

Design of sequential PLA devices

50m

BB

33.

Design of sequential PAL devices- 4-bit binary

counter- state table, K-map and PAL diagram

50m

BB

34.

8-bit Parallel Cyclic Redundancy Check (CRC)

generator- Block diagram and PAL diagram

50m

BB

35.

Field- Programmable Gate Array (FPGA)- PLS 151,

PLS103

50m

BB

36.

Asynchronous State Machine Design

50m

BB

37.

State Machine Design- Program for the logic blocks,

K maps, implementation of the state table

50m

BB

38.

Xilinx FPGA and Xilinx 4000 block diagram

explanation

50m

BB

CAT II

180m

DOC/LP/01/28.02.02
LESSON PLAN

LP AP9212
LP Rev. No: 00

UNIT V

Sub Code & Name: AP9212 Advanced Digital System Design

Date: 07/09/12

Unit : V

Page 05 of 06

Branch : ME-MAE

Semester: I

SYSTEM DESIGN USING VHDL

VHDL operators Arrays concurrent and sequential statements packages- Data flow
Behavioral structural modeling compilation and simulation of VHDL code Test
bench - Realization of combinational and sequential circuits using HDL Registers
counters sequential machine serial adder Multiplier- Divider Design of simple
microprocessor.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

39.

Introduction to VHDL, Arrays and VHDL operators

50m

5,6

BB

40.

Concurrent ,Sequential statements and PackagesDeclaration, Deferred constants, Package body

50m

5,6

BB

41.

Introduction to write a program in Data flow,

Behavioral and structural model

50m

5,6

BB

42.

Compilation and simulation of VHDL code , Test

bench- Stimulus only, Full test bench, Simulator
specific, Hybrid and Fast test bench

50m

43.

Structural VHDL code- Full Adder, Multiplexer,

Demultiplexer, Encoder and Decoder

50m

5,6

BB

44.

Behavioral and Dataflow VHDL code- JK, T, D flipflop

50m

5,6

BB

45.

Design of Shift registers SISO, SIPO, PISO and

PIPO using VHDL

50m

5,6

BB

46.

Design of Counters and Serial adder using VHDL

50m

47.

Design of Multiplier- Booth, Modified Booth and

Divider using VHDL

50m

48.

Design of Microprocessor with simple arithmetic

operation using VHDL

50m

CAT III

75m

5,6

5,6
5,6
5,6
-

BB

BB
BB
BB
-

DOC/LP/01/28.02.02
LESSON PLAN

LP AP9212
LP Rev. No: 00

Sub Code & Name: AP9212 Advanced Digital System Design

Branch : ME-MAE

Semester: I

Date: 07/09/12
Page 06 of 06

Course Delivery Plan:

1

Week

10

11

12

13

I II I II I II I II I II I II I II I II I II I II I II I II
I
1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 5 5 5

Units

CAT I
CAT II

CAT III

REFERENCES
1
2
3
4
5
6

Charles H.Roth Jr Fundamentals of Logic Design Thomson Learning 2004

Nripendra N Biswas Logic Design Theory Prentice Hall of India,2001
Parag K.Lala Fault Tolerant and Fault Testable Hardware Design B S
Publications,2002
Parag K.Lala Digital system Design using PLD B S Publications,2003
Charles H Roth Jr.Digital System Design using VHDL Thomson learning, 2004
Douglas L.Perry VHDL programming by Example Tata McGraw.Hill - 2006
Prepared by

Approved by

Signature
Name

M.Athappan

Dr.S.Ganesh Vaidyanathan

Designation

Assistant Professor/EC

HOD/EC

Date

07-09-2012

07-09-2012