Tips & Tricks

How to Perform the Four Routing Stages in IC Compiler

Audience: Design engineers with limited or no prior-knowledge of place and route tools and
processes.
Overview: The purpose of this paper is to explain the four stages IC Compiler (ICC) goes through
to route a design after the placement is done.
When performing physical design, routing is the step where physical
connections are made in the entire place and route process. Until routing
is done, the timing numbers from the layout are based on virtual routes.
These timing reports can be overly optimistic in cases where there are large
congestion hot-spots.

Global
Track Assign
Detail
Search and Repair

The core command route_opt instructs ICC to perform both optimization

and routing. However, the results of the automated approach might not
Figure 1 Routing stages
be suitable for all design sizes and styles. Knowing details of the routing
process enables the engineer to optimize each stage and obtain the desired routing results.
IC Complier has 4 Routing Stages:
Global Route (GR), Track Assign (TA), Detail Route (DR) and Search & Repair (S&R).
The 1st stage is Global Route (GR): GR uses the concept of an
imaginary cell called a G-cell. By definition, a G-cell is a square
whose side is equal to the height of a standard cell library. It has
tracks defined for all of the metals layers from the technology file
following the respective metal-pitch rules. During GR, ICC assigns
nets one G-cell at a time. The G-cell itself is shifted to the next
location such that at the end of GR, every part of the core area is
covered by a G-cell once. This results in the assignment of nets to
appropriate G-cells. Though GR assigns nets to the G-cells, it does
Figure 2 Global Routing (GR)
not assign a net to a specific track within the G-cell. Even though
the nets can be queried to what metal layer it is in, there is no width
associated with the net at the GR stage. Hence these are not nets in the true sense. An example of
how the design will look after GR is done is shown in Figure 2.
The 2nd stage of routing is Track Assign (TA): TA assigns
nets to appropriate tracks within the G-cell. TA tries to make the wires
as straight as possible and in the process might alter the assignments
made in the GR stage. Unlike GA, which performs track assignment
only within the G-cell boundary, TA analyzes the nets crossing over
different G-cells. Once TA is complete, nets can be queried to obtain
layer and width details of the nets. Since the nets now have widths
associated with them, performing SI analysis at this point will provide
accurate results. An example of how the design will look after TA is
done is shown in Figure 3.

Routing
optimized
from
figure 2

Figure 3 Track Assign

The 3rd stage of routing is Detail Route (DR): DR uses a rectangular virtual box called Switch
Box (S-box) that overlaps multiple G-cells. DR moves from one S-box to another by fixing as many
DRC violations as possible within the S-box.
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Tips & Tricks

Virtual S-box

Next location

Last location

Next location

Figure 4 Virtual S-box used to locate and fix DRC violations

DR runs two loops, which is evident from the log file which reports
total violations twice after parsing the whole chip. Because DR looks
for violations within the S-box, it will try to fix only those violations.
If the DRC violations span across multiple S-boxes, DR may not be
able to fix them. An example of violations that can be fixed by DR is
shown in Figure 5.
4th stage in routing is Search & Repair (S&R): Similar to DR,
S&R also uses the concept of a virtual S-box to select portions of
the design to work on. The difference in S&R is that the S-box size
increases as it progressively scans the design. Therefore, it can
detect and fix the DRC violations that were not seen by DR.

Virtual S-box

S-box increased

S-box increased further

N otch
Sp acing

N otch
Sp acing
Thin& Fa t
Sp acing
Min
Sp acing

Figure 5 Violations fixed in DR

S-box = Chip size

Figure 6 Search & Repair

As seen in Figure 6, as the number of loops increase, ICC increases the size of the S-box.
Depending on the number of physical DRC violations in the design, more loops may be
necessary to fix all of them. DR and S&R can only detect gate-level DRC violations but not the
transistor-level violations. Thus, a sign-off DRC checker like Hercules is required to ensure a
DRC clean design.
For very simple designs that dont have lots of congestion hot-spots, it is possible to have a
design that is free from both timing and DRC violations after search and repair. However, for
complex designs, ICC provides control options to implement a DRC clean routing.
Where do I get more information?
This paper is an excerpt from the training on IC Compiler. For more details on the topics
covered the training and schedule please visit us on the web at
http://www.synopsys.com/support/customered/customer_edu.html
Extensive documentation is available via www.solvnet.com
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2007 Synopsys, Inc. 8/07.VR.07-15588