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Dinesh Sharma
Microelectronics Group, EE Department
IIT Bombay, Mumbai
A simple model
1.4
Vg = 3.5
1.2
1.0
3.0
0.8
0.6
2.5
0.4
2.0
0.2
0.0 0.5
1.5
1.0
1.0 1.5 2.0 2.5 3.0 3.5
Drain Voltage (V)
4.0 4.5
Ids = K
(Vgs VT )2
2
1.4 1.6
0.0
0.2
0.4
0.0
1.0
2.0
3.0
4.0
Drain Voltage (V)
5.0
and Idss
2(V
V
)
gs
T
1
VE 1 +
VE
Vgs VT
(Vgs VT ) 1
2VE
1 2
K (Vgs VT )Vdss Vdss
2
1 2
K (Vgs VT )Vds Vds
2
V + VE
Idss d
Vdss + VE
CMOS Inverter
The simplest of CMOS logic structure is the inverter.
Vdd
Vi
Vo
Static Characteristics
VOH
VOL
V
iL
iH
VOL
V
iL
iH
VOL
V
iL
iH
Therefore,
Id
1
Vo ) (Vdd Vo )2
2
Kn
(Vi VTn )2
2
If Kn = Kp ; ( = 1),
q
Vo = (Vi + VTp ) + (Vdd VTn VTp )(Vdd 2Vi + VTn VTp )
for Vi
Vi =
1+
Vdd
Vi
Vo
VoH
Output Voltage
2.5
2.0
1.5
V +V
Tn Tp
1.0
0.5
VoL
0.0
0.0
0.5
1.0
1.5
2.0
ViL
ViH
Input Voltage
2.5
3.0
Vi VTn Vo Vi + VTp
when
Vi =
Vdd +
VTn VTp
1+
exactly,
Kp
(V Vi VTp )2
2 dd
1 2
= Kn (Vi VTn )Vo Vo
2
(Vdd Vi VTp )2
1 2
Vo (Vi VTn )Vo +
=0
2
2
This has solutions
Vo = (Vi VTn )
(Vi VTn )2
(Vdd Vi VTp )2
VOL
V
iL
iH
Noise Margins
For the high level, we require that the output of one stage
should still be interpreted as high at the input of the next
gate even when pulled down a little due to noise.
Logic Levels
The region to the left of ViL and to the right of ViH has
o
| V
Vi | < 1, and is suitable for digital operation.
Vo
Vi
is
Vdd
Vi
Vo
Vo
Vi
Vo
= 1 = 1
Vi
This gives
ViL =
VoH
VoL =
Dynamic Characteristics
Rise time
Vdd
ViL
Idp = C
Vo
so,
dVo
dt
dt
dVo
=
C
Idp
VoH
dVo
Idp
rise
=
C
VoH
dVo
Idp
ViL +VTp
dVo
Kp
2 (Vdd
0
VoH
ViL +VTp
Kp (Vdd
ViL VTp )2
dVo
ViL VTp )(Vdd Vo ) 21 (Vdd Vo )2
rise =
+
2C(ViL + VTp )
Kp (Vdd ViL VTp )2
Vdd + VoH 2ViL 2VTp
C
ln
Kp (Vdd ViL VTp )
Vdd VoH
Fall Time
Vo
Vi H
dVo
dt
Separating variables and integrating from the initial voltage
(= Vdd ) to some terminal voltage VoL gives
Idn = C
fall
=
C
voL
Vdd
dVo
Idn
Fall time
fall
=
C
voL
Vdd
dVo
Idn
=
=
Vi VTn
Vdd
Vdd
Vi VTn
Vi VTn
VoL
dVo
Idn
VoL
Vi VTn
dVo
Kn
2
2 (Vi VTn )
dVo
Idn
dVo
Kn [(Vi VTn )Vo 21 Vo2
Fall time
V Vi + VTn
2(Vi VTn ) VoL
fall
1
= Kdd
ln
+
n
2
C
K
(V
V
)
VoL
n
i
Tn
2 (Vi VTn )
The first term represents the time taken to discharge at
constant current in the saturation regime, whereas the second
term is the quasi-resistive discharge in the linear regime.
ViL VoL =
D
C
E
Out
CMOS summary
Vdd
Vi
Vo