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648
Boost Cell
1
Output DC
Bus
Voltage Sensor
Boost Cell
2
Boost Cell
3
Boost Cell
4
Output
Capacitor
Baterry
Charger
Boost Cell
5
Input
Battery
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KSENSOR
s + Z
s
s=
2 z 1
9.8242 9.8221 z
1 z
(1)
TS z +1
iin =
vO
vin
(2)
2 L vO vin
Where: vo is the output voltage, vin is the input voltage, L
is the boost inductance, d is the duty cycle, and TS is the
switching period.
Basically, the right side of (2) is kept constant through the
variation of duty cycle along the AC line period when the
converter is operating as PFCR, compensating the amplitude
changes of input voltage.
Therefore, the main disadvantages related to PFCR boost
converter operating in DCM when the static conversion gain
is low near the unity, namely no compliance of input current
harmonic content with IEC 61000-3-4 due to significant
increase of low order components amplitude, are eliminated.
650
V. EXPERIMENTAL RESULTS
A low power prototype rated at 15 kW was developed in
laboratory in order to verify the feasibility of the proposed
converter for the development of nominal rate application at
150 kW. It should be noticed that the experimental results for
this prototype were obtained using loads with predominant
resistive characteristic.
Initially, two digital control strategies were evaluated for a
power rate around 5 kW, considering the compliance with
input current restrictions imposed by IEC 61000-3-4
standards and the required low static voltage conversion gain
near unity.
The input current and voltage waveforms for the proposed
PFC voltage rectifier considering only the regular PWM
modulation and power rate around 5 kW are shown in Fig. 7.
It can be observed that the input current waveform is in
phase with the input voltage waveform and the discontinuity
is eliminated due to interleaving technique.
Although the experimental power factor measured is near
unity (0.964), due to the low static voltage conversion gain
value the THD of input current was high (26.35%), and as
expected the harmonic content in third order components
exceeds the limit allowed by the IEC 61000-3-4, as shown in
Fig. 8.
Fig. 7. Input current and voltage for the proposed PFC boost
interleaved rectifier considering regular PWM modulation, during
one AC line period (Current Scale: 10A/div, Voltage Scale: 200
V/div, Time Scale: 2 ms/div).
800
600
400
200
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.3
0.35
0.4
0.45
0.5
VVin-avg
in-avg
800
600
400
200
0
0
0.05
0.1
0.15
0.2
0.25
VX(t)=V
-V (t)
VX(t) =
Vin-avg
in-avg in - Vin(t)
600
400
11 13 15 17 19 21 23 25
Harmonic Order (n)
200
0
0
40.0%
35.0%
30.0%
25.0%
20.0%
15.0%
10.0%
5.0%
0.0%
0.05
0.1
0.15
0.2
0.25
Time [seconds]
0.3
0.35
0.4
0.45
0.5
651
Fig. 11. Input current THD and third order component as a function
of output power.
Fig. 9. Input current and voltage for the proposed PFC interleaved
rectifier considering current correction PWM modulation, during
one AC line period (Current Scale: 10A/div, Voltage Scale: 200
V/div, Time Scale: 2ms/div).
Harmonic Limits IEC 61000-3-4
25.0%
20.0%
15.0%
10.0%
5.0%
0.0%
11 13 15 17 19 21 23 25
Harmonic Order (n)
Fig. 10. Harmonic current amplitudes from the proposed PFC boost
interleaved rectifier considering current correction PWM
modulation.
Fig. 13. Output voltage (AC mode) and input current waveforms
during transient process related to load step from no-load to 6 kW
(Current Scale: 10A/div, Voltage Scale: 20 V/div, Time Scale:
50ms/div).
Fig. 14. Output voltage (AC mode) and input current waveforms
during transient process related to load step from 6 kW to no-load
(Current Scale: 10A/div, Voltage Scale: 10 V/div, Time Scale:
20ms/div).
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653
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