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MODULE
+
GATE
Yogesh S. Chauhan
Department of Electrical Engineering
IIT Kanpur
Email: chauhan@iitk.ac.in
Office: WL125, Phone: 7244
CIRCUIT
Vin
Vout
G
S
n+
DEVICE
D
n+
Y. S. Chauhan, IITK
Switch
vi
Normal switch
Gate oxide
W
Polysilicon
Gate
Source
n+
Drain
n+
L
Field-Oxide
(SiO2)
Inverted switch
ON (Signal applied) = High resistance
OFF = Low resistance
p substrate
p+ stopper
Bulk (Body)
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Voltage Swing
Vswing= VOH-VOL
1
RL
RL
RL
RSL
RSH
SimplestInverter
Y. S. Chauhan, IITK
Y. S. Chauhan, IITK
Performance Delay
/
V DD
V DD
RL
CL discharging to VOL.
RL
V out
Req
R SH
Propagation Delay
0.69
CL charging to VOH.
(a) Low-to-high
Vin goes from VDD to ground.
2
Asymmetric delays are undesirable.
To solve this (asymmetric delays),
CL
0.69
1
1
(b) High-to-low
Vin goes
Y. S. Chauhan, IITK
V out
R SL
0.69
0.69
CL
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Power
NMOS Inverter
MOSFET can be operated as a switch.
and
and
VOH=VDD
NMOS Inverter
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NMOS Inverter
1,
Where
2
11
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NMOS Inverter
NMOS Inverter
2
Assuming v0 is small, ignore v02
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NMOS Inverter
To place VM at VDD/2,
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NMOS Inverter
Req=(Rdis(0%) + Rdis(50%))/2
and
To determine RL, use
kn = 300 A V2 and W/L = 1.5
Average v0,
RL=25k
=121W
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Key observations
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tpLH>> tpHL
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VOH = VDD VT
Q2 is always in saturation
1
2
As vI exceeds VT1, Q1 operates in saturation,
1
2
Using VT1=VT2=VT and equating,
1
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Key observations
Noise margins are much lower than the ideal values of VDD/2.
=85.7W
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Improvements-1
Depletion load NMOS Inverter
Key observations
Like the resistively-loaded MOS inverter, the NMOSloaded inverter dissipates a large amount of static power.
Advantages
VOH=VDD
VT2=0V
Disadvantages
Body effect
Others similar to NMOS
load
DepletionloadNMOSInverter
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Improvements-2
Pseudo-NMOS Inverter
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Pseudo-NMOS Inverter
Ratio r
1
1
2
3
1
1
1
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1
1
>0
1
1
2
3
Designparameter=r
Ratioed Logic
tpLH isr timeslargerthantpHL
VOL0
Standbypower
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CMOS Inverter
N Well
Design Metrics:
V DD
V in
VDD
Cost=Complexity and
area
Integrity and
robustness Static (or
steady-state) behavior
Performance
Dynamic (or transient)
response
Energy efficiency
Energy and power
consumption
V out
CL
Y. S. Chauhan, IITK
Reference:Rabaey book
In
Vin = 0
Out
Metal 1
Polysilicon
NMOS
GND
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VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Vin = V DD
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Out
CMOS Properties
Rp
Rn
Contacts
NMOS
Vout = 0
In
29
VDD
Vout = 1
PMOS
PMOS
CMOS Inverter:
Steady State Response
VDD
VDD
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Logic levels not dependent upon the relative device sizes transistors
can be minimum size ratioless
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X 10-4
2.5
VGS = 2.5V
VDS (V)
-2
-1
0
0
VGS = 2.0V
1.5
1
VGS = 1.5V
0.5
VGS = 1.0V
VGS = -1.0V
-0.2
VGS = -1.5V
-0.4
-0.6
VGS = -2.0V
-0.8
0
0.5
1.5
VDS (V)
2.5
VGS = -2.5V
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-1 X 10-4
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CMOS
Inverter Load Lines
CurrentthroughNMOSandPMOSaresame.
PMOS
IDn
2.5
NMOS
X 10-4
Vin = 2.5V
Vin = 0V
2
Vin = 0.5V1.5
Vin = 2.0V
Vout
Vin = 0
Vin = 0
Vin = 1.5
Vin = 1.5
Vin = 1.0V 1
Vin = 2V
0.5
Vin = 1V
Vin = 1.5V
Vin = 0.5V
Vin = 1.0V
Vin = 1.5V
Vin = 2.0V
VGSp = -1
VGSp = -2.5
35
Vin = 0.5V
Vin = 2.5V 0
Vin = 1.5V
0.5
1.5
Vout (V)
Y. S. Chauhan, IITK
2.5 Vin = 0V
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
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NMOS sat
PMOS res
Vout (V)
PMOS
1.5
In
NMOS sat
PMOS sat
NMOS
NMOS res
PMOS sat
NMOS res
PMOS off
0
0
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CMOS Inverter:
Switch Model of Dynamic Behavior
VDD
Vout
CL
Rn
1.5
Vin (V)
2.5
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Rp
Vout
0.5
VDD
Vin = 0
Out
1
0.5
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CL
VDD
NMOS off
PMOS res
2.5
PMOS
Out
Vin = V DD
NMOS
and/orR
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1
Switching threshold set by the ratio r, which compares the
relative driving strengths of the PMOS and NMOS transistors
Switching Threshold
(short channel)
knVDSATn(VM-VTn-VDSATn/2)
(W/L)n kpVDSATp(VDD-VM+VTp+VDSATp/2)
Thus
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0.25mCMOS,VDD=2.5V
VM is relatively insensitive to
variations in device ratio
1.4
Vmb
Vma
ChangingWp/Wn ratio
shiftsthetransientregion
oftheVTC.
Thiscanbeveryuseful, as
asymmetricaltransfer
characteristicsareactually
desirableinsomedesigns.
1.3
1.2
1.1
42
Making VM asymmetric
Simulated Inverter VM
1.5
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1
0.9
0.8
0.1
(W/L)p/(W/L)n
~3.4
10
TomovetheVM to1.5Vrequiresatransistorratioof
11,andfurtherincreasesareprohibitivelyexpensive.
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44
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Vout
V OH
VOH = VDD
VM
VM
V in
VOL = GND0
V OL
Vin VIH
A piece-wise linear
approximation of VTC
V IL
VIL
A simplified approach
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2.5
Vout (V)
2
1.5
VM 1.25V, g = -27.5
0.5
0
0.5
Vin (V)
1.5
2.5
Output resistance
low-output = 2.4k
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high-output = 3.3k
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V IH
This gives,
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Gain Determinates
Vin
0.5
1.5
2.5
0
-2
-4
(1+r)
g ---------------------------------(VM-VTn-VDSATn/2)(n - p )
-6
-8
-10
Determined by technology
parameters, especially channel
length modulation (). Only
designer influence through supply
voltage and VM (transistor sizing).
-14
-16
-18
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PVT
Nominal
Bad PMOS
Good NMOS
0
0
0.5
1.5
2.5
Vin (V)
0.2
VDD
tpHL = f(Ron.CL)
Vout (V)
0.15
Vout (V)
2.5
Forfixedr,VM isproportionaltoVDD.
GainincreaseswithdecreaseinVDD ( areconstant)!
1.5
1
= 0.69 RonCL
0.1
Vout
0.05
0.5
CL
Ron
Gain=-1
0
0
0.5
Corners:
SlowFast
FastFast
FastSlow
SlowSlow
1.5
0.5
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PVT
Good PMOS
Bad NMOS
Vout (V)
1.5
2.5
ln(0.5)
Vout
1
VDD
0.5
Vin (V)
Device threshold voltages are
kept (virtually) constant Y. S. Chauhan, IITK
0.05
0.1
0.15
Vin (V)
Device threshold voltages are
kept (virtually) constant 51
0.2
0.36
Vin = V DD
RonCL
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t
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Gate-Drain Capacitance
Gate-drain
capacitances
Diffusion
capacitances
Wire
capacitances
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Inadigitalinverter,thelargescalegainbetweeninputandoutputalwaysequals1.
CMOS Inverters
In
VDD
metal1-poly via
metal1
PMOS
polysilicon
metal2
VDD
pdiff
1.2m
=2
Out
In
Metal1
Polysilicon
metal1-diff via
ndiff
NMOS
GND
GND
metal2-metal1 via
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Transient Response
3
2.5
Propagation delay
tp = 0.69 CL (Reqn+Reqp)/2
ln 2
2
Very often, it is desirable for a gate to have identical
propagation delays for both rising and falling inputs.
Use
out
(V)
1.5
tpHL
tpLH
ln 2
and
0.5
0
-0.5
0.5
1.5
t (sec)
2.5
x 10
-10
OvershootscausedbytheCgd oftheinvertertransistors,whichcouplethesteepvoltagestepat
theinputnodedirectlytotheoutputbeforethetransistorscanevenstarttoreacttothe
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changesattheinput.
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DelayofagatecanbemodulatedbymodifyingVDD.Thisflexibilityallowsthedesignerto
tradeoffenergydissipationforperformance.
5.5
5
4.5
t (normalized)
3.5
3
ForVDD>>VTn +VDSATn/2,delayisindependentofVDD.
2.5
2
1.5
1
0.8
1.2
1.4
1.6
V
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DD
1.8
2.2
(V)
SharpincreasearoundVDD2VTn.
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2.4
LargeVDD
reliabilityconcerns(oxide
breakdown,hotelectroneffects)
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Device Sizing
3.8
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3.4
3.2
0.69
2.8
2.6
2.4
2.2
2
8
S
10
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1
Widening both
NMOS and PMOS of
the driving inverter
with a factor S,
14
Self-loading effect:
Intrinsic capacitances
dominate
62
NMOS/PMOS ratio
Impact of Fanout:
1
Extrinsic capacitance is a function of the fanout of the gate: the
larger the fanout, the larger the external load.
Assuming that each fanout gate presents an identical load, and that
the wiring capacitance is proportional to the fanout, we can rewrite
the delay equation as a function of the fanout N.
1
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Total Capacitance
-11
3.6
t (sec)
x 10
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NMOS/PMOS ratio
x 10
-11
0.35
tpHL
0.3
= Wp/Wn
tp
t (sec)
tpLH
4.5
tpH L(nsec)
0.25
0.2
3.5
0.15
3
1.5
2.5
3.5
4.5
0.2
0.4
0.6
trise (nsec)
0.8
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Inverter Sizing
Sizing up an inverter reduces its delay it also increases
its input capacitance.
Inverter Sizing
Cint=Cg
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Cint=Cgd1+Cgd2+Cdb1+Cdb2=3fF
Cg=Cg3+Cg4=3.04fF
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Inverter Chain
In
Inverter Delay
Minimum length devices, L=0.25m
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
W
RP Runit P
Wunit
W
Runit N
Wunit
69
RN RW
tpLH = (ln 2) RPCL
C gin 3
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2W
W
Cunit
Wunit
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Delay
Delay
2W
RW
W
Cext
RW
Load (CL)
tp = k RWCext
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Cext
Load
CN = Cunit
Delay = kRW(Cint + Cext) = kRW Cint(1+ Cext /Cint)
= Delay (Internal) + Delay (Load)
Cint
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Delay Formula
Delay ~
In
Out
1
CL
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gin ,1
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Example
In
C1
Out
1
f2
C L= 8 C 1
ln F
ln f
t p 0 ln F f
ln f ln f
t p t p 0 ln F ln f 1 f
0
f exp1 f
f
ln 2 f
t p Nt p 0 F 1/ N / 1
f 38 2
For = 0, f = e, N = lnF
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Impact of Self-Loading on tp
WithSelfLoading=1
f exp1 f
fopt = 3.6
for =1
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