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M.E Student, 2Associate Professor, Department of Electronics & Communication, L.D.College of Engineering,
Gujarat, India
Abstract
This paper describes the comparator circuits used in FLASH Analog to digital converter (ADC). The performance of FLASH ADC is
greatly influenced by the choice of comparator. In this paper, first a single ended Threshold Inverter Quantizer (TIQ) is presented.
The TIQ comparator is based on a CMOS inverter cell, in which voltage transfer characteristics (VTC) are changed by systematic
transistor sizing. However, TIQ comparator is very sensitive to power supply noise. Another comparator circuit presented in this
paper is Two stage open loop comparator. It is implemented in 50 nm CMOS Technology. Pre-simulation of comparator is done in
LT-Spice and post layout simulation is done in Microwind 3.1.
The comparator is a critical part of almost all kind of analogto-digital (ADC) converters. Depending on the type and
architecture of the comparator, the comparator can have
significant impact on the performance of the target
application. The speed and resolution of an ADC is directly
affected by the comparator input offset voltage, the delay and
input signal range. Some basic applications of comparators are
analog-to-digital conversion, function generation, signal
detection and neural networks etc.
The following study gives an overview of some of the
different comparator topologies examined during the prestudy. Here, first TIQ comparator is described. TIQ
comparator has single ended input and reference voltages are
changed where there is a noise in the power supply voltage.
Then Two stage open loop comparator is presented in this
paper.
2. TIQ COMPARATOR
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Volume: 03 Issue: 02 | Feb-2014, Available @ http://www.ijret.org
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Vm = (r(Vdd+Vtp)+Vtn) / (1+r)
with r = (kp/kn)1/2
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Volume: 03 Issue: 02 | Feb-2014, Available @ http://www.ijret.org
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VOL = VSS.
We can design two stage open loop comparator from
following formulas:
(W6/L6) = (2I6)/(Kp*(VSD6(sat))2) ;
(W7/L7) = (2I7)/(KN*(VDS7(sat))2) ;
(W3/L3) = (W4/L4) = (I5)/(Kp*(VSG3-|VTP|)2) ;
(W1/L1) =(W2/L2) = gm12/(KN*I5);
(W5/L5) = (2I5)/(KN*(VDS5(sat))2) ;
Where, I6=I7= (|Pll|*Cll)/(n + p);
(a)
|Pll| = 1/(tp*(mk)1/2) ;
I5= (2*I7*Cl)/Cll;
4. SIMULATION RESULTS
In this section, the functional and post-layout simulation
results of the two stage open loop comparator have been
presented. There are two parts of result. First, functional
simulation of comparator is done in LT-Spice software using
50 nm CMOS technology. Then, post-layout of comparator is
done in Microwind 3.1 using 50 nm CMOS technology.
(b)
Fig -6: Output of a comparator (a) Vref = 0.8V (b) Vrf = 0.4V
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5. CONCLUSIONS
In this paper, a comparator circuit is proposed. There are some
disadvantages of TIQ comparator in some applications as
stated in section 2. Two stage open loop comparator is
presented using 50nm CMOS technology. This architecture
can be extended to medium-to-high resolution applications
because the simplicity of the circuit. Comparator is a main part
of flash ADC. As a future work, we can design low power
flash ADC using this comparator design.
REFERENCES
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