NIWeek Vision Summit

August 7-8, 2012 Austin, Texas

www.ni.com/niweek/summit_vision

NIWeek Vision Summit

August 78, 2012

Austin, Texas

Getting Started with LabVIEW FPGA for

Vision Applications
Vivek Nath
Systems Engineer
National Instruments

Agenda

What is FPGA?
Getting Started with LabVIEW FPGA
Why Vision on FPGA?
Vision Application Areas
Vision FPGA Hardware
LabVIEW FPGA Programming for Vision

Field Programmable Gate Array (FPGA)

PROGRAMMABLE
INTERCONNECT

I/O BLOCK

Source: Xilinx

CONFIGURABLE LOGIC BLOCK (CLB)

A semi-conductor device containing many gates (logic

devices). A wiring list downloaded to the FPGA determines
the gate connections and the functionality.

Software-Defined Hardware = FPGA

Software Programmable (and Reconfigurable)

Hardware Reliable (and Repeatable)
High-speed Signal Processing (and Parallel Processing)
Extreme Determinism (and clock-cycle control)

Getting Started with LabVIEW FPGA

Demonstration

Motivation FPGA Processing for Vision

High data rate cameras

Highly parallel image processing algorithms
System scalability
Tightly integrate processing and IO

High-Speed Control
FPGA is directly in the path of the image data
FPGA generates and outputs control commands directly

FPGA
Camera
Actuator

Memory
Acquisition
Logic

CPU

LabVIEW FPGA
Inline Processing

Digital I/O

Image Acquisition Device

Memory

Host

High-Speed Control
Laser alignment/steering

Beam profile/position measurements

Low latency control output

High-speed sorting

Segmentation
Measure parameters of contaminant
Trigger rejection valves

In Air Sorting

Image and inspect falling product

Low jitter requirement for decision making and
IO

Adaptive Optics System

Shack-Hartmann wavefront sensor

Wavefront
Image

Detector

Lenslets

Adaptive Optics centroid computation

512 x 512 image divided into 16 x 16 pixel zones (1024 total)

Camera transmits 8 pixels per clock cycle
Running sums stored for each zone
16 x 16 pix
per zone
Centroid divide on last clock of zone
Data reduced to 1k point vector

8 pix per
clock

Adaptive Optics centroid computation

Host based vision starts processing after image transmitted

FPGA vision can start on first pixel and finish shortly after last pixel
Latency reduced by almost 1 frame period
Start of exposure to last result available ~600us
Exp

Exp
Readout
Processing
Time to Decision
Time to Decision

Image Pre-processing
FPGA is directly in the path of the image data
Processes pixels as they arrive
Final image processing handled by the host CPU

FPGA
Memory

Camera

Acquisition
Logic

CPU

LabVIEW FPGA
Inline Processing
Memory

Image Acquisition Device

Host

Image Pre-processing
Optical Coherence Tomography (OCT)

Data scaling
FFT
Logarithmic LUT
Image display (host)

Web and surface inspection

Flat field correction

Thresholding
Particle analysis

NI FPGA Hardware
NI FlexRIO + NI 1483 adapter
module
PCIe-1473R

Base, medium or full configuration

cameras
General purpose digital I/O

LabVIEW FPGA example programs

Area scan and linescan image

acquisition
Threshold
Centroid
Bayer Decoding

FPGA Programming

Acquire data from area and linescan cameras

Transfer images to host
Processing examples
Other Considerations

Sequential Image Processing

Acquire

Threshold

Morphology

Pipelining
Processing loop rate
limited by longest delay
in SCTL
Reduce delays by
splitting operations into
multiple cycles
Increases speed, but
also latency

Acquire

Threshold
Morphology

Pipelining (contd)
Common implementation: feedback nodes
instead of shift registers

Vision Application Development

Considerations
Prototype application first using Vision tools on CPU
(Host)
Define FPGA value statement

Speed
Scalability
Determinism
Size, weight, power

Is IP readily available?
NI LabVIEW FPGA IP Builder

Sources for Processing Algorithms

IPNet (ni.com/ipnet)

Repository for image processing and many other

functions

Xilinx CORE Generator Libraries

15+ blocks for image scaling, color space

conversion, noise removal, etc.
Integrated within LabVIEW FPGA environment

IP Integration Node

Import custom VHDL to create IP blocks with

standard LabVIEW IO interfaces

Is LabVIEW FPGA Appropriate?

Latency
Jitter
Computing power
Pipelining
Security
Weight / Power / Heat
Complexity
Raw Clock Rates
Limited Floating Point support

NIWeek Vision Summit

August 78, 2012

Austin, Texas

Keynote
Embedded Vision Alliance

Tuesday, August 7
1:00-2:00

Inside the Thunderdome FPGAs vs. Multicore Processors

National Instruments

10:30-11:30

Extending Machine Vision in LabVIEW to 3D Applications

ImagingLab

2:15-2:45

Visual Servoing Using RIO Technology

National Instruments

2:45-3:15

Vision Inspection for Defects in Wafer Fabrication Process

Graftek Imaging

3:30-4:00

Automated Seed Germination Monitoring System With Multispectral and Color Image
Analysis

Coleman Technologies

4:00-4:30

Best Practices: Image Calibration

National Instruments

4:45-5:15

Aligning and Calibrating Multiple Line Scan Cameras for Web Inspection

PVI Systems

5:15-5:45

Getting Started With LabVIEW FPGA for Vision Applications

National Instruments

10:30-11:30

Whats New in the NI Vision Development Modules 2012 3D Vision and More

National Instruments

1:00-2:00

Vision at Mach 1

GE Global Research Center

2:15-3:15

Optics and Lighting Best Practices

Edmund Optics

3:30-4:30

Applying Industry Standards in Imaging

Procter and Gamble

4:45-5:15

USB3 Vision in a Nutshell

National Instruments

5:15-5:45

Keynote: The Evolution of Embedded Vision

Tuesday, August 7

Wednesday, August 8