n Tt Nghip

CHNG II
VI IU KHIN
PIC 18F4550

CHNG II: VI IU KHIN PIC 18F4550

Trang 1

 n Tt Nghip

2.1.

TNG QUAN V VI IU KHIN PIC:

PIC l mt h vi iu khin RISC c sn xut bi cng ty Microchip Technology.

Th h PIC u tin l PIC1650 c pht trin bi Microelectronics Division thuc General
Instrument.
PIC l vit tt ca "Programmable Intelligent Computer" l mt sn phm ca hng
General Instruments t cho dng sn phm u tin l PIC1650. Thi im PIC1650 c
dng giao tip vi cc thit b ngoi vi cho my ch 16 bit CP1600, v vy, ngi ta cng
gi PIC vi ci tn "Peripheral Interface Controller" b iu khin giao tip ngoi vi.
CP1600 l mt CPU mnh nhng li yu v cc hot ng xut nhp v vy PIC 8-bit
c pht trin vo nm 1975 h tr cho hot ng xut nhp ca CP1600.
ROM cha m, mc d khi nim RISC cha c s dng thi by gi, nhng PIC
thc s l mt vi iu khin vi kin trc RISC, chy mt lnh vi mt chu k my gm 4
chu k ca Oscillator.
Nm 1985 General Instruments bn cng ngh cc vi in t ca h, v ch s hu mi
hy b hu ht cc d n - lc qu li thi. Tuy nhin PIC c b sung EEPROM
to thnh 1 b iu khin vo ra lp trnh.
Ngy nay rt nhiu dng PIC c xut xng vi hng lot cc module ngoi vi tch
hp sn (nh USART, PWM, ADC...), vi b nh chng trnh t 512 Word n 32K Word.

2.2.

MT S C TNH CHUNG CA VI IU KHIN PIC:

Hin nay c kh nhiu dng PIC v c rt nhiu khc bit v phn cng, nhng chng
ta c th im qua mt vi nt nh sau:

L CPU 8/16 bit, xy dng theo kin trc Harvard.

C b nh Flash v ROM c th tu chn t 256 byte n 256 Kbyte.

C cc cng xut nhp (I/O ports).

C timer 8/16 bit.

C cc chun giao tip ni tip ng b/khng ng b USART.

C cc b chuyn i ADC 10/12 bit.

C cc b so snh in p (Voltage Comparators).

C cc khi Capture/Compare/PWM.

C h tr giao tip LCD.

C MSSP Peripheral dng cho cc giao tip IC, SPI, v IS.

C b nh ni EEPROM - c th ghi/xo ln ti 1 triu ln.

C khi iu khin ng c, c encoder.

C h tr giao tip USB.

C h tr iu khin Ethernet.

CHNG II: VI IU KHIN PIC 18F4550

Trang 2

 n Tt Nghip

C h tr giao tip CAN.

2.2.1. Cc c tnh USB (Universal Serial Bus) :

Ph hp vi USB V2.0

Tc thp (1.5 Mb/s) v Tc Cao (12 Mb/s)

H tr iu khin, Ngt, ng b v Truyn Khi

H tr ln ti 32 Endpoints ( 16 Endpoints mi chiu)

2 b nh RAM 1-Kbyte cho USB

B thu-pht USB On-Chip v B n p On-Chip

Giao tip cho B thu-pht USB Off-Chip

Truyn Port song song (Streaming Parallel Port - SPP) cho truyn d
liu USB ( ch thit b 40/44 chn)

2.2.2. Cc ch qun l nng lng :

Chy: CPU chy, thit b ngoi vi chy.

Ch: CPU tt, thit b ngoi vi chy.

Ng: CPU tt, thit b ngoi vi tt.

Thot khi ch ch trong 5.8 s.

Thot khi ch ng trong 0.1 s.

Oscillator Timer1: 1.1 s, 32kHz, 2V.

Watchdog Timer2: 2.1 s.

Khi ng Oscillator 2 tc

2.2.3. Cu trc linh hot ca Oscillator :

4 ch thch anh, bao gm chnh xc cao PLL cho USB

2 ch xung Clock bn ngoi, ln ti 48 Mhz.

Khi dao ng ni:

- 8 tn s c th la chn bi ngi dng, t 31 kHz n 8 Mhz
- Ngi dng c th iu chnh b vo tn s sai lch

Oscillator th 2 s dng Timer1 32 kHz

Cc la chn cho Dual Oscillator cho php Vi iu khin v module

USB chy cc tc xung clock khc nhau.

CHNG II: VI IU KHIN PIC 18F4550

Trang 3

 n Tt Nghip

Fail-Safe Clock Monitor:

- Cho php tt an ton nu c bt k xung clock no dng.

2.2.4. Cc c tnh ngoi vi ni bt :

Dng Sink/Source cao : 25 mA/ 25 mA

3 External Interrupts

4 module Timer ( Timer0 n Timer3)

Ln ti 2 Capture/Compare/PWM (CCP) module:

- Capture 16-bit, phn gii ti a 5.2 ns
- Compare 16-bit, phn gii ti a 83.3 ns
- phn gii ca PWM l 1 n 10-bit

Module Capture/Compare/PWM (ECCP) ci tin:

- Cc ch nhiu ng ra.
- C th chn phn gii
- C th lp trnh thi gian ch
- T ng shutdown v t ng restart.

Module USART ci tin:

- H tr LIN bus

Module Master Synchronous Serial Port (MSSP) h tr 3-wire SPI (4

ch ) v I2C Master v ch Slave.

10-bit, ln ti 13 knh ADC vi kh nng lp trnh thi gian nhn

2 b so snh Analog vi ng vo a hp

Bng 2.1: So snh cu trc 4 loi PIC 18F

S chn PIC18F2455/2550/4455/4550

CHNG II: VI IU KHIN PIC 18F4550

Trang 4

 n Tt Nghip

Hnh 2.1: S chn PIC18F2455/2550/4455/4550 loi 28 v 40 chn

CHNG II: VI IU KHIN PIC 18F4550

Trang 5

 n Tt Nghip

Hnh 2.2: S chn PIC18F2455/2550/4455/4550 loi 44 chn

CHNG II: VI IU KHIN PIC 18F4550

Trang 6

 n Tt Nghip

2.3.

VI IU KHIN PIC 18F4550

2.3.1. Cu hnh PIC 18F4550

PIC 18F4550 c 40/44 chn vi cu trc nh sau:

C 5 port xut/ nhp.
C 13 knh chuyn i A/D
C port giao tip song song

c im
Tn s hot ng
B nh chng trnh (bytes)

PIC 18F4550
DC 48MHz
32768

B nh chng trnh (cu trc)

B nh d liu (bytes)

16384
2048

B nh d liu EEPROM (bytes)

Ngun ngt
I/O port

256
20
A, B, C ,D, E

Timer
Capture/Compare/PWM module
Capture/Compare/PWM module ci tin
Giao tip Serial

4
1
1
MSSP, USART ci tin

USB module
Streaming Parallel Port (SPP)
10-Bit Analog-to-Digital Module
Reset ( v Delay)

1
C
13 knh
POR, BOR,
RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR(optional),
WDT

B so snh tng t
Tp lnh

2
75, 83 vi tp lnh m rng

S chn

40-pin PDIP
44-pin QFN
44-pin TQFP
Bng 2.2: c im PIC 18F4550

CHNG II: VI IU KHIN PIC 18F4550

Trang 7

 n Tt Nghip
2.3.2. S khi bn trong PIC 18F4550

Hnh 2.3: S khi PIC 18F450

CHNG II: VI IU KHIN PIC 18F4550

Trang 8

 n Tt Nghip
Hnh 2.3 trnh by s khi ca PIC 18F4550, gm cc khi:

Khi ALU Arithmetic Logic Unit.

Khi b nh cha chng trnh Flash Program Memory.

Khi b nh cha d liu EEPROM Data EPROM.

Khi b nh file thanh ghi RAM RAM file Register.

Khi gii m lnh v iu khin Instruction Decode Control.

Khi thanh ghi c bit.

Khi b nh ngn xp.

Khi reset mch khi c in, khi nh thi reset mch khi c in, khi nh
thi n nh dao ng khi c in, khi nh thi gim st, khi reset khi st
gim ngun, khi g ri, khi lp trnh b nh in p thp.

Khi ngoi vi timer T0, T1, T2, T3

Khi giao tip ni tip.

Khi chuyn i tn hiu tng t sang s ADC.

Khi so snh in p tng t.

Khi to in p tham chiu.

Khi cc port xut nhp.

CHNG II: VI IU KHIN PIC 18F4550

Trang 9

 n Tt Nghip
2.3.3. S chn v chc nng cc chn PIC 18F4550

Hnh 2.4: S chn PIC 18F4550 loi 40 chn

1. Chn MCLR/Vpp/RE3:
- MCLR: ng vo reset tch cc mc thp
- Vpp: ng vo nhn in p khi ghi d liu vo b nh ni flash
- RE3: xut/ nhp s
2. Chn RA0/AN0
- RA0: xut/ nhp s
- AN0: ng vo tng t ca knh th 0
3. Chn RA1/AN1
- RA1: xut/nhp s.
- AN1: ng vo tng t ca knh th 1.
4. Chn RA2/AN2/VREF-/CVREF
- RA2: xut/nhp s.
- AN2: ng vo tng t ca knh th 2.
- VREF-: ng vo in p chun (thp) ca b ADC.
- CVREF: in p tham chiu VREF ng ra b so snh
5. Chn RA3/AN3/VREF+
- RA3: xut/nhp s.

CHNG II: VI IU KHIN PIC 18F4550

Trang 10

 n Tt Nghip
- AN3: ng vo tng t knh th 3.
- VREF+: ng vo in p chun (cao) ca b A/D.
6. Chn RA4/T0CKI/C1OUT/RCV
- RA4: xut/nhp s m khi c cu to l ng ra.
- TOCKI: ng vo xung clock t bn ngoi cho Timer0.
- C1OUT: ng ra b so snh 1.
7. Chn RA5/AN4/SS/HLVDIN/C2OUT
- RA5: xut/nhp s.
- AN4: ng vo tng t knh th 4.
- SS : ng vo chn la SPI ph.
- C2OUT: ng ra b so snh 2.
8. Chn RE0/AN5/CK1SPP
- RE0: xut/nhp s.
- AN5: ng vo tng t 5.
9. Chn RE1/AN6/CK2SPP
- RE1: xut/nhp s.
- AN6: ng vo tng t knh th 6.
10. Chn RE2/AN7/OESPP
- RE2: xut/nhp s.
- AN7: ng vo tng t knh th 7.
11. Chn VDD
12. Chn VSS
13. Chn OSC1/CLKI: l ng vo kt ni vi dao ng thch anh hoc ng vo nhn
xung clock bn ngoi.
- OSC1: ng vo dao ng thch anh hoc ng vo ngun xung bn ngoi.
Ng vo c mch Schmitt Trigger nu s dng dao ng RC
- CLKI: ng vo ngun xung bn ngoi.
14. Chn OSC2/CLKO/RA6: ng ra dao ng thch anh hoc ng ra cp xung clock.
- OSC2: ng ra dao ng thch anh. Kt ni n thch anh hoc b cng
hng.
- CLKO: ch RC, ng ra ca OSC2, bng tn s ca OSC1 v chnh l
tc ca chu k lnh.
- RA6: : xut/nhp s.
15. Chn RC0/T1OSO/T13CKI

CHNG II: VI IU KHIN PIC 18F4550

Trang 11

 n Tt Nghip
- RC0: xut/nhp s
- T1OSO: ng ra ca b dao ng Timer1.
- T13CKI: ng vo xung clock t bn ngoi Timer1 v Timer 3
16. Chn RC1/T1OSI/CCP2/UOE
- RC1: xut/nhp s.
- T1OSI: ng vo ca b dao ng Timer1.
- CCP2: ng vo Capture2, ng ra compare2, ng ra PWM2
17. Chn RC2/CCP1/P1A
- RC2: xut/nhp s
- CCP1: ng vo Capture1, ng ra compare1, ng ra PWM1
18. Chn VUSB : chn ngun USB
19. Chn RD0/SPP0
- RD0: xut/nhp s.
- SPP0: d liu port song song
20. Chn RD1/SPP1
- RD1: xut/nhp s
- SPP1: d liu port song song
40. Chn RB7/KBI3/PGD
- RB7: xut/nhp s
- KBI3: Interrupt-on-change
- PGD: mch g ri v d liu lp trnh ICSP.
39. Chn RB6/KBI2/PGC
- RB6: xut/nhp s
- KBI2: Interrupt-on-change
- PGC: mch g ri v xung clock lp trnh ICSP
38. Chn RB5/KBI1/PGM
- RB5: xut/nhp s
- KBI1: Interrupt-on-change
- PGM: Chn cho php lp trnh in p thp ICSP.
34. Chn RB1/AN10/INT1/SCK/SCL
- SCK: ng vo xung clock ni tip ng b/ng ra ca ch SPI.
- SCL: ng vo xung clock ni tip ng b/ng ra ca ch I2C.
33. Chn RB0/AN12/INT0/FLT0/SDI/SDA

CHNG II: VI IU KHIN PIC 18F4550

Trang 12

 n Tt Nghip
- INT0: ng vo nhn tn hiu ngt ngoi.
- SDI: d liu vo SPI.
- SDA: xut/nhp d liu I2C.
26. Chn RC7/RX/DT/SDO
- RC7: xut/nhp s.
- RX: nhn bt ng USART.
- DT: d liu ng b USART.
- SDO: d liu ra SPI.
25. Chn RC6/TX/CK
- RC6: xut/nhp s.
- TX: truyn bt ng b USART.
- CK: xung ng b USART

CHNG II: VI IU KHIN PIC 18F4550

Trang 13

 n Tt Nghip

2.4. T CHC B NH CA PIC 18F4550:

PIC 18F4550 c 3 loi b nh: b nh chng trnh (Program Memory), b nh d
liu RAM v b nh d liu EEPROM.

2.4.1. Kin trc b nh ca PIC:

PIC c kin trc b nh dng Harvard, mt kin trc ci tin so vi kin trc Von
Neumann.

Hnh 2.5: Kin trc Von Neumann v Harvard.

Kin trc Von Neumann: vi kin trc ny th b nh giao tip vi CPU thng qua 1
bus d liu 8 bit, b nh c cc nh cha d liu 8 bit, b nh va lu tr chng trnh v
d liu.
- u im: kin trc n gin.
- Khuyt im: do ch c 1 bus nn tc truy sut chm, kh thay i dung lng lu
tr ca nh.
Kin trc Harvard: vi kin trc ny th b nh c tch ra lm 2 loi b nh c
lp: b nh lu chng trnh v b nh lu d liu, CPU giao tip vi 2 b nh c lp nn
cn 2 bus c lp. V c lp nn c th thay i s bit lu tr ca tng b nh m
khng nh hng ln nhau. Vi PIC th b nh chng trnh vi mi nh lu tr 14
bit, cn b nh d liu vi mi nh lu d liu 8 bit.
- u im: do ch c 2 bus nn tc truy sut nhanh, ty thay i s bit ca nh.
- Khuyt im: kin trc phc tp.

CHNG II: VI IU KHIN PIC 18F4550

Trang 14

 n Tt Nghip
2.4.2. Kho st b nh chng trnh ca PIC:

Hnh 2.6: S b nh chng trnh v ngn xp

CHNG II: VI IU KHIN PIC 18F4550

Trang 15

 n Tt Nghip
B nh chng trnh ca PIC 18Fx455 c dung lng 32K.
Thanh ghi b m chng trnh PC (Program Counter) s qun l a ch ca b nh
chng trnh, thanh ghi PC c di 21 bit s qun l 2.097.152 nh tng ng vi 32K
nh. Mi nh chng trnh lu 14 bit d liu.
Khi PIC b reset th thanh ghi PC c gi tr l 0000H v PIC s bt u thc hin
chng trnh ti a ch 0000H.
Khi c bt k ngt no tc ng th PIC s thc hin chng trnh phc v ngt cao ti
a ch 0008H v ngt thp ti a ch 0018H.
Mi trang ca b nh chng trnh c a ch xc nh nh trong hnh 2.6, vic phn
chia theo trang b nh ch c tc dng i vi lnh nhy v lnh gi chng trnh con. Khi
ni nhy n hoc chng trnh con nm trong cng 1 trang th lnh s vit ngn gn hn so
vi trng hp nm khc trang, s c trnh by phn cc kiu truy xut b nh.
Trong cc h vi iu khin khc th b nh ngn xp dng chung vi b nh d liu,
u im l cu trc n gin, khuyt im l vic dng chung nu khng bit gii hn s ln
chim ln nhau v lm mt d liu lu trong b nh ngn xp v chng trnh thc thi sai.
vi iu khin PIC th nh thit k tch b nh ngn xp c lp vi b nh d liu
v ch dng lu a ch tr v khi thc hin lnh gi chng trnh con v khi thc hin
ngt. Dung lng b nh b nh ngn xp ch c 32 nh t stack level 1 n stack level 31
- xem hnh 2.6. Do ch c 8 nh nn khi thc hin cc chng trnh con lng vo nhau ti
a l 32 cp.
Khi khng s dng ngt th chng trnh c th vit bt u v lin tc ti a ch
0000H, nhng nu s dng ngt th nn dng lnh nhy trnh vng nh bt u ti a ch
0008H - v vng nh ny dng vit chng trnh con phc v ngt.
B nh chng trnh c chc nng lu tr chng trnh. Chng trnh sau khi vit
xong trn my tnh, dch ra s nh phn s c np vo b nh chng trnh vi iu khin
thc hin.

2.4.4. Kho st b nh d liu v thanh ghi trng thi ca PIC

A. Cu trc b nh d liu:
B nh d liu c phn chia thnh 16 Bank, mi bank c 256byte bao gm mt s
thanh ghi chc nng c bit, cn li l cc nh thng dng c chc nng lu tr d liu.
Cc thanh ghi c chc nng c bit nm vng a ch thp, cc nh cn li
khng c g c bit nm ng a ch bn trn cc thanh ghi chc nng c bit xem nh
cc nh RAM dng lu d liu.
Tt c cc bank thanh ghi u cha nhng thanh ghi c bit - xem hnh 2.8:

CHNG II: VI IU KHIN PIC 18F4550

Trang 16

 n Tt Nghip

Hnh 2.7: T chc b nh d liu ca PIC

CHNG II: VI IU KHIN PIC 18F4550

Trang 17

 n Tt Nghip

Hnh 2.8: T chc Thanh ghi chc nng c bit ca PIC

B. Thanh ghi trng thi

CHNG II: VI IU KHIN PIC 18F4550

Trang 18

 n Tt Nghip
Bit 7-5:

Khng s dng: c l 0

Bit 4:

N: Nagative bit Bit m. Bit ny c s dng nh du ton hc.

N ch ra kt qu khi no kt qu l m
1 = kt qu l m
2 = kt qu l dng

Bit 3:

OV: Overflow bit Bit trn. Bit ny c s dng nh du ton hc.

N ch ra mt php ton trn 7 bit lm bit du thay i trng thi
1 = s kin trn xy ra cho du ton hc
0 = s kin trn khng xy ra.

Bit 2:

Z: Zero bit (bit 0)

1 = khi kt qu bng 0.
0 = khi kt qu khc 0.

Bit 1:

DC: Digit carry/borrow bit

(cc lnh ADDWF, ADDLW, SUBLW, SUBWF)
1 = khi cng 4 bit thp b trn.
0 = khi cng 4 bit thp khng b trn.

Bit 0:

C: Carry/borrow bit (cc lnh ADDWF, ADDLW, SUBLW, SUBWF)

1 = khi kt qu php ton c trn.
0 = khi kt qu php ton khng b trn

CHNG II: VI IU KHIN PIC 18F4550

Trang 19

 n Tt Nghip

2.5.

CU HNH CC PORT CA PIC 18F4550

2.5.1. Gii thiu:

Vi iu khin c cc port xut nhp d liu giao tip vi cc i tng iu khin.

Tn hiu iu khin t CPU gi ra port iu khin, ng thi c cc port nhn d liu v
x l. Trong mt h thng lun c cc tn hiu vo ra v nh h thng iu khin robo nh
hnh sau:

Hnh 2.9: S kt ni Port vi i tng iu khin

Mi vi iu khin khc nhau c cu hnh cc port cng khc nhau, phn ny s kho st cc
port ca vi iu khin PIC bao gm port A, B, C, D , E.
Mi port ca vi iu khin PIC gm c thanh ghi port v thanh ghi nh hng cho Port v d
nh hnh 2.10 l PORTA v TRISA. Bit ca thanh ghi nh hng TRIS bng 0 th port c
chc nng xut d liu, nu bng 1 th c chc nng nhp d liu.
Ch : '0' tng ng vi 'OUT', '1' tng ng vi 'IN'.

CHNG II: VI IU KHIN PIC 18F4550

Trang 20

 n Tt Nghip

: S t ni

rt x t nh

CHNG II: VI IU KHIN PIC 18F4550

hin

Trang 21

 n Tt Nghip
2.5.2. Cc Port xut nhp IO:
A. Port A v thanh ghi TrisA

Hnh 2.11: Bng tm tt chc nng cc chn ca PortA

CHNG II: VI IU KHIN PIC 18F4550

Trang 22

 n Tt Nghip

Hnh 2.12: Tm tt cc thanh ghi lin kt vi PortA

CHNG II: VI IU KHIN PIC 18F4550

Trang 23

 n Tt Nghip
B. Port B v thanh ghi TrisB

Hnh 2.13: Bng tm tt chc nng cc chn ca PortB

CHNG II: VI IU KHIN PIC 18F4550

Trang 24

 n Tt Nghip

Hnh 2.14: Bng tm tt chc nng cc chn ca PortB

Hnh 2.15: Bng tm tt cc thanh ghi lin kt vi PortB

CHNG II: VI IU KHIN PIC 18F4550

Trang 25

 n Tt Nghip
C. Port C v thanh ghi TrisC

Hnh 2.16: Bng tm tt chc nng cc chn ca PortC

CHNG II: VI IU KHIN PIC 18F4550

Trang 26

 n Tt Nghip

Hnh 2.17: Bng tm tt chc nng cc chn ca PortC

Hnh 2.18: Bng tm tt cc thanh ghi lin kt vi PortC

CHNG II: VI IU KHIN PIC 18F4550

Trang 27

 n Tt Nghip
D. Port D v thanh ghi TrisD

Hnh 2.19: Bng tm tt chc nng cc chn ca PortD

CHNG II: VI IU KHIN PIC 18F4550

Trang 28

 n Tt Nghip

Hnh 2.20: Bng tm tt cc thanh ghi lin kt vi PortD

CHNG II: VI IU KHIN PIC 18F4550

Trang 29

 n Tt Nghip
E. Port E v thanh ghi TrisE

Hnh 2.21: Bng tm tt chc nng cc chn ca PortE

Hnh 2.22: Bng tm tt cc thanh ghi lin kt vi PortE

CHNG II: VI IU KHIN PIC 18F4550

Trang 30

 n Tt Nghip

2.6.

TIMER/ COUNTER CA PIC 18F4550:

2.6.1. Gii thiu:

Vi iu khin PIC 18F4550 c 4 timer T0, T1, T2 v T3. T0,T1 v T3 l timer/counter

16 bit c 3 u c b chia trc. T2 ch l timer/counter 8 bit c b chia trc v chia sau
phc v cho cc ng dng c bit.

2.6.2. Kho st Timer/ Counter:

A. Kho st Timer0:
Module Timer0 c nhng c im sau:
- C th la chn bng phn mm ch hot ng Timer/Counter 8-bit hoc 16-bit
- C th c v ghi thanh ghi
- Vi ch 8-bit, c th la chn chia trc bng phn mm
- C th chn la ngun xung clock (trong hoc ngoi)
- La chn cnh ln hoc xung ca xung clock ngoi
- Ngt trn
Ngt ca Timer0 c to ra khi thanh ghi TMR0 trn t FFh n 00h ch 8-bit ,
hoc t FFFFh n 0000h ch 16-bit. Vic trn ny lm bit c trn TMR0IF t 0 ln 1.
Ngt c th ngn bng cch xa bit cho php ngt TMR0IE (INTCON<5>). Trc khi cho
php ngt li, TMR0IF phi c xa bi phn mm trong chng trnh con ngt.
Nu Timer0 tt trong ch Sleep, ngt TMR0 khng th nh thc vi x l khi
Sleep.

CHNG II: VI IU KHIN PIC 18F4550

Trang 31

 n Tt Nghip

Hnh 2.23: Thanh ghi iu khin Timer0

Hnh 2.24: Cc thanh ghi lin kt vi Timer0

CHNG II: VI IU KHIN PIC 18F4550

Trang 32

 n Tt Nghip
B. Kho st Timer1:
Module Timer1 timer/counter c nhng c im sau:
- La chn ch 16-bit timer hoc counter bng phn mm
- c v ghi li cc thanh ghi 8-bit (TMR1H v TMR1L)
- Chn la ngun xung clock vi thit b to xung clock hoc la chn b dao ng
Timer1 ni.
- Ngt trn
- Module Reset Triger CCP s kin c bit
Cp thanh ghi TMR1 (TMR1H:TMR1L) tng t 0000h n FFFFh v quay li 0000h.
Nu ngt TMR1 cho php, n to ra vic trn v set c trn TMR1IF (PIR1<0>) ln 1. Ngt
c th bt hoc tt bng set hoc xa TMR1IE (PIE1<0>).

CHNG II: VI IU KHIN PIC 18F4550

Trang 33

 n Tt Nghip

Hnh 2.25: Thanh ghi iu khin Timer1

CHNG II: VI IU KHIN PIC 18F4550

Trang 34

 n Tt Nghip

Hnh 2.26: Cc thanh ghi lin kt vi Timer1

C. Kho st Timer2:
Module Timer2 c nhng c im sau:
- timer 8-bit
- C th dng phn mm chia trc (1:1, 1:4 v 1:16) v chia sau (1:1 n 1:16)
- Ngt TMR2 n khi trng PR2
- La chn xung clock ln cho module MSSP.
Timer 2 c th to ra la chn thit b ngt. Ng ra tn hin ca Timer2 yu cu ng ra
4-bit ca counter/postcaler. Ngt c c cho php bng cch iu chnh bit TMR2IE
(PIE1<1>). 16 ch chia trc c th la chn bng cc bit iu khin chia trc
T2OUTPS3:T2OUTPS0 (T2CON<6:3>)

CHNG II: VI IU KHIN PIC 18F4550

Trang 35

 n Tt Nghip

Hnh 2.27: Thanh ghi iu khin Timer2

Hnh 2.28: Cc thanh ghi lin kt vi Timer2

D. Kho st Timer3:
Module timer/counter Timer3 c nhng c im sau:
- La chn bng phn mm ch 16-bit timer hoc counter.
- c v ghi cc thanh ghi 8-bit (TMR3H v TMR3L)
- La chn ngun xung clock vi thit b to xung hoc b dao ng Timer1 bn trong
- Ngt trn

CHNG II: VI IU KHIN PIC 18F4550

Trang 36

 n Tt Nghip
Cp thanh ghi TMR3 (TMR3H:TMR3L) tng t 0000h n FFFFh v trn 0000h.
Ngt Timer3 nu cho php s to ra trn v lm bit c trn ln 1 TMR3IF (PIR2<1>). Ngt c
th cho php bng cch iu chnh bit TMR3IE (PIE2<1>).

Hnh 2.29: Thanh ghi iu khin Timer3

CHNG II: VI IU KHIN PIC 18F4550

Trang 37

 n Tt Nghip

Hnh 2.30: Cc thanh ghi lin kt vi Timer3

CHNG II: VI IU KHIN PIC 18F4550

Trang 38