Professional Documents
Culture Documents
V.A.
CSED,TU
Disclaimer
This is NOT A COPYRIGHT
MATERIAL
www.os-book.com
www.cs.jhu.edu/~yairamir/cs418/os2/sld001.htm
www.personal.kent.edu/~rmuhamma/OpSystems/os.html
http://msdn.microsoft.com/en-us/library/ms685096(VS.85).aspx
http://www.computer.howsttuffworks.com/operating-system6.htm
http://williamstallings.com/OS/Animations.html
Etc
VA.
CSED,TU
Introduction
Program must be brought into memory and placed within a process for it
to be run
VA.
CSED,TU
VA.
CSED,TU
Compilation Pipeline
VA.
CSED,TU
Address Binding
VA.
CSED,TU
Logical/Physical Address
Logical and Physical Addresses are the same in compile-time and loadtime address-binding schemes.
VA.
CSED,TU
VA.
CSED,TU
MMU
VA.
CSED,TU
H/W Protection
VA.
CSED,TU
VA.
CSED,TU
Swapping
scheduling algorithms.
VA.
CSED,TU
Swapping (Conti)
VA.
CSED,TU
Contiguous Allocation
Multiple-partition allocation
VA.
CSED,TU
Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size
Worst-fit: Allocate the largest hole; must also search entire list
Fragmentation
Paging
To run a program of size n pages, need to find n free frames and load
program
Internal Fragmentation
VA.
CSED,TU
VA.
CSED,TU
Paging Hardware
VA.
CSED,TU
VA.
CSED,TU
Paging Example
VA.
CSED,TU
VA.
CSED,TU
The two memory access problem can be solved by the use of a special
fast-lookup hardware cache called Associative Memory or Translation
Look-aside Buffers (TLBs)
VA.
CSED,TU
Associative Memory
VA.
CSED,TU
VA.
CSED,TU
invalid indicates that the page is not in the process logical address
space
VA.
CSED,TU
VA.
CSED,TU
Hierarchical Paging
VA.
CSED,TU
VA.
CSED,TU
A logical address (on 32-bit machine with 1K page size) is divided into:
Since the PAGE TABLE IS PAGED, the page number is further divided
into:
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
Segmentation
VA.
CSED,TU
VA.
CSED,TU
Segmentation Architecture
VA.
CSED,TU
Segmentation Hardware
VA.
CSED,TU
Example of Segmentation
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
Page replacement find some page in memory, but not really in use,
swap it out
Algorithm
VA.
CSED,TU
if p = 0 no page faults
if p = 1, every reference is a fault
Page Replacement
VA.
CSED,TU
2.
3.
Read the desired page into the (newly) free frame. Update the page
and frame tables.
4.
VA.
CSED,TU
Page Replacement
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
VA.
CSED,TU
Optimal Algorithm
VA.
CSED,TU
VA.
CSED,TU
Thrashing
If a Process does not have enough pages, the Page-fault rate is very
high. This leads to:
VA.
CSED,TU
Thrashing (contd.)
VA.
CSED,TU
Reference String: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
Counter Implementation
-- Every page entry has a counter; every time page is referenced through this
entry, copy the clock into the counter
-- When a page needs to be changed, look at the counters to determine which
are to change
VA.
CSED,TU
VA.
CSED,TU
Page referenced:
VA.
CSED,TU
VA.
CSED,TU
Reference bit
Second chance
VA.
CSED,TU
Counting Algorithms
Keep a counter of the number of references that have been made to each
page.
MFU Algorithm: Based on the argument that the page with the
smallest count was probably just brought in and has yet to be used
VA.
CSED,TU
Reference List
etc
VA.
CSED,TU
Thnx
VA.
CSED,TU