SPARTAN 2

-Nitin Anand
The Spartan-II family of FPGAs have a regular, flexible, programmable
architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of
programmable Input/output Blocks (IOBs). There are four Delay-Locked Loops
(DLLs), one at each corner of the die. Two columns of block RAM lie on opposite
sides of the die, between the CLBs and the IOB columns. These functional
elements are interconnected by a powerful hierarchy of versatile routing
channels.

SPECIFICATION: Specifications

Mounting Type: Surface Mount

Number of Gates:15000 ~ 200000
Number of I/O:60 ~ 260
Number of LABs/CLBs:96 ~ 1176

Number of Logic Elements/Cells:432 ~ 5292

Package / Case:100-TQFP ~ 456-BBGA
Total RAM Bits:16384 ~ 57344
Voltage - Supply:2.375 V ~ 2.625 V

In XC9572-PC84, the macro cells which corresponds to the input/output pins are
69 macro cells in the 72 macro cells. In case of XC95108-PC84, they are 69
macro cells in the 108 macro cells. The macro cells which don't correspond to the
input/output pins can be used only in the logic circuits inside.

Features

7.5 ns pin-to-pin logic delays on all pins

fCNT to 125 MHz
72 macro cells with 1,600 usable gates
Up to 72 user I/O pins
5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and

Temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macro cells
Within Function Block
- Global and product term clocks, output enables,
Set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
Macro cell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design

protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V Fast FLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP packages

UNIVERSAL BOARD:This is a unique board that accepts any PLD device of any make or package.This
striking feature has been introduced by MILMAN to cater to the needs of design
engineers.

SPECIFICATION:

32 digital input/outputs (Bi-directional) with LED indication

4-key switches in 2X2 matrix format
4 seven segment multiplexed LED display
RS232 driver interface with 9 pin D-type connector for serial code
verification
Power-ON reset circuit with reset key
On board 3.57/6 MHz clock
Polarity free power connector
On board JTAG interface, which eliminates the costly JTAG cable, required
for downloading the design.
ADDITIONAL COMPONENT:
1. Digital input/output: Total 32 digital I/O with LED indication are
provided, which can be used as bidirectional port.
2. Keyboard: Total 4 keys are provided in 2X2-matrix format. There are
two-scan line (SL0 & SL1) and two-return lines (RL0 & RL1).
3. Display: Four seven segment multiplexed LED displays are provided.
The segment a to dp are common to all the displays and the
common point is driven through DIS0 to DIS3. A state 1 will turn
ON particular segment and 0 will switch off. Also DIS0 to DIS1 are
active low.
4. Power on reset circuit: The power ON reset circuit with reset key is
provided with active high output.
5. Clock: On board clock of 3.57 /6 MHz is available.

PIN ASSIGNMENT:

SPARTAN 3E

Overview of the Procedure

1. Design the circuit that you would like to map to the Xilinx part on the FPGA.
You can use schematics, or Verilog, or a mixture of both.
2. Simulate your circuit using the ISE Simulator and a Verilog testbench to
provide inputs to the circuit. Use if statements in your testbench to make it selfchecking.

3. Generate a UCF file to hold constraints such as pin assignments (later well use
the UCF file for other constraints like timing and speed). Use the PlanAhead tool
to generate this file.
4. Assign the I/O pins in your design to the pins on the FPGA that you want them
connected to.
5. Synthesize the design for the FPGA using the XST synthesis tool.
6. Implement the design to map it to the specific FPGA on the Spartan-3E board
7. Generate the programming .bit file that has the bitstream that configures the
FPGA.
8. Connect your Spartan3 board to the computer and use the iMPACT tool to
program the FPGA using the bit stream.

ON BOARD FEATURES
Intel Corporation for the 128 Mbit Strata Flash memories.
Linear Technology for the SPI-compatible A/D and D/A converters, the
programmable pre-amplifier, and the power regulators for the non-FPGA
components
Micron Technology, Inc. for the 32M x 16 DDR SDRAM
SMSC for the 10/100 Ethernet PHY
STMicroelectronics for the 16M x 1 SPI serial Flash PROM
Texas Instruments Incorporated for the three-rail TPS75003 regulator supplying
most of the FPGA supply voltages
Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash
PROM and their support for the embedded USB programmer
Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner-II CPLD
Xilinx Spartan-3E has in-built clock of 50 MHz frequency.

Experiment 1
Aim- Design of a 4 bit counter using Verilog in Xilinx 8.1 platform and
implement it in SPARTAN II kit.
Theory-

Truth table of counter.

Procedure:
1. Click on this icon. For Starting a new project

2. Select File > New Project in the opened window

3. Select a project location and name. For this tutorial we will

Name the project counter. Click Next.

4. Select the device family, device, package, and speed grade,

as shown here. Click Next.

5. Click New Source.

6. Select Verilog Module and enter count as the file name.

Click Next.

7. Specify the inputs and outputs for the counter.

Click Next.

8. In the summary window click Finish.

9. Click Next.

10. Click next, because we do not want to add any other

source.

11. In this summary window click Finish.

12. Write the Verilog code for the counter in the window
shown below.

13. Before we can synthesize this design we need to specify

what pins on the FPGA the inputs and outputs are connected
to. Double-Click on Assign Package Pins under User
Constraints in the Processes pane in the left of the Project
Navigator window.

Note: You may be asked to save the VHDL file, and your
design will be checked for syntax errors (these will need to
be fixed before you can proceed).
14. We want to create a UCF file, so click yes.

15. The PACE editor will load as seen.

16. Enter the pin names for each signal in the Design Object
List at the left as shown here. Click File > Save.

17. This dialog may appear when saving the file select XST
Default :<>

18. You can then view the UCF file by double-clicking .

19. Click on generate programming file as shown

20. A window as shown below will appear after successful

generation of programming file. Double Clink on configure
device (iMPACT) in the Generate programming file option.

21. A iMPACT window that appear select Configure device

using Boundary-Scan(JTAG) and Automatically connect to a
cable and identify Boundary- scan chain. Click on finish

22. After successfully identifying the device select and open

the generated .jed file as shown.

23. Right click on device and select program option.

24. In the programming properties select Erase before

programing click apply and then OK.

25. After success of program check the functioning of your

program in the Kit.

Code:

`timescale 1ns / 1ps

module Counter(input clk, input rst, output reg [3:0]
count);
integer temp;
always @ (posedge clk)
begin
if (rst)
begin
count <= 4'b0000;
temp <= 0;
end
else if (temp == 5000000)
begin
count <= count +1;
temp <= 0;
end
else
temp <= temp+1;
end
endmodule

Experiment-2
Aim- To design a 1 bit full adder in Xilinx 8.1 and implement it on
SPARTAN 2 kit.
Theory-

Fig. Circuit diagram of full adder

Truth table of 1 bit full adder

Code:
`timescale 1ns / 1ps
module FA1(a, b, cin, cout, sum);
input a;
input b;
input cin;
output cout;
output sum;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule

Experiment-3
Aim- To display last 4 digit of your roll number in 7 segment display of

SPARTAN 2 kit using Xilinx 8.1

TheoryThe SPARTAN 2 board has four seven-segment LED displays, each containing
seven bars and one small round dot. To reduce the use of FPGA's I10 pins, the
board uses a time-multiplexing sharing scheme. In this scheme, the four displays
have their individual enable signals but share eight common signals to light the
segments. All signals are active low (i.e., enabled when a signal is 0). The
schematic of displaying a "3" on the rightmost LED is shown in. Note that the
enable signal (i.e., an) is "1 110". This configuration clearly can enable only one
display at a time. We can time-multiplex the four LED patterns by enabling the
four displays in turn. If the refreshing rate of the enable signal is fast enough, the
human eye cannot distinguish the on and off intervals of the LEDs and perceives
that all four displays are lit simultaneously. This scheme reduces the number of
110 pins from 32 to 12 (i.e., eight LED segments plus four enable signals) but
requires a time-multiplexing circuit.
Truth table of 7 segment display decoder.

Fig. Circuit for Time-multiplexing for display in four 7-segment display

simultanously.

Code:

`timescale 1ns / 1ps

module AminSevenSeg(input clk, output reg [7:0]out, output reg [3:0] enable);
reg [15:0]temp=16'b0000000000000000;
always @ (posedge clk )
begin
temp=temp+1;

end
always@ *
case(temp[15:14])
2'b00: begin
enable = 4'b1110;// active low enable biases PNP to make it ON (i.e., DIS-0)
out= 8'b11101101; // data for 5
end
2'b01: begin
enable = 4'b1101; // active low enable biases PNP to make it ON (i.e., DIS-1)
out= 8'b11111101; // data for 6
end
2'b10: begin
enable = 4'b1011;// active low enable biases PNP to make it ON (i.e., DIS-2)
out= 8'b11101111;// data for 9
end
default:

begin
enable = 4'b0111;// active low enable biases PNP to make it ON (i.e., DIS-3)
out= 8'b11111111;// data for 8
end

endcase
endmodule

Experiment-4
Aim- To display and blink last 4 digit of your roll number in 7 segment

display of SPARTAN 2 kit using Xilinx 8.1

Code:
`timescale 1ns / 1ps

module blink(input clk, output reg [7:0]out, output reg [3:0] enable);
reg [15:0]temp=16'b0000000000000000;
reg [20:0]delay=21'b000000000000000000000;
always @ (posedge clk )
begin
temp=temp+1;
delay=delay+1;
end
always@ *
begin

if(delay>=21'b100000000000000000000 && delay <=21'b111111111111111111111)

begin
enable= 4'b1111;
end
else

case(temp[15:14])
2'b00: begin
enable = 4'b1110;// active low enable biases PNP to make it ON (i.e., DIS-0)
out= 8'b11101101; // data for 5
end
2'b01: begin
enable = 4'b1101; // active low enable biases PNP to make it ON (i.e., DIS-1)
out= 8'b11111101; // data for 6
end
2'b10: begin
enable = 4'b1011;// active low enable biases PNP to make it ON (i.e., DIS-2)
out= 8'b11101111;// data for 9
end
default:

begin

enable = 4'b0111;// active low enable biases PNP to make it ON (i.e., DIS-3)
out= 8'b11111111;// data for 8
end
endcase
end
endmodule

Experiment-5
Aim- To display and rotate HELP in 7 segment display of SPARTAN 2 kit

using Xilinx 8.1

Code:
`timescale 1ns / 1ps
module rotation(input clk, output reg [7:0]out, output reg [3:0] enable );
reg [15:0]temp=16'b0000000000000000;
reg [20:0]delay=21'b000000000000000000000;
reg [3:0]param[3:0];
reg [3:0]next;
initial
begin
param[0]=4'b1110;
param[1]=4'b1101;
param[2]=4'b1011;
param[3]=4'b0111;
end
always @ (posedge clk )
begin
temp=temp+1;
delay=delay+1;
if(delay==21'b111111111111111111111 )
begin
next=param[0];

param[0]=param[1];
param[1]=param[2];
param[2]=param[3];
param[3]=next;
end
else
case(temp[15:14])
2'b00: begin
enable = param[0];// active low enable biases PNP to make it ON (i.e., DIS-0)
out= 8'b01110011; // data for 5
end
2'b01: begin
enable = param[1]; // active low enable biases PNP to make it ON (i.e., DIS1)
out= 8'b00111000; // data for 6
end
2'b10: begin
enable = param[2];// active low enable biases PNP to make it ON (i.e., DIS-2)
out= 8'b01111001;// data for 9
end
default:

begin

enable = param[3];// active low enable biases PNP to make it ON (i.e., DIS-3)
out= 8'b01110110;// data for 8
end
endcase
end

endmodule

Experiment-6
Aim- Design a 4 bit Johnson counter and implement it on SPARTAN 3E

kit.
A Johnson counter is a modified ring counter, where the inverted output
from the last flip flop is connected to the input to the first. The register cycles
through a sequence of bit-patterns. The MOD of the Johnson counter is 2n if n
flip-flops are used. The main advantage of the Johnson counter counter is that it
only needs half the number of flip-flops compared to the standard ring counter
for the same MOD.
Theory-

Fig . Circuit diagram of Johnson counter.

Truth table for Johnson counter

Clk
1
2
3
4
5
6
7
8
9

Q0
0
1
1
1
1
0
0
0
0

Q1
0
0
1
1
1
1
0
0
0

Q2
0
0
0
1
1
1
1
0
0

Q3
0
0
0
0
1
1
1
1
0

Code:
`timescale 1ns / 1ps
module AminJohnson (input direction, rst, clk_in, output reg [3:0] count);

FreqDiv InstanceName (.clk_out (clk_out), .clk_in(clk_in));

initial
count[3:0] = 4'b0000;
always @ (posedge clk_out) begin

//clk rising edge

if(!rst)
begin
if(direction)
begin
count[3:1] <= count[2:0];

//Shift lower bits (Left Shift)

count[0]<=!count[3];

//Circulate inverted MSB to LSB

count[2:0] <= count[3:1];

//Shift upper bits (Right Shift)

count[3] <= !count[0];

//Circulate inverted LSB to MSB

end
else
begin

end
end
else
count[3:0] <= 4'b0000;
end
endmodule

`timescale 1ns / 1ps

module FreqDiv(output reg clk_out, input clk_in);
integer count;
initial
begin
clk_out=1'b0;
count=0;
end
always @(posedge clk_in)
if (count==44999999)
begin
count<=0;
clk_out<=~clk_out;
end
else
count<=count+1;
endmodule

Experiment - 7
Aim- Design of a 4 bit LFSR (Linear feedback shift resistor) using Verilog
and implement it in SPARTAN 3E kit.
Theory:
LFSR:
In computing, a linear-feedback shift register (LFSR) is a shift
register whose input bit is a linear function of its previous state.
The most commonly used linear function of single bits is exclusiveor (XOR). Thus, an LFSR is most often a shift register whose input bit is
driven by the XOR of some bits of the overall shift register value.
The initial value of the LFSR is called the seed, and because the
operation of the register is deterministic, the stream of values
produced by the register is completely determined by its current (or
previous) state. Likewise, because the register has a finite number of
possible states, it must eventually enter a repeating cycle. However, an
LFSR with a well-chosen feedback function can produce a sequence of
bits which appears random and which has a very long cycle.
Applications
of
LFSRs
include
generating pseudo-random
numbers, pseudo-noise sequences, fast digital counters, and whitening
sequences. Both hardware and software implementations of LFSRs are
common.

Code:
`timescale 1ns / 1ps
module lfsr(input clk, rst, en, input[3:0]load, output reg [3:0] out);

FreqDiv instance_name(.clk_out(clk_out),.clk_in(clk));
wire feedback;
assign feedback=(out[2]^out[3]);
always @(posedge clk_out)
begin
if(rst)
out=4'b1111;
else if(en)
out[3:0]=load[3:0];
else
out={out[2:0],feedback}; // OUT[3] <= feedback
end
endmodule

`timescale 1ns / 1ps

module FreqDiv(output reg clk_out, input clk_in);
integer count;
initial

begin
clk_out=1'b0;
count=0;
end
always @(posedge clk_in)
if (count==44999999)
begin
count<=0;
clk_out<=~clk_out;
end
else
count<=count+1;
endmodule

Experiment - 8
Aim - Display your name in 16*2 LCD using Verilog in SPARTAN 3E kit.
Theory:

LCD
The Spartan-3A/3AN Starter Kit board prominently features a 2-line by 16character liquid crystal display (LCD). The FPGA controls the LCD via the eightbit data interface. The Spartan-3A/3AN Starter Kit board also supports the four-bit
data interface to remain compatible with other Xilinx development boards.
CHARACTER LCD INTERFACE
Signal name

FPGA Pin

Function

LCD_DB<7>
LCD_DB<6>
LCD_DB<5>
LCD_DB<4>
LCD_DB<3>
LCD_DB<2>
LCD_DB<1>
LCD_DB<0>

LCD_E

Y15
AB16
Y16
AA12
AB12
AB17
AB18
Y13
AB4

LCD_RS

Y14

LCD_RW

W13

Data bit DB7

Data bit DB6
Data bit DB5
Data bit DB4
Data bit DB3
When using the
four bit interface,
Data bit DB2
drive these signals
Data bit DB1
High.
Data bit DB0
Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
Register Select
0: Instruction register during write operation
Busy Flag During read operations
1: Data for read or write operations
Read/Write Control
0: Write, LCD accepts data
1: Read, LCD presents data

UCF LOCATION CONSTRAINT

NET "LCD_E"
LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_RS"
LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_RW"
LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<7>" LOC = "Y15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<6>" LOC = "AB16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<5>" LOC = "Y16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<4>" LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<3>" LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<2>" LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =
NET "LCD_DB<0>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW =

SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;

Power-On Initialization

The initialization sequence first establishes that the FPGA application wishes to
use the Four-bit data interface to the LCD as follows:
1. Wait 15 ms or longer, although the display is generally ready when the FPGA
finishes. Configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz
2. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
3. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz
4. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
5. Wait 100 s or longer, which is 5,000 clock cycles at 50 MHz
6. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
7. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz
8. Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles.
9. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz

Display Configuration
After the power-on initialization is completed, the four-bit interface is established.
The next part of the sequence configures the display:
1. Issue a Function Set command, 0x28, to configure the display for operation on
the Spartan kit.
2. Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
3. Issue a Display On/Off command, 0x0C to turn the display on and disable the
cursor and blinking.
4. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock
cycles) after
Issuing this command.

Write data to display

To write data to the display, specify the start address, followed by one or more data values.
Before writing any data, issue a Set DD RAM Address command to specify the initial seven bit
Address in the DD RAM. See Figure 5-3 for DD RAM locations.
Write data to the display using a Write Data to CG RAM or DD RAM command. The eight bit
Data value represents the look-up address into the CG ROM or CG RAM
The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to represent the
Associated character.
If the address counter is configured to auto-increment, as described earlier, the application can
Sequentially write multiple character codes, and each character is automatically stored and
Displayed in the next available location.
Continuing to write characters, however, eventually falls off the end of the first display line. The
Additional characters do not automatically appear on the second line because the DD RAM map
is not consecutive from the first line to the second.

Code:
`timescale 1ns / 1ps

module LCD(output reg SFD_8,

output reg SFD_9,
output reg SFD_10,
output reg SFD_11,
output reg LCD_E,
output reg LCD_RS,
output reg LCD_RW,
input clk,

output reg SF_CE0 // pin D16

);
reg[26:0] count;
reg[5:0] inst; //instruction to display
always@(posedge clk)
begin
count<= count+1;
case(count[26:21]) // increment to [0:20] is for delay for displaying data
//power on initialization
0: inst<= 6'h03;
1: inst<= 6'h03;
2: inst<= 6'h03;
3: inst<= 6'h02;
// display configuration command
4: inst<= 6'h02; //H28 to configure the display for operaion on spartan 3E kit
5: inst<= 6'h08;
6: inst<= 6'h00; //H06 to set the display to automatically increment the address pointer
7: inst<= 6'h07;
8: inst<= 6'h00; //To turn on the display and disable the cursor and blinking .
9: inst<= 6'h0C;
10: inst<= 6'h00; // To clear the previous display
11: inst<= 6'h01;

// data to be dispalyed

12: inst<= 6'h24; // upper 4bits nibbles

13: inst<= 6'h21; // lower 4 bits nibble for displaying A
14: inst<= 6'h24;
15: inst<= 6'h2D; // for M
16: inst<= 6'h24;
17: inst<= 6'h29; // For I
18: inst<= 6'h24;
19: inst<= 6'h2E; // for N
20: inst<= 6'h25;
21: inst<= 6'h25; // for U
22: inst<= 6'h24;
23: inst<= 6'h2C; // for L
24: inst<= 6'h22;
25: inst<= 6'h20; // for space
26: inst<= 6'h24;
27: inst<= 6'h29; // for I
28: inst<= 6'h25;
29: inst<= 6'h23; // for S
30: inst<= 6'h24;
31: inst<= 6'h2C; // for L
32: inst<= 6'h24;
33: inst<= 6'h21; // lower 4 bits nibble for displaying A
34: inst<= 6'h24;
35: inst<= 6'h2D; // for M

default: inst<=6'h10;
endcase

SF_CE0<=1;
LCD_E<=count[20];
LCD_RS<=inst[5]; //1-> data 0-> command
LCD_RW<=inst[4]; // 1->read 0->write
SFD_8<=inst[0];
SFD_9<=inst[1];
SFD_10<=inst[2];
SFD_11<=inst[3];
end
endmodule

Experiment - 9
Aim- Display and blink your name in 16*2 LCD using Verilog in SPARTAN
3E kit.
Code:
`timescale 1ns / 1ps

module LCD(output reg SFD_8,

output reg SFD_9,
output reg SFD_10,
output reg SFD_11,
output reg SFD_E,
output reg SFD_RS,
output reg SFD_RW,
input clk,
output reg SF_CE0 // pin D16
);
reg[26:0] count;
reg[5:0] inst; //instruction to display
always@(posedge clk)
begin
count<= count+1;
case(count[26:21]) // increment to [0:20] is for delay for displaying data

//power on initialization

0: inst<= 6'h03;
1: inst<= 6'h03;
2: inst<= 6'h03;
3: inst<= 6'h02;
//default: inst<=6'h10;
endcase
end

// display configuration command

always@ (posedge clk)
begin
inst= 6'h02; //H28 to configure the display for operaion on spartan 3 E kit
inst= 6'h08;
inst= 6'h00; //H06 to set the display to blink
inst= 6'h06;
inst= 6'h00; //To turn on the display and disable the cursor and blinking .
inst= 6'h0C;
inst= 6'h00; // To clear the previous display
inst= 6'h01;

// data to be dispalyed

inst= 6'h24; // upper 4bits nibbles

inst= 6'h21; // lower 4 bits nibble for displaying A
inst= 6'h24;
inst= 6'h2D; // for M
inst= 6'h24;
inst= 6'h29; // For I
inst= 6'h24;
inst= 6'h2E; // for N
inst= 6'h25;
inst= 6'h25; // for U
inst= 6'h24;
inst= 6'h2C; // for L

end
always@ (posedge clk)
begin
SF_CE0<=1;
SFD_E<=count[20];
SFD_RS<=inst[5]; //1-> data 0-> command
SFD_RW<=inst[4]; // 1->read 0->write
SFD_8<=inst[0];
SFD_9<=inst[1];

SFD_10<=inst[2];
SFD_11<=inst[3];
end
endmodule

Experiment 10
Aim- Design of a full adder using IP core (core generator &
architecture wizard)

Theory- You can create CORE Generator IP to instantiate in your HDL or schematic

designs. When you create IP, the CORE Generator software produces a combination of the
following files and places them in the specified directory for use in your ISE project:
Procedure to

add IP core-

1.
2.
3.
4.
5.
6.

New project ->New source file -> IP

(core generator & architecture wizard)
Give file name
View by function->select math function
-> select adder/subtractor ->next >finish.
Logic core window will appear
Select the option add and other
parameters like no of input bits, carry in,
carry out etc.
In the project window expand core
generator-> click on view HDL
instantiation template -> copy the
instance part of code.
ipcore your_instance_name (
.a(a), // input [1 : 0] a
.b(b), // input [1 : 0] b
.clk(clk), // input clk
.c_in(c_in), // input c_in
.s(s) // output [2 : 0] s);

7.
8.

Create a new source file and write the

code for full adder and instantiate the
code shown above.
assign pins-> Generate the programming
file-> and implement it on FPGA.

Code:
module adder(input clk, c_in, input a[1:0], b[1:0], output s[2:0] );
ipcore your_instance_name (
.a(a),

// input [1 : 0] a

.b(b),

// input [1 : 0] b

.clk(clk),

// input clk

.c_in(c_in),

// input c_in

.s(s)

// output [2 : 0] s

);
endmodule

Experiment 11
Aim- Use of system generator without chipscope for
adder.

Theory-

System Generator for DSP is the industrys leading high-level tool for designing high-

performance DSP systems using Xilinx All Programmable devices. With System Generator for DSP, create
production-quality DSP algorithms in a fraction of time compared to traditional RTL.

Develop highly parallel systems with the industrys most advanced FPGAs
Provide system modeling and automatic code generation from Simulink and MATLAB (The Mathworks, Inc.)
Integrates RTL, embedded, IP, MATLAB and hardware components of a DSP system
A key component of the Xilinx DSP Targeted Design Platform

System Generator for DSP is part of the Vivado System Edition Design Suite. With System Generator for DSP,
developers with little FPGA design experience can quickly create production quality FPGA implementations of DSP
algorithms in a fraction of traditional RTL development times.
Procedure-

1. All programs-> Xilinx design tools -> ISE design suite 14.1 ->
System generator-> system generator -> Simulink ->sink >scope (for output)-> write click on scope and add to the
model. Save the model at describe location with a file name.
2. Xilinx block set -> basic elements ->add gateway out, 2
gateway In, system generator.
3. Xilinx block set -> maths-> addsub.
4. Double click Gateway In-> change arithmetic type to
Unsigned. Set the number of bits and binary point.
5. Go to implementation tab and checks specify IOB location
constraint -> assign input pin location in FPGA. Repeat the
same for both inputs to adder.
6. Double click on gateway out -> checks specify IOB location
constraint -> assign input pin location in FPGA.
7. Double click on Addsub-> basic tab->click on addition option > output tab-> precision user defined -> arithmetic sign ->
unsigned -> select the number of bits and binary point.

8. Double click on system generator -> clock in -> A/O

compilation -> bitstream .Part->SPARTAN 3E-> XC3S500E->
-4 -> FG320.Hardware description language -> Verilog.
Clocking -> clock pin -> C9.
9. Now generate file.
For dumping into kit:
1.
2.

All programs-> Xilinx design tools -> ISE design suite 14.1
->ISE design tool -> 32- bit tools -> Impact.
Select the bit file and program as before(bit file name is
generated inside netlist directory) bitfile name is file_name
.bit.
Circuit Diagram :

Experiment 12
Aim- Use of system generator with chipscope for adder.
Theory- ChipScope Pro tool inserts logic analyzer, system analyzer, and virtual I/O low-profile software
cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft
processors. Signals are captured in the system at the speed of operation and brought out through the programming
interface, freeing up pins for your design. Captured signals are then displayed and analyzed using the ChipScope Pro
Analyzer tool.
The ChipScope Pro tool also interfaces with your Agilent Technologies bench test equipment through the ATC2
software core. This core synchronizes the ChipScope Pro tool to Agilents FPGA Dynamic Probe add-on option. This
unique partnership between Xilinx and Agilent gives you deeper trace memory, faster clock speeds, more trigger
options, and system-level measurement capability all while using fewer pins on the FPGA device.
The ChipScope Pro Serial I/O Toolkit provides a fast, easy, and interactive setup and debug of serial I/O channels in
high-speed FPGA designs. The ChipScope Pro Serial I/O Toolkit allows you to take bit-error ratio (BER)
measurements on multiple channels and adjust high-speed serial transceiver parameters in real-time while your serial
I/O channels interact with the rest of the system.

ChipScope Pro Key Features:

New RX Margin Analysis tool takes advantage of the Eye Scan feature in 7 Series FPGA transceivers enabling
our users to interactively characterize and optimize channel quality in both real time or view the test results offline
Analyze any internal FPGA signal, including embedded processor system buses
Inserts low-profile, configurable software cores either during design capture or after synthesis
All ChipScope Pro cores are available through the Xilinx CORE Generator System
Analyzer trigger and capture enhancements makes taking repetitive measurements easy to do
Enhancements to the Virtex-5 and Virtex-6 System Monitor console make it easier to access on-chip temperature,
voltage, and external sensor data
Change probe points without re-implementing the design
Debug over a network connection using remote debug, from your office to the lab, or across the globe
ChipScope core insertion and generation integrated into Project Navigator and PlanAhead tool flows
Add debug probes directly in HDL (VHDL and Verilog) or constraint files

ChipScope Pro Serial I/O Toolkit Key Features:

Fast and easy interactive setup and debug of FPGA serial I/O channels
Measure bit-error ratios (BER) on multiple channels simultaneously
Adjust high-speed serial transceiver parameters in real-time while your serial I/O channels are interacting with the
rest of the system
Built-in pattern generators and checkers, including many standard ITU standard patterns
IBERT (Bit Error Ratio Tester) sweep test plot GUI
Built-in graphical viewer of IBERT sweep test results for Virtex-6 GTX/GTH FPGA transceivers

Standalone graphical viewer for offline analysis of IBERT sweep test results for Kintex-7 FPGA GTX, Virtex-7
FPGA GTX, Virtex-6 FPGA GTX/GTH, Spartan-6 FPGA GTP, and Virtex-5 FPGA GTX transceivers

Requires only JTAG port access to your board, no extra pins needed for dedicated high-speed serial debug or
setup

Support Kintex-7 GTX, and Virtex-7 GTX/GTH/GTZ, and Artix-7 GTP RX Margin Analysis with two different scan
algorithms:

2D Full Scan: Scans all horizontal and vertical offset sampling points within the eye

PROCEDURE:
1.
2.

Open system generator

Select Gateway In, Gateway OUT, system generator, Chipscope and Scope from

3.

LIBRARY Browser.
Setting for step:

4.

Step time 1
Initial value 1

Final value 0
Sample time 0

Check interrupt vector parameter as I-D

Check enable zero crossing detection

Setting for gateway IN

1.
2.

5.

on FPGA, select NONE.

Setting for gateway OUT
3.

6.
7.

8.

9.

In Basic window ,Output type BOOLEAN, Sample period 1

In Implementation window, Check IOB timing constraint and give input location

In Implementation window, Check IOB timing constraint and give output location
on FPGA, select NONE.

No setting for scope.

Setting for Counter

In Basic window, Counter type FREE Running,Counter direction UP, Initial value
0, Step 1

In OUTPUT precision: select Unsigned

Number of Bits :4

Binary point : 0
Setting for CHIPSCOPE:

No. of trigger port :1

Display setting for trigger port :1

Number of match unit :1

Match type: basic

Number of data ports:1

Depth of capture Buffer:1024

Double click on system generator -> clock in -> A/O compilation -> bitstream .Part>SPARTAN 3E-> XC3S500E-> -4 -> FG320.Hardware description language -> Verilog.

Clocking -> clock pin -> C9 and FPGA clock period =20ns.Now generate file.
10. Dump program into FPGA KIT.