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  • Lint SPQ

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    Anil Kumar
    566 views3 pages
    The document lists various rules for detecting unsynthesizable VHDL code along with the associated severity level for each rule. It provides the rule name/identifier and sets the severity level for overriding existing rule severity levels. The rules check for issues like implicit sequential logic without a clock, multiple assignments to signals, incompatible port widths, undriven ports, combinational loops and other logic errors that prevent successful synthesis of the VHDL code to logic gates.

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    lint.spq

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    The document lists various rules for detecting unsynthesizable VHDL code along with the associated severity level for each rule. It provides the rule name/identifier and sets the severity level for overriding existing rule severity levels. The rules check for issues like implicit sequential logic without a clock, multiple assignments to signals, incompatible port widths, undriven ports, combinational loops and other logic errors that prevent successful synthesis of the VHDL code to logic gates.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    566 views3 pages

    Lint SPQ

    Uploaded by

    Anil Kumar
    The document lists various rules for detecting unsynthesizable VHDL code along with the associated severity level for each rule. It provides the rule name/identifier and sets the severity level for overriding existing rule severity levels. The rules check for issues like implicit sequential logic without a clock, multiple assignments to signals, incompatible port widths, undriven ports, combinational loops and other logic errors that prevent successful synthesis of the VHDL code to logic gates.

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    © All Rights Reserved
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    of 3

    // Unsynthesizable modeling style for a sequential logic.

    Clock and reset cannot


    be inferred
    -rules badimplicitSM1
    -overloadrules=badimplicitSM1+severity=Error
    // Unsynthesizable implicit sequential logic: states can only be updated on same
    clock phase
    -rules badimplicitSM2
    -overloadrules=badimplicitSM2+severity=Error

    // Both edges of the same variable are not allowed in the event control list
    -rules bothedges
    -overloadrules=bothedges+severity=Error
    // Parameter width does not match with the value assigned
    -rules ParamWidthMismatch-ML
    -overloadrules=ParamWidthMismatch-ML+severity=Info
    // Multiple assignments to a signal
    -rules sim_race02
    -overloadrules=sim_race02+severity=Race
    // Use same port index bounds in component instantiation and entity declaration
    -rules W110a
    -overloadrules=W110a+severity=Warning
    // Range of return type and return value of a function should be same
    -rules W416
    -overloadrules=W416+severity=Warning
    // The rule flags those uses of reset signals that are different from the reset
    line in the always construct s sensitivity list.
    -rules STARC05-2.3.1.6
    -overloadrules=STARC05-2.3.1.6+severity=Mandatory
    // Comparison of Real operands is not recommended
    -rules W292
    -overloadrules=W292+severity=Warning
    // A case choice is covered more than once in a case statement
    -rules W398
    -overloadrules=W398+severity=Error
    // Loop index is not of type integer
    -rules W480
    -overloadrules=W480+severity=Warning

    // Comparison to a tristate in a case statement is treated as false in synthesis


    .
    -rules W496b
    -overloadrules=W496b+severity=Error
    // Delay used without timescale compiler directive
    -rules CheckDelayTimescale-ML
    -overloadrules=CheckDelayTimescale-ML+severity=Info
    // An instance port connection has incompatible width compared to the port defin
    ition
    -rules W110
    -overloadrules=W110+severity=Error
    // Latch inferred
    -rules InferLatch
    -overloadrules=InferLatch+severity=Error
    // Use of blocking assignment in a sequential block
    -rules W336
    -overloadrules=W336+severity=Error
    // Use of non-blocking assignment in a combinational block
    -rules W414
    -overloadrules=W414+severity=Error
    // Undriven but loaded input terminal of an instance detected
    -rules UndrivenInTerm-ML
    -overloadrules=UndrivenInTerm-ML+severity=Error
    // Combinational loop exists
    -rules CombLoop
    -overloadrules=CombLoop+severity=Error
    // Flip-flop clock pin driven by a constant value
    -rules FlopClockConstant
    -overloadrules=FlopClockConstant+severity=Warning
    // Do not use a reset or set with both positive and negative polarity within the
    samedesign unit
    -rules W392
    -overloadrules=W392+severity=Warning
    // Variable/signal that does not infer a tristate and has multiple simultaneous
    drivers
    -rules W415
    -overloadrules=W415+severity=Error
    // Real variables are unsynthesizable

    -rules W294
    -overloadrules=W294+severity=Error
    // Undriven but loaded output port of a module detected
    -rules UndrivenOutPort-ML
    -overloadrules=UndrivenOutPort-ML+severity=Error
    // Do not write to input ports
    -rules W188
    -overloadrules=W188+severity=Error
    // A port with a range is redeclared with a different range
    -rules W423
    -overloadrules=W423+severity=Error
    // No asynchronous pin to pin paths.
    -rules Topology_02
    -overloadrules=Topology_02+severity=Warning

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