Birla Institute of Technology and Science

Pilani (Rajasthan)
Analog & Digital VLSI Design
Semester I (2005-2006) Comprehensive Examination
Date: 07/12/2005

Time: 3 hours

Marks: 70

State clearly any simplifying assumptions that you make

Use the following parameters unless otherwise stated :
VDD = 3V, Sio2 = 3.9, 0 = 8.85x10-14 F cm-1, tox = 9x10-9 m
nMOS : Vtn = 0.7 V, = 0.1, nCox = 90 A V-2
pMOS : Vtp = -0.8 V, = 0.2, pCox = 36 A V-2

Q1. Given below is a diagram of a V-to-I converter.

i)
ii)
iii)
iv)

Assuming an ideal opamp find the relationship between Vref and Iout.
If Vref = 2V what is the minimum Vout such that this circuit will work as expected?
Assume that the actual output voltage is 500mV above your answer in (ii). Find the
(W/L) of M1.
If the opamp gain is not infinite find the error in output current for the two cases where
the opamp gains are 1) 40 dB
and 2) 60 dB.

Q2. For the given circuit

i)
ii)
iii)
iv)

(1.5+1+2+3=7.5)

(1+2+2.5+5=10.5)

Identify the logic block in the digital domain.

Find the gain in the analog domain either by inspection or by the small signal model.
Assuming that the circuit is a symmetric inverter in the digital domain, find the output
dc bias for an input bias of VDD/2, and hence find the range of input dc bias for this
output bias.
Modify the circuit to increase its input bias range by adding a dc level shifter to the
circuit. Explain how this helps in achieving the same.

Q3. The circuit diagram for a 2 stage compensated opamp is given overleaf. The total power budget
is 6mW. For all devices Lmin = 0.5 m. The required output swing is 2.5 V.
(3+2+1.5+3+3.5+2+2+4=21)

i.
ii.

iii.
iv.
v.
vi.
vii.

viii.

Qualitatively state, with reasons, how you would divide a given gain for the opamp into the
2 stages with reference to 1) maximising bandwidth and 2) maximising the input bias limits
of the second stage.
Allocating a current of 1 mA to the second gain stage and roughly equal overdrives to the
two transistors, determine their (W/L)s. (Note that the gate-source capacitance of M5 is in
the signal path whereas that of M6 is not. This implies that the size of the former can be
much larger than that of the latter.)
Determine the aspect ratio of M3 and M4 for zero input referred systematic offset.
Calculate the aspect ratios of M1 and M2 so that the overall voltage gain of the opamp is
equal to 500.
Derive and calculate the value of the PSRR of the differential pair alone.
Explain how the compensation capacitor splits the poles far apart.
Find the frequency of the RHP zero that the compensation capacitor introduces into the
circuit. (The zero of the system is when the output of the system is absent/zero. Hence, you
can find the zero frequency by grounding the output node and writing the small signal KCL
at the node)
Prove that, for the compensated amplifier, if the zero is placed 10 times higher than the
unity gain frequency 0, then in order to achieve a phase margin of 60o, the second pole has
to be placed at least 2.2 times higher than 0.
(The phase shift provided by each pole and the RHP zero is given by tan -1(/x) where x is
the numerical value of the pole/zero. The phase margin is the phase left over 180 o, after
each pole/zero contribution)

Q4. This is the diagram of a switched capacitor integrator where 1 and 2 are non-overlapping
clocks.
(2+1.5+2.5+3.5=9.5)

i.
ii.
iii.

Write down the transfer function of the integrator in the z-domain by inspection or
otherwise.
Explain how it is stray-insensitive.
If fin is very high, qualitatively state what is to be done to the (W/L)s of the switches. How
does this make worse any non-idealities of the circuit?

iv.

If fin = 1 MHz, what is the minimum frequency that the clocks should have? Assuming an
RC circuit settles in 5, what is the required (W/L) of the switches? (Note that the input can
be considered as small signal for the purpose of this calculation)

Q5. Calculate the gain of the following circuit at frequencies close to dc and also at high
frequencies.
(3+3=6)