Q...1..

Write a function IsLittleEndian() which returns True if a n-bit processor is

Little Endian and False if the processor is Big Endian?
Q.2 What is the lowest positive integer whose Least significant digit when moved to
Most significant position the new number is 3/5(or 3/4 th ) of original. (110)
Q.7 To find maximum clock periods of four circuit of two cascaded D-f/fs having
different directions of clock and different position of buffers for delay. Also to find out
which circuit wont work reliably as shift register.
Q.8 If in a RISC system a pair of stmt is replaced by a single stmt, to reduce number of
stmt, it increases clock period by 10%. If such pairs of stmts occurs 20% of time in
source code and only 80% of these are of particular type to be replaced did the
performance actually improved.
Q.9 True and false (ten)
o LFSRs cant generate all zeros pattern.
o For each mealy M/C there is Moore and M/C and vice versa.
Q4. about physical and virtual address, which is greater?
Q5. TLB (Translation Lookahead Buffer) is used for ?
options:
1. L1 cache misses
2. L2 cache miss
3. some thing page miss (not remembered exactly)
Q10. Write a program in C or C++ to implement Stack and its functions
such as
isEmpty, isFull, Push, Pop, Init etc. (I think based on the question
given,
array implementation is sufficient)
Q3. elevator of 60 steps, one kid going up also climbs 15 steps during the
upward motion. another kid runs up in the downward elevator and reaches
top along with the first kid ?? how many steps are covered by second kid
(answer = 45 + 60 = 105)
Q4. find the minimal exp for a > b, where a=a0a1 and b=b0b1.
5 X 6 marks..
Q10.This is a Q from Low power design ( circuits )
The technology used for a design is changed from 0.13 Um to 0.09 Um and VDD from 1.2v to
1.0 v.
If Area of a chip is 81mm2 and Power consumed is 1w and maximum frequency is 500 MHz,in
the earlier 0.13 Um technology, what will be the Power consumed in the new Technology of
0.09Um and Vdd of 1.0v? what will be the area of the chip? What will be the maximum
frequency if the Power consumed is kept same ???

Q.Design a TLB structure for a page size of 64 KB and a physical address length of
64 bits and virtual address length of 32 bits. Why TLB misses less than that of
cache misses though TLB table size is less than the size of the cache?
7. An architect (like u) observed that in a processor configuration a sequence of
operations as shown below is happening often.
Add ra,rb->rc
add ra,rb->rc
Load rd<-(rc)
store rd->(rc)
So he advised a new addressing mode configuration as shown below to improve
the performance.
Load rd<-(ra+rb)
store rd->(ra+rb)
But the introduction of this increased the cycle time by 10%. The total load-store
instructions are only 20% of the total instructions and in those only 40% are of above
configuration. Will the new configuration proposed (by you) will result in performance
improvement or degradation. Give the reason.
9. Write a C code for removeNodeFromList() function in a double linked list. U can
find this in any Data Structure books.
Q4. find the minimal exp for a > b, where a=a0a1 and b=b0b1.