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INTRODUCTION TO VLSI
1.1GENERAL
VLSI stands for "Very Large Scale Integration". This is the field which involves packing more
and more logic devices into smaller and smaller areas. VLSI, circuits that would have taken boardfuls
of space can now be put into a small space few millimeters across! This has opened up a big
opportunity to do things that were not possible before. VLSI circuits are everywhere .your computer,
your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you. All this
involves a lot of expertise on many fronts within the same field, which we will look at in later sections.
VLSI has been around for a long time, but as a side effect of advances in the world of computers, there
has been a dramatic proliferation of tools that can be used to design VLSI circuits. Alongside, obeying
Moore's law, the capability of an IC has increased exponentially over the years, in terms of computation
power, utilisation of available area, yield. The combined effect of these two advances is that people can
now put diverse functionality into the IC's, opening up new frontiers. Examples are embedded systems,
where intelligent devices are put inside everyday objects, and ubiquitous computing where small
computing devices proliferate to such an extent that even the shoes you wear may actually do
something useful like monitoring your heartbeats. Integrated circuit (IC) technology is the enabling
technology for a whole host of innovative devices
Jack Kilby and Robert Noyce received the 2000 Nobel Prize in Physics for their invention of the
integrated circuit; without the integrated circuit, neither transistors nor computers would be as
important as they are today. VLSI systems are much smaller and consume less power than the discrete
components used to build electronic systems before the 1960s. Integration allows us to build systems
with many more transistors, allowing much more computing power to be applied to solving a problem.
Integrated circuits are also much easier to design and manufacture and are more reliable than discrete
systems; that makes it possible to develop special-purpose systems that are more efficient than generalpurpose computers for the task at hand.
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Three Categories:
1. Analog:
Small transistor count precision circuits such as Amplifiers, Data converters, filters, Phase
Locked, sensors etc
extra
features
like
games,
calendar,etc.
electronics are usually smaller, more flexible, and easier to service. In other cases electronic systems
have created totally new applications. Electronic systems perform a variety of tasks, some of them
visible, some more hidden:
Personal entertainment systems such as portable MP3 players and DVD players perform
sophisticated algorithms with remarkably little energy.
Electronic systems in cars operate stereo systems and displays; they also control fuel injection
systems, adjust suspensions to varying terrain, and perform the control functions required for
anti-lock braking (ABS) systems.
Digital electronics compress and decompress video, even at high definition data rates, on-thefly in consumer electronics.
Low-cost terminals for Web browsing still require sophisticated electronics, despite their
dedicated function.
Personal computers and workstations provide word-processing, financial analysis, and games.
Computers include both central processing units (CPUs) and special-purpose hardware for disk
access, faster screen display, etc.
Medical electronic systems measure bodily functions and perform complex processing algorithms to
warn about unusual conditions. The availability of these complex systems, far from overwhelming
consumers, only creates demand for even more complex systems. The growing sophistication of
applications continually pushes the design and manufacturing of integrated circuits and electronic
systems to new levels of complexity. And perhaps the most amazing characteristic of this collection of
systems is its variety as systems become more complex, we build not a few general-purpose computers
but an ever wider range of special-purpose systems. Our ability to do so is a testament to our growing
mastery of both integrated circuit manufacturing and design, but the increasing demands of customers
continue to test the limits of design and manufacturing.
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While we will concentrate on integrated circuits in this book, the properties of integrated
circuits what we can and cannot efficiently put in an integrated circuitlargely determine the
architecture of the entire system. Integrated circuits improve system characteristics in several critical
ways. ICs have three key advantages over digital circuits built from discrete components:
Size. Integrated circuits are much smallerboth transistors and wires are shrunk to micrometer sizes,
compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages
in speed and power consumption, since smaller components have smaller parasitic resistances,
capacitances, and inductances.
Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip than they can
between chips. Communication within a chip can occur hundreds of times faster than communication
between chips on a printed circuit board. The high speed of circuits on-chip is due to their small size
smaller components and wires have smaller parasitic capacitances to slow down the signal.
Power consumption. Logic operations within a chip also take much less power. Once again, lower
power consumption is largely due to the small size of circuits on the chipsmaller parasitic
capacitances and resistances require less power to drive them.
Reduced cost. Reducing the number of components, the power supply requirements, cabinet costs,
and so on, will inevitably reduce system cost. The ripple effect of integration is such that the cost of a
system built from custom ICs can be less, even though the individual ICs cost more than the standard
parts they replace. Understanding why integrated circuit technology has such profound influence on the
design of digital systems requires understanding both the technology of IC manufacturing and the
economics of ICs and digital systems.
pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have
integrated peripheral Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs)
with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.[5] Such devices
blur the line between an FPGA, which carries digital ones and zeros on its internal programmable
interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its
internal programmable interconnect fabric.
chip to discriminate between two tones, utilising analogue features of the digital chip. The application
of genetic algorithms to the configuration of devices like FPGAs is now referred to as Evolvable
hardware .
applications than they have been historically used for, to which the company attributes the growing
number of FPGA design starts (see History). Some FPGAs have the capability of partial reconfiguration that lets one portion of the device be re-programmed while other portions continue
running.
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1.7 APPLICATIONS
Applications of FPGAs include digital signal processing, software-defined radio, aerospace and
defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition,
cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection and a
growing range of other areas. FPGAs originally began as competitors to CPLDs and competed in a
similar space, that of glue logic for PCBs. As their size, capabilities, and speed increased, they began to
take over larger and larger functions to the state where some are now marketed as full systems on chips
(SoC). Particularly with the introduction of dedicated multipliers into FPGA architectures in the late
1990s, applications which had traditionally been the sole reserve of DSPs began to incorporate FPGAs
instead. Traditionally, FPGAs have been reserved for specific vertical applications where the volume of
production is small. For these low-volume applications, the premium that companies pay in hardware
costs per unit for a programmable chip is more affordable than the development resources spent on
creating an ASIC for a low-volume application. Today, new cost and performance dynamics have
broadened the range of viable applications.
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with different base dies customised by both metal and polysilicon layers. Some base dies include RAM
elements.
model (see Simics, for example). Each technique has advantages and disadvantages, and often
several methods are used.
Logic synthesis transforms the RTL design into a large collection of lower-level constructs
called standard cells. These constructs are taken from a standard-cell library consisting of precharacterized collections of gates (such as 2 input nor, 2 input NAND, inverters, etc.). The
standard cells are typically specific to the planned manufacturer of the ASIC. The resulting
collection of standard cells, plus the needed electrical connections between them, is called a
gate-level netlist.
The gate-level netlist is next processed by a placement tool which places the standard cells onto
a region representing the final ASIC. It attempts to find a placement of the standard cells,
subject to a variety of specified constraints.
The routing tool takes the physical placement of the standard cells and uses the netlist to create
the electrical connections between them. Since the search space is large, this process will
produce a sufficient rather than globally optimal solution. The output is a file which can be
used to create a set of photomasks enabling a semiconductor fabrication facility (commonly
called a 'fab') to produce physical ICs.
Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In
the case of a digital circuit, this will then be further mapped into delay information, from which
the circuit performance can be estimated, usually by static timing analysis. This, and other final
tests such as design rule checking and power analysis (collectively called signoff) are intended
to ensure that the device will function correctly over all extremes of the process, voltage and
temperature. When this testing is complete the photomask information is released for chip
fabrication.
These steps, implemented with a level of skill common in the industry, almost always produce a
final device that correctly implements the original design, unless flaws are later introduced by the
physical fabrication process. The design steps (or flow) are also common to standard product design.
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The significant difference is that standard-cell design uses the manufacturer's cell libraries that have
been used in potentially hundreds of other design implementations and therefore are of much lower risk
than full custom design. Standard cells produce a design density that is cost effective, and they can also
integrate IP cores and SRAM (Static Random Access Memory) effectively, unlike Gate Arrays.
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CHAPTER - 2
LITERATURE REVIEW
A. 7-Segments Decoder
A 7-segments decoder is able to convert the logic states of inputs into seven bits of outputs and displays
in7-segments display. It is used widely in devices where its main function is to display numbers from a
digital circuitry. An example of these devices includes calculators, displays in elevator, digital timers,
digital clocks and etc.
There are many types of decoders such as 2-4 decoder, 3- 8 decoder and 4-16 decoder. Since there are
ten decimal numerals (09) to be displayed in the 7-segments display, a 4-16 decoder was used.
The structure of a 7-segments display is shown in Fig. 1. It is used to display decimal numerals in
seven segments and each segment is represented by an alphabet a to g. By setting the required
segments to be turned on, the desired decimal numeral can be displayed on the 7-segments display
B. IC Design
IC layouts are built from three basic components which are the transistors, wires and vias. During the
design of the layouts, the design rule has to be considered.
Design rules govern the layout of individual components and the interaction between those
components. When designing an IC, designers tend to make the components as small as possible
enabling implementation of as many functions as possible onto a single chip. However, since the
transistors and wires are extremely small, errors may happen during the fabrication process. Hence,
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design rules are created and formulated to minimise problems during fabrication process and helps to
increase the yield of correct chips to a suitable level. Therefore, it is important to adhere to the design
rules during layout design.
corresponding devices are checked. Besides that, the sizes of the device will also be checked including
the width and length of transistors, sizes of resistors and capacitors.
The LVS will also identify the extra components and signals that have not been included in the
schematic, for example, floating nodes.
In Electric VLSI Design System, this type of checking is known as the Network Consistency Checking
(NCC) as is able to compare any two circuits, which includes two layouts or two schematics
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CHAPTER - 3
TASKS PERFORMED
3.1: Fundamentals in Digital Abstraction
3.1.1: Why digital?
In classical physics, measureable quantities that we might use to represent information such as
position, voltage, frequency, force, and many others, have values that vary continuously over some
range of possibilities. The values of such variables are real numbers: even over a restricted range. For
example the interval between 0 and 1, the number of possible values of a real variable is infinite,
implying that such a variable might carry arbitrarily large amounts of information. This may appear
as an advantage of continuous variables, but it comes at a serious cost. It obscures
the actual information content of the variable. This limitation of the engineering discipline
surrounding analog systems results in representation of information in digital format.
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The minimum ON-state gate voltage required to ensure that the MOSFET remains ON when
carrying the selected drain current can be determined from the V-I transfer curves above in figure
3.3.1.1. When VIN is HIGH or equal to VDD, the MOSFET Q-point moves to point A along the load line.
The drain current ID increases to its maximum value due to a reduction in the channel
resistance. ID becomes a constant value independent of VDD, and is dependent only on VGS. Therefore,
the transistor behaves like a closed switch but the channel ON-resistance does not reduce fully to zero
due to its RDS(on) value, but gets very small.
Likewise, when VIN is LOW or reduced to zero, the MOSFET Q-point moves from point A to
point B along the load line. The channel resistance is very high so the transistor acts like an open
circuit and no current flows through the channel. So if the gate voltage of the MOSFET toggles
between two values, HIGH and LOW the MOSFET will behave as a single-pole single-throw
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(SPST) solid state switch. The MOSFET basically has two regions, cut-off region and saturation
region.
(3.4.1)
In this expression fc is the clock frequency and is the switching probability, the so-called activity
ratio. A more universal measure is the switching energy which is related to the power consumption
as seen in equation 3.4.2.
Es=CL(VDD)2+(1/fc)IoffVDD
Therefore
Ptot=fcEs
(3.4.3)
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(3.4.2)
The advantage of using the switching energy rather than the total power consumption is
that Es is independent of the system throughput. For example, when pipelined architectures are
considered the power consumption varies with the architectural changes, but the switching energy
does not and is therefore the better candidate to optimize.
The speed of a digital circuit can be characterized in two ways: the delay time td which is assumed
as and the maximum clock frequency fc,max which is given by
Td=CLVDD / Ion
(3.4.4)
fcmax= 1 / tdld
(3.4.5)
In the equation 3.4.5 the logic depth ld is the number of stages through which a switching event must
propagate during one clock cycle.
Clearly, a system is most efficient when operated at the maximum clock frequency. Combining
(3.4.2), (3.4.4), and (3.4.5) assuming that fc = fc,max yields the following fundamental equation:
Es =CL(VDD)2[1+(ld / )(Ioff/Ion)]
(3.4.6)
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Transistors are built on a Silicon (semiconductor) substrate. Pure silicon has no free carriers
and conducts poorly. Dopants are added to increase conductivity: extra electrons (n-type) or extra holes
(p-type).
MOS structure is created by superimposing several layers of conducting, insulating and
transistor forming materials. Metal gate has been replaced by polysilicon or poly in modern
technologies.
There are two types of MOS transistors:
nMOS : Negatively doped silicon, rich in electrons.
pMOS : Positively doped silicon, rich in holes.
CMOS: Both type of transistors are used to construct any gate.
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The output of combinational circuit at any instant of time depends only on the levels present at
input terminals.
The combinational circuits do not use any memory. The previous state of input does not have
any effect on the present state of the circuit.
A combinational circuit can have an n number of inputs and m number of outputs as shown in
figure 3.6.1 and its classification can be seen in figure 3.6.2.
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Figure 3.6.2: Classification of combinational logic circuit Few important combinational circuits
are elaborated as follows.
Examples of combinational circuits are Half Adder, Full Adder, Multiplexers, Demultiplexer, Decoder,
encoder etc.
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The word Sequential means that things happen in a sequence, one after another and in
Sequential Logic circuits, the actual clock signal determines when things will happen next. Simple
sequential logic circuits can be constructed from standard Bistable circuits such as: Flip-flops,
Latches and Counters and which themselves can be made by simply connecting together universal
NAND Gates and/or NOR Gates in a particular combinational way to produce the required sequential
circuit. Figure 3.7.1 shows the representation of sequential logic circuit.
2. Clock Driven synchronous circuits that are synchronized to a specific clock signal.
3. Pulse Driven This is a combination of the two that responds to triggering pulses.
Sequential logic circuits return back to their original steady state once reset and sequential
circuits with loops or feedback paths are said to be cyclic in nature. Sequential circuits changes
occur only on the application of a clock signal making it synchronous, otherwise the circuit is
asynchronous and depends upon an external input. To retain their current state, sequential circuits rely
on feedback and this occurs when a fraction of the output is fed back to the input. The classification
of sequential circuits is seen in figure 3.7.2.
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A master-clock generator is used to generate a periodic train of clock pulses. These clock pulses
are distributed throughout the system. Clocked sequential circuits are most commonly used. The
memory elements are flip-flops. These flip-flops are the binary cells capable of storing one bit of
information. It generates two outputs: one for the normal value and one for the complement value. It
also maintains a binary state indefinitely until directed by an input signal to switch states.
3.8: Synchronization
System/Application level
File level
enable smooth manufacturing process, e.g. ordering material when enterprise is running out stock;
synchronizing customer orders with manufacturing process, etc. There are thousands of examples
from real life when the real time is becoming either advantage or a must to be successful and
competitive.
3) Security
Different systems may have different policies to enforce data security and access levels. Even
though the security is maintained correctly in the source system which captures the data, the security
and information access privileges must be enforced on the target systems as well to prevent any
potential misuse of the information. This is particularly an issue when handling personal information
or any piece of confidential information under Non Disclosure Agreement (NDA). Any intermediate
results of the data transfer as well as the data transfer itself must be encrypted.
4) Data Quality
Maintaining data in one place and sharing with other applications is best practice in managing and
improving data quality. This prevents inconsistencies in the data caused by updating the same data in
one system.
5) Performance
The data synchronization process consists basically of five phases:
1.
2.
Data transfer
3.
Data transformation
4.
Data transfer
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5.
The setup time is the interval before the clock where the data must be held stable.
The hold time is the interval after the clock where the data must be held stable. Hold time can
be negative, which means the data can change slightly before the clock edge and still be properly
captured. Most of the current day flip-flops have zero or negative hold time.
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The combinational logic between the flip-flops should be optimized to get minimum delay.
Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be
fast there by helping fixing setup violations.
One can add lockup-latches (in cases where the hold time requirement is very huge, basically to
avoid data slip).
3.10: Metastability
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Whenever there are setup and hold time violations in any flip-flop, it enters a state where its
output is unpredictable: this state is known as metastable state (quasi stable state); at the end of
metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as
metastability. In the figure 3.10.1 below Tsu is the setup time and Th is the hold time. Whenever the
input signal D does not meet the Tsu and Th of the given D flip-flop, metastability occurs.
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Causes of metastability:
When the setup time and hold time violation occurs, then metastability occurs, so we have to see
when signals violate this timing requirement:
When the clock skew/slew is too much (rise and fall time are more than the tolerable values).
When interfacing two domains operating at two different frequencies or at the same frequency
but with different phase.
When the combinational delay is such that flip-flop data input changes in the critical window
(setup + hold window).
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This is the first major step in getting the layout done, and is the most important one. Floorplan
determines the chip quality. At this step, we decide the size of our chip/block, allocates power routing
resources, place the hard macros, and reserve space for standard cells. Every subsequent stage like
placement, routing and timing closure is dependent on how good the floorplan is. In a real time
design, many iterations are performed before arriving at an optimum floorplan.
1. Core Boundary
Floorplan defines the size and shape of the chip/block. A top level digital design will have a
rectangular/square shape, whereas a sub block may have rectangular or rectilinear shapes. Core
boundary refers to the area where one will be placing standard cells and other IP blocks. One may
have power routing spaces allocated outside the core boundary. For a full chip, we also have IO
buffers and IO pads placed outside the core boundary.
In PnR tool, floorplanning can be controlled by various parameters:
Aspect ratio: This is the ratio of height divided by width and determines whether we get a square or
rectangular floorplan. An aspect ratio of 1 gives a square floorplan.
Core utilization: Core utilization = (standard cell area+ macro cells area)/ total core area
A core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas 20%
is left free for routing.
Boundary: We need to specify a boundary and the tool can honour it. This comes in handy when we
have an existing boundary from a previous version. When we specify Boundary as the control
parameter, both aspect ratio and core utilization are irrelevant. The tool gives a report of the
utilization for the current boundary specified.
2. IO Placement/Pin placement
In a digital-top design, we need to place IO pads and IO buffers of the chip. Take a rectangular or
square chip that has pads in four sides. To start with, one may get the sides and relative positions of
the PADs from the designers. We also get a maximum and minimum die size according to the
package we have selected. Perl script is used to place IO once the chip size is decided.
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3. Macro placement
Once the size & shape of the floorplan is ready and initialized, thereby creating standard cell
rows, then place the macros. Do not use any auto placement. Flylines in the tool will show the
connection between the macros and standard cells or IOs.
i.
Use flylines and make sure to place blocks that connects each other closer
ii.
For a full-chip, if hard macros connect to IOs, place them near the respective IOs.
iii.
the
power
rings
using
IC
Compiler
can
be
done
as
follows:
First decide the trunks that supply power to the core then make sure that all the hard macros have
sufficient rings/straps around it to hook into the PG trunks. As usual, a robust power structure will
take iterations and IR drop analysis at a later stage, but a close approximation can be arrived at the
initial stages.
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3.13: PLACEMENT
Placement does not just place the standard cells available in the synthesized netlist. It also
optimizes the design, thereby removing any timing violations created due to the relative placement on
die.
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6. Placement blockages:
The utilization constraint is not a hard rule, and if you want to specifically avoid placement in
certain areas, use placement blockages.
7. Scan chain reordering:
In a less complex design, usually scan reordering is carried out. However, sometimes it may
become difficult to pass scan timing constraints once the placement is done. The scan flip flop
placements may create lengthier routes if the consecutive flops in scan chain are placed far apart due
to a functional requirement. In this case, the PnR tool can reconnect the scan chains, to make routing
easier. A prerequisite for this option is a scan DEF for the tool to recognize the chains.
8. TIE cells
In your netlist, some unused inputs are tied to either VDD/VSS (or logic1/logic0). It is not
recommended to connect a gate directly to the power network, so one can use TIEHI or TIELO cells
if available in the library for the same. These are single pin cells which effectively ties the pin it
connects high or low. After placement, dump out a netlist and search for direct pin connections to the
PG rails (other than power pins).
3.14: CLOCK TREE SYNTHESIS
Clock Tree Synthesis is a process which makes sure that the clock gets distributed evenly to
all sequential elements in a design. The goal of CTS is to minimize the skew and latency. The
placement data will be given as input for CTS, along with the clock tree constraints. The clock tree
constraints will be Latency, Skew, Maximum transition, Maximum capacitance, Maximum fan-out,
list of buffers and inverters etc.
The clock tree synthesis contains clock tree building and clock tree balancing. Clock tree
can be build by clock tree inverters so as to maintain the exact transition (duty cycle) and clock tree
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balancing is done by clock tree buffers (CTB) to meet the skew and latency requirements. Less clock
tree inverters and buffers should be used to meet the area and power constraints.
Standard Clock Tree Synthesis engines are driven by timing closure and, hence, are not PVT
(process/voltage/temperature) variation aware. They are used to fix setup/hold violations by adjusting
the clock skew, adding, removing, and swapping buffers, or exploiting different clock wire lengths
and levels and so on. As a result, the skew sensitivity with respect to PVT variations cannot be kept
low, since there are several contributors originating from different physical phenomena.
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Another problem with a clock mesh, especially when conceived at top level, is the large
amount
of
power
consumed,
which
means
that
dynamic
power
drop
is
likely.
Other techniques found in the literature, such as PLL/DLL de-skewing, are not suited for high
precision, low uncertainty clock distribution, mainly due to added jitter of PLL/DLL circuitry.
II.
III.
IV.
V.
VI.
VII.
VIII.
We can replace buffers with two inverters placing farther apart so that delay can adjust.
We can also reduce some larger than normal capacitance on a cell output pin.
We can upsize the cells to decrease the delay through the cell.
LVT cells
Hold Fixing:
It is well understood hold time will be large if data path has more delay. So we have to add
more delays in data path.
I.
II.
III.
IV.
V.
Decreasing the size of certain cells in the data path, It is better to reduce the cells n capture path
closer to the capture flip flop because there is less chance of affecting other paths and causing new
errors.
VI.
By increasing the wire load model, we can also fix the hold violation.
3.15: ROUTING
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The routing process determines the precise paths for interconnections. This includes the standard cell
and macro pins, the pins on the block boundary or pads at the chip boundary. After placement and
CTS, the tool has information about the exact locations of blocks, pins of blocks, and I/O pads at chip
boundaries. The logical connectivity as defined by the netlist is also available to the tool. In routing
stage, metal and vias are used to create the electrical connection in layout so as to complete all
connections defined by the netlist. Now, to do the actual interconnections, the tool relies on some
Design Rules.
Most of the routers available are grid based routers. There are routing grids defined for the
entire layout. Consider it like a graph as below. For grid based routers, there are also preferred
routing directions defined for each metal layer. e.g. Metal1 has a preferred direction of horizontal,
metal2 has preferred routing direction of vertical and so on. So, in the whole layout, metal1 routing
grids will be drawn (superimposed) horizontally with metal1 wire pitch and metal2 grids will be
drawn vertically with metal2 wire pitch between each.
This can be the minimum spacing of the metal itself, but is usually a value greater than the
minimum spacing. This is calculated by taking into account the via dimension as well, so that no two
adjacent wires on the grid create any DRC violation even when there are vias present.
Iavg * R
Static IR drop is caused by the resistance of the metal wires comprising the power distribution
network. It occurs due to current flow when the circuit is at a steady state i.e. no inputs are
switching.
3.17.1.2: Dynamic IR drop
In dynamic IR drop time-varying voltage V(t) drop on power/ground network. Dynamic IR drop
additionally models the following
Package inductance
Decoupling Capacitance
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(a)
(b)
Figure 3.17.2.1 (a) Insertion of decoupling capacitor (b) supply voltage within tolerance
level after decap insertion
There are 2 types of decaps:
1. White-space decaps figure 3.17.2.2(a): consists of NMOS transistors placed between the logic blocks
in the open area on a chip.
2. Standard cell decaps figure 3.17.2.2(b): consists of cross coupled PMOS and NMOS transistors
placed within the logic blocks.
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Figure 3.17.2.2. (a) White Space Decaps. (b) Standard Cell Decaps.
Selective Glitch Reduction: Whenever there is a transition at the output of any logic it is due to two
reasons:
1. When there is transition of input signals resulting in desired output.
2. When there is transition of unnecessary logic resulting in undesired output (spurious transition).
These unnecessary signals at the output of logic are known as glitches.
Dynamic power consumption = NTPT
NT = number of switching transitions through the logic.
PT = average power consumption per switching transition.
The motive of selective glitch reduction technique is to reduce N T through glitch elimination in
selected combinational cells which are contributing to peak IR drop.
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STA tool is the routed netlist, clock definitions (or clock frequency) and external environment
definitions.
Figure 3.18.1 shows the basic functionality of static timing analysis. Given a design along with a
set of input clock definitions and the definitions of external environment of the design, the purpose of
static timing analysis is to validate that the design can operate safely at the specified frequency of
clocks without any timing violations.
The entire design is analyzed once and required timing checks are performed for all possible
paths of the design. Thus STA is a complete and exhaustive method for verifying the timing of a
design.
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In figure 3.18.3 it is very clear that the clock path starts from the input port/pin of the design
which is specific for the Clock input and the end point is the clock pin of a sequential element. In
between the Start point and the end point there may be lots of Buffers/Inverters/clock divider.
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All paths in the design may not run always in worst case delay.
Clock related all information has to be fed to the design in the form of constraints.
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1) Clock gating involves disconnecting of the clock from a device it drives when the data going
into the device is not changing. This technique is used to minimize dynamic power.
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As technologies have shrunk, leakage power consumption has grown exponentially, thus
requiring more aggressive power reduction techniques to be used. Similarly, increase in clock
frequency have caused dynamic power consumption of the devices to outstrip the capacity of the
power networks that supply them, and this becomes especially acute when high power consumption
occurs in very small geometries, as this is a power density issue as well as a power consumption
issue.
Several advanced low power techniques have been developed to address these needs. The most
commonly adopted techniques today are:
1) Multi-voltage supply (MVS): The operation of different areas of a design at different voltage
levels. Only specific areas that require a higher voltage to meet performance targets are connected to
the higher voltage supplies. Other portions of the design operate at a lower voltage, allowing for
significant power savings. Multi-voltage supply is generally a technique used to reduce dynamic
power, but the lower voltage values also cause leakage power to be reduced.
2) Power gating: The complete shut off of supply nets to different areas of a design when they are
not needed (also known as MTCMOS or power shutdown). Since the power has been completely
removed from these shutdown areas, the power for these areas is reduced essentially to zero. This
technique is used to reduce leakage power.
It is very common to see multi-voltage and power gating used together on the same design, whereby
different regions operate at different voltages, and one or more of those regions can also be shutdown.
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CHAPTER - 4
REFLECTION NOTES (Specific Outcomes)
Experience and Assessment:
The experience at the company was satisfactory, the people work in co-ordination and the company
environment is very safe and studios. The reason to choose this company was that it was offering
internship in VLSI which is my core specialization in PG degree and I wanted to benefit from this
experience, also I got to learn new tools like Electric, Symica DE and Microwind.
I used to spend nearly 5 to 6 hours daily in the company trying out with different circuits
and making their layouts manually. I thank my guide who was always there by my side throughout my
internship process giving me advice, feedback and tips on how the people work in an industry
environment.
Some technical outcomes are:
VLSI chips application is mainly for mobile devices which are expected to have longer
battery life. Additionally, the new electronic products require increased functionality, high performance
and integration of large number of components within a single chip leading to power-consumed
designs. So how to make the chip lower power is very important for the company.
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A 7-segments decoder is able to convert the logic states of inputs into seven bits of outputs
and displays in 7-segments display. It is used widely in devices where its main function is to display
numbers from a digital circuitry. Examples of these devices includes calculators, displays in elevator,
digital timers, digital clocks and etc. There are many types of decoders such as 2:4 decoder, 3:8
decoder and 4:16 decoder. Since there are ten decimal numerals (09) to be displayed in the 7segments display, a 4:16 decoder was used.
The structure of a 7-segments display is shown in Fig. 4.2.1. It is used to display decimal numerals
in seven segments and each segment is represented by an alphabet a to g. By setting the required
segments to be turned on, the desired decimal numeral can be displayed on the 7-segments display. The
logic diagram of 7-segments decoder is shown in Fig. 4.2.2.
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However, since the transistors and wires are extremely small, errors may happen during the
fabrication process. Hence, design rules are created and formulated to minimize problems during
fabrication process and helps to increase the yield of correct chips to a suitable level.
FINDINGS
In my implementation project, an IC layout of a decoder that displays the decimal numeral in
7-segments display was designed. It consists of NOT gates, 2-input NAND gates, 3-input NAND
gates, 4-input NAND gates, 2-input AND gates and 3-input AND gates. The schematic circuits and
layouts of all these gates were drawn and simulated using MicroWind VLSI Design System.
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Figure 4.3.3.5 shows the 4-input NAND gate symbol and spice code. The code was
required and used to complete the simulation process. The input wire are named as a, b, c andd;
whereas output wire is named as y. Simulation result of the 4-input NAND gate. If all the inputs of
the 4-input NAND gate are 1, the output will be 0. Meanwhile, whenever there is 0 among the
inputs, the output will be 1. In addition, due to the capacitance, the fall in the waveform actually
indicates a logic 0 whereas the rise in waveform indicates a logic 1. From the waveform
generated, as shown in Fig. 11, the results are match with the theoretical 4-input NAND gate. It can
be deduced that the 4-input NAND gate drawn by using MicroWind VLSI Design System operates
correctly.
and D is the most significant bit. The input E is acting as an enable signal, such that when E is
1(high), all the 7 outputs will be displayed depend on the inputs else all the 7 outputs will remain
0(low)
Since it is a 7-segment decoder, seven outputs will be needed. These outputs are labelled
as a, b, c,d, e, f and g.
Figure 4.4.1 Schematic diagram and Icon View of 7-Segment Decoder in MicroWind.
In reference to the truth table of the binary-convert-decimal, as shown in Table I, the designed
decoder is match with the theoretical work and said to function as expected.
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5. APPLICATIONS
As the technology advances, the time factor becomes an important element in many of the
fields. The time is usually notified soon when displayed in digital format. Hence 7 Segment Decoder
is applicable in many areas to display time and other field related information. Few of them are listed
below:
1) Railway Stations: To display time of arrival and departure of trains and train number,7-Segment
decoder based LED Display is very much useful.
2) Big Organizations: For example in a cricket match, to display scored runs, lost wickets and time
of start of the match etc.
3) Wrist Watch: When time need to display in digital format, technology use 7-Segment Decoder in
wrist watches.
4) Calculators: Since all the calculated values are in number format from 0 to 9, hence calculators
are also use 7-Segment Decoder based LED Display.
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5) Bus Stands: To display departure and arrival time of each bus can be displayed using 7-Segment
Decoder based LED Display.
6) Lifts: In order to display floor numbers, 7-Segment decoder based LED Display is much
applicable.
6. CONCLUSION
In conclusion, 7-segments decoder IC is to display the numbers in 7 segments. It converts the
binary input to 7 bits according to the input. The IC layout of the decoder is designed and
successfully proves that the output waveforms generated matches the theoretical decoder.
In addition, the open source MicroWind VLSI Design System is a user friendly software to be
used in designing a layout of 7-segments decoder. It is expected that the software is able to cope with
more complex digital IC design with its suite of verification and design tools.
The internship program was quite beneficial to me. I learned various technical aspects which
were included in our curriculum, apart from these there were non-technical areas in which I
developed a lot. It was a great experience working with professionals and interacting with them,
learning from their experience and working under their guidance. I also enjoyed complying with the
protocols of the organization. I learned professionalism on whole.
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7. BIBLIOGRAPHY
[1] About Electric. (May 2013). [Online]. Available: www.staticfreesoft.com/electric.html
[2] R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, John Wiley & Sons,
2010, pp. 6-12.
[3] M. M. Forrest, Understanding Digital Computers, Radio Shack, 1987.
[4] S. H. Teen and S. Y. Lee, CMOS IC layout design: 7-segments counter, Lecture Notes on
Photonics and Optoelectronics, vol. 1, no. 2, pp. 52-55, December 2013.
[5] A. P. Douglas and E. Kamran, Basic VLSI Design, 3rd ed., Prentice Hall, 1994, pp. 72-76.
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