23 08 2013 04 29 46 Opamp ST Aug 23rd PDF

Institute of Engineering Studies (IES,Bangalore)
Page 1 of 31
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Subject: Analog Electronics
Total Questions :120
Practice Questions for Classroom & Postal Series Students
Topic: Op Amp
Classroom & Postal courses students can check solution of any Qn in online with Q.ID provided for each Qn eg., QAnaA021
Common Data for Q1 and Q2 is given below
1)Find input resistance

[B] 3 K
[D]1 K
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[A] 2 K
[C]6.47 K
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Consider op-amp ideal
2)Find the ratio
. [QAnaA022] .. 2 Marks (
[B] 2.66
[D]2.5
(IE
[A] 3
[C]1.66
3)For an amplifier having a slew rate of 60 v/sec, what is the highest frequency at which a 20 (peak to
peak) sine wave can be produced at the output ?
= 9.8 mA and _
[B] 1 MHz
[D]95.5 kHz
= 0.7V
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4)Find the value of R to get _
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[A] 47.74 kHz

[C]20 kHz
[A] 1.02 k
[C]949
5)For a type 741 op- amp ( = 9.5 A and

[A] 0.92 V/ sec
[C]0.56 V/ sec
[B] 640.3
[D]378
= 30 PF) then the slew rate is

[B] 0.63 V/ sec
[D]0.72 V/ sec
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Page 2 of 31
6)The circuit in figure is
[A] LPF
[C]HPF
[B] Notch Filter

[D]All pass filter
is
[C]
[D]
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[B]
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[A]
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7)TheSchmitt trigger is shown in figure. The hysteresis
co
[A] Both (a) and (r) are true and (r) is the correct
reason for (a)
[C]Both (a) and (r) are false
(IE
8)Assertion (a) : An Op-Amp can perform mathematical operations like scaling, addition, integration,
differentiation etc. Such building blocks can be suitably connected to obtain an analog computer
Reason (r) : A differentiator is not used in analog computer because it amplifier noise and other unwanted
signals as its inputs.
[B] Both (a) and (r) are true and (r) is not the correct
reason for (a)
[D](a) is true but (r) is false
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9)Thecommon mode rejection ratio of a diff amp with parameters

= 10V,
= - 10V,JQ = 0.8 mA and
= 12 k .The transistor parameters are = 100,
= .Assume the output resistance looking into the
constant current source is = 25 K .Use a one sided output at
. TheCMRR in dBs
[A] 42.3 dB
[C]72.3 dB
10)Consider the Schmitt trigger in figure with parameters

- 10V . Determine the hysteresis
[B] 51.8 dB
[D]82.1 dB
= 10 K and
= 90 k . Let
= 10V and
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Page 3 of 31
[A] 5 V
[C]3 V
[B] 4 V
[D]2 V
11)For the RC phase shift oscillator in figure , the parameters are R = 10 K and C = 100 PF . The required
value of at = 65 KHz
[B] 570 K
[D]720 K
equals to
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12)For the circuit shown in figure
e)
[A] 320 K
[C]290 K
[A]
[B]
[D]
co
[C]
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13)For the correct shown in figure
[A]
[B]
[C]
[D]
Page 4 of 31
14)
Consider the deferential amplifier shown in the figure. Let
(dB)
10 and
= 11. Determine CMRR
[B] 22.4 dB
[D]41.6 dB
or
is
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15)For the amplifier circuit shown in figure ,
e)
[A] 52.1 dB
[C]62.1 dB
in the circuit shown in the
would be respectively
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and
and
16)The expression for the output voltage in terms of the input voltage
figure , assuming the operational amplifier to be ideal is :
The values of
[B] 22 V
[D]None
(IE
[A] 100 V
[C]11 V
[A] 9 and - 10
[C]- 9 and 10
[B] 9.9 and -10

[D]- 9.9 and 10
17)The circuit connection of op-amp given in figure (i) and figure (ii) represent
[A] logarithmic amplifiers for both figures (i) and (ii)

[C]detector for figure (i) and logarithmic amplifier for
figure (ii)
[B] detectors for both figures (i) and (ii)

[D]logarithmic amplifier for figure (i) and detector for
figure (ii)
Page 5 of 31
18)In the op-amp circuit shown below ,
>0 and
. The output voltage
will be proportional to
[A]
[C]
[B]
[D]
and
are to be amplified the same amplification factor , the
[B] r = 12 k
[D]r = 22 k
= 5 V ,
= 5 V ,
= 1 mA
= 0.5 mA
u.
[A]
[C]
co
(IE
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20)Calculate output voltage &current for the circuit
ng
[A] r = 33 k
[C]r = 58 k
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or
e)
19)In the given circuit , if the voltage inputs

value of 'R' should be
[B] = 5 V ,
[D]None
= 1.5 mA
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21)Assume that the operational amplifier in figure is ideal . The current ' I' through the 1k ohm resistor is
[A] - 4 mA
[C]2 mA
[B] - 2 mA
[D]4 mA
Page 6 of 31
22)For the op-amp, BJT circuit shown assume = 4 for BJT , and op-amp to be ideal. Which is the correct
statement , assume BJT be in active region and power supply will be 10 V
[A] terminal A is inverting and = 1V

[C]terminal A is inverting and = 1.25 V
[B] terminal A is non - inverting and = 1V

[D]terminal A is non - inverting and = 1.25 V
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23)In the figure shown, what is the value of
[A] 10 V
[C]6 V
and
are identical and have
. What is the value of
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24)For the circuit shown assume op-amp to be ideal
[B] 8 V
[D]2 V
[A] 4.2 V
[C]4 V
[B] 3 V
[D]can not be determined as op-amp is in positive
feedback
Page 7 of 31
25)Input the op-amp circuit is sine wave of peak value of 10V. What is the duty cycle of output
[A] 0.55
[C]0.5
[B] 0.45
[D]1
e)
26)Assertion(A): Op-Amps with FET input stages have less gain than those with BJT
Reason(R) : BJT has higher transconductance than FET
[B] Both A and R are true but R is NOT the correct
explanation of A
[D]A is false but R is true
al
or
[A] Both A and R are true and R is the correct

explanation of A
[C]A is true but R is false
[B]
[D]
and
and
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, and
[A]
[C] and
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27)In single stage differential amplifier , the output offset voltage is basically dependent on the mismatch of
(IE
28)Assertion(A) : In an op-amp circuit when one input terminal of the op-amp is grounded, the other terminal
becomes a virtual ground
Reason(R) : Input impedance of the op-amp is high
co
[A] both A and R are true and R is the correct

explanation of A
[B] both A and R are true but R is NOT the correct

explanation of A
Ps
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29)In a 741 op-amp, there is 20 dB/decade fall-off starting at a relatively low frequency . This is due to the
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[A] applied load

[C]impedance of the source
[B] internal compensation

[D]power dissipation in the chip
30)The input differential stage of op-Amp 741 is biased at about 10 A current .Such a low current of the input
stage gives
1.high CMRR 2. high differential gain
3. low differential gain 4. high input impedance
Which of these are correct ?
[A] 1 and 2
[C]3 and 4
[B] 1,2 and 4

[D]1,2,3 and 4
31)Assertion(A) : Operational amplifiers should have a high slew rate for good transient response
Reason(R): Slew rate is the maximum rate of change of the output voltage of the operational amplifier
when a large amplitude step is applied to its input

explanation of A

explanation of A
Page 8 of 31
32)Assertion(A) : An operational amplifier can amplify very low frequency including d.c signals
Reason(R) : op-amp uses very large coupling capacitor for cascading the various stages

explanation of A
[B] Both A and R are true but R is NOT the correct

explanation of A
33)An operational amplifier possesses

[A] very large input resistance and very large output

resistance
[C]very large input resistance and very small output
resistance
[B] very small input resistance and very small output

resistance
[D]very small input resistance and very large output
[A] To avoid saturation of the op-Amp

[C]To reduce reverse breakdown voltage of D1
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35)Cosider the following circuit :
[B] To provide negative feedback when the input is

negative
[D]As a buffer
(IE
What is the function of diode D2 in the above circuit ?
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34)consider the following circuit :
How does the above circuit work

[A] As a logarithmic amplifier
[C]As a positive clipper
[B] As a negative clipper

[D]As a half-wave rectifier
36)Consider the following statements :

Dominant pole frequency compensation in an OP-AMP
1.increases the slow-rate of the OP-AMP
2. Increases the stability of the OP-AMP
3. Reduces the bandwidth of the OP-AMP
4.reduces the CMRR of the OP-AMP
Which of the statements given above are correct ?
[A] 1 and 3 only
[C]1 and 2 only
[B] 1,2 and 4

[D]2 and 3 only
Page 9 of 31
37)What is the output voltage
of the below circuit ?
[A] -1.1 V
[C]1.0 V
[B] 1.1 V
[D]10 V
of the below circuit ?
S,
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or
e)
38)What is the output voltage
[A] -11 V
[C]11 V
[B] 6 V
[D]-6 V
with
[A]
[C]
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(IE
39)For the circuit of figure with an ideal operational amplifier, the maximum phase shift of the output
reference to the input is
40)Assuming the operational amplifier to be ideal the gain
for the circuit shown in figure is
[A] - 1
[C]- 100
[B]
[D]
[B] - 20
[D]- 120
Page 10 of 31

1. stray capacitance at the input terminal of an op-amp effectively introduces an additional phase lag
network in feedback loop
2.stray capacitance depends upon the value of resistor used in feedback
3.Low value of resistances has higher effects on stray capacitance
4.High value of resistances has higher effects on stray capacitance.
Which of the statements given above are correct ?
[A] 1,2 and 3

[C]1,3 and 4
[B] 2,3 and 4

[D]1,2 and 4
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43)Inthe circuit shown above , what is the value of transfer function
or
[B] 1%
[D]0.01%
al
[A] 10%
[C]0.1%
e)
42)A differential amplifier has inputs , = 1050 V and = 950 V with CMRR = 1000. What is the error in the
differential output ?
[B]
[D]
(IE
[A]
[C]
44)For a given op-amp, CMRR =

?
co
Ps
u.
[A]
[C]
. What is the common mode gain of the op-amp
and differential gain =
[B] 2 x
[D]1
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45)The voltage comparator shown in figure can be used in the analog to-digital conversion as
[A] a 1-bit quantizer

[C]a 4- bit quantizer
[B] a 2- bit quantizer

[D]a 8- bit quantizer
46)For the circuit given below , what is equal to ?
Page 11 of 31
[A] V/
[C]V /( R+ )
[B] V/R
[D]V /( 2R+
47)In the active filter circuits shown in figure, if Q= 1, a pair of poles will be realized with equal to
[B] 100 rad/s

[D]1 rad/s
or
of the circuit in figure is
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48)The input resistance
e)
[A] 1000 rad/s

[C]10 rad/s
[A] + 100 k
[C]+ 1 M
[B] - 100 k
[D]- 1 M
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49)What is the load current I in the circuit below ?

L
[A] -5 mA
[B] -10 mA
[C]+25 mA
[D]+50 mA
Page 12 of 31
50)Consider the inverting amplifier using an ideal operational amplifier shown in the figure. The designer
wishes to realize the input resistance seen by the small-signal source to be as large as possible, while
keeping the voltage gain between 10 and 25. the upper limit on is 1 M . The value of should be
[A] Infinity
[C]100 k
[B] 1 M
[D]40 k
and
(IE
in the above circuit, if the voltage
are to be amplified by the same
co
What is the value of

amplification factor ?
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e)
51)Consider the following circuit :
u.
[A] 7 k
[C]33 k
[B] 22 k
[D]35 k
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52)Consider the following Op-Amp circuit:
What is the output voltage
[A] 10 V
[C]11 V
in the above Op-amp circuit ?
[B] -10 V
[D]-11 V
Page 13 of 31
53)Consider the following circuit :
Which one of the following expressions for
is correct ?
[B]
[C]
[D]
e)
[A]
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54)In the given figure, if the input is a sinusoidal signal, the output will appear as shown in
[B]
(IE
[A]
[D]
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[C]
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55)In the op-amp circuit shown above (assuming ideal op-amp)
The output voltage is

[A] = -5 V
[C] = 0
[B] = + 5 V
[D] = - 2V
Page 14 of 31
56)The current through the resistor R in the below circuit is
[A] 1 mA
[B] 4 mA
[D]10 mA
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or
57)The stage marked X in the shown below architecture of a two-stage op-amp is
e)
[C]8 mA
[B] buffer amplifier

[D]Blocking oscillator
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[A] 1. Direct coupled amplifier

[C]Level shifter
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[A] 3/2 sin (100 t)

[C]2 sin(100 t)
for an input = [ 2+ sin(100 t)] V
Ps
The output voltage
u.
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(IE
58)A non inverting op-amp is shown below (assume ideal op-amp)
[B] 3 sin (100t)

[D]3 sin (100 t) +1/2
59)An op-amp circuit is shown in the figure
The output
will be (assume ideal op-amp)
[A] equal to zero because the input is zero
[B] dependent on element values hence nothing can

be predicted without a knowledge of element
values
Page 15 of 31
[C]a square wave varying between +
and -
[D]a sinusoidal wave of amplifier
60)For a given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit shown in figure
will be
[B]
[C]
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[A]
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Page 16 of 31
61)An op-amp circuit is shown in the figure given below. Different inputs and output are given under List-I and
List-II . Match List-I(inputs) with List-II(Outputs) and select the correct answer using the codes given below
the lists :
co
Codes: A B C D
[B] 1 3 2 4
[D]1 4 2 3
u.
[A] 2 4 1 3
[C]2 3 1 4
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[A] 10 V
[C]100 V
and output voltage is 10 volt, the differential voltage should be
Ps
62)In a circuit , if the open loop gain is
63)In the circuit shown in the given figure,
[A] Sin(t /4)

[C]sin t
[B] 0.1 V
[D]1 V
is given by
[B] sin(t+ /4)

[D]cos t
Page 17 of 31
64)In the circuit shown in the given figure, the current flowing through resistance of 100 would be
[A] 8 mA
[B] 10 mA
[C]20 mA
[D]100 mA
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e)
65)The op-amp circuit shown in the given figure is
[A] a high pass circuit
[B] a low-pass circuit
[C]a band-pass circuit
[D]an all-pass circuit
[B] 2 alone
[D]1 and 3
of the Op-Amp circuit shown in the given figure is
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67)The
Ps
[A] 1 alone
[C]3 alone
u.
co
(IE

A totem pole configuration used in the output stage of an op-amp has the advantage of using
1.only n-p-n BJTs
2.complementary symmetrical pair of transistors
3.only one transistor
Which of these statements is/are correct ?
[A] 11
[C]
[B] 10
[D]Zero
Page 18 of 31
68)The voltage gain versus frequency curve of an Op-Amp is shown in the given figure
The gain-bandwidth product of the Op-Amp is
[B] 200 MHz

[D]2 MHz
e)
[A] 200 Hz
[C]200 kHz
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69)The voltage gain versus frequency curve of an Op-Amp is shown in the given figure
(IE
The gain-bandwidth product of the Op-Amp is
[B] 200 MHz

[D]2 MHz
of the given circuit
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70)The output voltage
co
[A] 200 Hz
[C]200 kHz
[A] -100 V
[C]10 V
[B] -100 mV
[D] 10 mV
Page 19 of 31
71)The circuit shown in the figure is
[A]
[B]
a voltage source with voltage
a voltage source with voltage
[C]
[D]
a current source with current
a current source with current
e)
72)The first dominant pole encountered in the frequency response of a compensated op-amp is
approximately at
[B] 10 kHz
[D]100 MHz
or
[A] 5 Hz
[C]1 MHz
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(IE
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73)The switch S in the circuit of the figure is initially closed, it is opened at timer t = 0. you may neglect the
Zener diode forward voltage drops. What is the behaviour of
for t >0 ?
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[A] It makes a transition from 5V to + 5V at t =

12.98 s
[C]It makes a transition from + 5V to - 5V at t =
12.98 s
[B] It makes a transition from 5V to + 5V at t = 2.57

s
[D]It makes a transition from + 5V to - 5V at t = 2.57
s
74)The first dominant pole encountered in the frequency response of a compensated op-amp is
approximately at
[A] 5 H
[C]1 MHz
75)In the circuit of the figure
[B] 10 kHz
[D]100 MHz
is
Page 20 of 31
[A] -1V
[B] 2V
[C]+ 1V
[D]+ 15V
or
e)
76)The configuration of the figure is
al
[A] precision integrator

[C]Butterworth high pass filter
ng
[B] Hartely oscillator
[D]Wien-bridge oscillator
S,
Ba
is a triangular wave then
will be
u.
[A] Square wave

[C]Parabolic wave
co
(IE
77)Assume that the op-amp of the figure is ideal. If
[B] Triangular wave

[D]Sine wave
Ps
78)The most commonly used amplifier in sample and hold circuits is
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[A] a unity gain inverting amplifier

[C]an inverting amplifier with a gain of 10
[B] a unity gain non-inverting amplifier

[D]an inverting amplifier with a gain of 100
79)If the op-amp in the figure has an input offset voltage of 5mV and an open-loop voltage gain of 10,000
then will be
[A] 0V
[C]+15V or 15V
[B] 5mV
[D]+50V or 50V
80)The ideal OP-AMP has the following characteristics.

[A] =
[C] =
, A=
, A=
, = 0
, =
[B] = 0, A=
[D] = 0, A=
,
,
=0
=
Page 21 of 31
81)Which one of the following causes phase shift through an op-amp?
[A] Internal RC circuits
[C]Gain roll off the internet transistor
. [QEDCA193] .. 2 Marks (
[B] External RC circuits

[D]Negative feedback
82)Which one of the following causes phase shift through an op-amp?

[A] Internal RC circuits
[C]Gain roll off of the internal transistor
[B] External RC circuits

[D]Negative feed back
depend on
e)
83)In the following a stable multivibrator circuit, which properties of
[B] Only the amplitude

[D]Neither the amplitude nor the frequency
or
[A] Only the frequency

[C]Both the amplitude and the frequency
Ps
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(IE
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. Decide whether
84)In the circuit shown below, the op-amp is ideal, the transistor has
the feedback in the circuit is positive or negative and determine the voltage V at the output of the op-amp
. [QISRA009] .. 2 Marks (
[B] Positive feed back, V = 0V

[D]Negative feed back, V = 2V
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[A] Positive feedback, V = 10 V

[C]Negative feed back, V = 5V
85)If the input to the circuit of figure is a sine wave , then the output will be :
[A] Half wave rectified sine wave

[C]A square wave
86)A high gain Op-Amp has
[B] A full wave rectified sine wave

[D]A triangular wave
. The correct statement is :
[A] The non-inverting gain &inverting gain are nearly

same
[C]The non-inverting gain is very much higher than
inverting gain
[B] The inverting gain is very much higher than noninverting gain
[D]The inverting &non-inverting gains are unrelated
Page 22 of 31
87)In this circuit , the relationship between
& is :
[A]
[B]
[C]
[D]None of these
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e)
88)What is the output waveform for a sinusoidal input of peak-peak amplitude of 4V . Assume that
are two identical Zener diodes of 4.7 V , and
u.
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89)Assume that
Find
[B] Sinusoidal waveform with 5.4V peak

[D]Sinusoidal waveform clamped to + /- 5.4 V
co
[A] Same as input

[C]Sinusoidal waveform clamped to +/ - 4.7 V
[A] 3.92 mA
[C]6.84 mA
[B] 4 mA
[D]2.8 mA
90)In an inverting OP-AMP , the input bias current is - 1

, and the input and the feedback resistances are
both 1 M . What will be the output voltage for an input voltage of 2.5 V ?
[A] - 2.5 V
[C]- 3.5 V
[B] - 3.0 V
[D]4.0 V
91)Which of the following devices can be used for generating a PWM signal ?
Page 23 of 31
[A] Comparator
[C]Counter and magnitude comparator
[B] 555 timer

[D]All the above
92)What would be the output of the following circuit , if a positive going unipolar pulse with an amplitude
greater than
, is applied at the input ?
will go high momentarily and return to low

will go high and remain high
[B]
[D]
will go low momentarily and return to high

will not change its previous state
e)
[A]
[C]
[B] bandwidth
[D]CMRR
u.
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94)
al
[A] open -loop gain

[C]slew rate
or
93)A differential amplifier is used in the input stage of Op-Amps to achieve very high
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[A] + 6V
[C]- 6V
Ps
In the circuit shown in the above figure , the value of output
is
[B] - 9V
[D]+ 9V
95)The circuit shown in figure is a
[A] Low-pass Filter

[C]Band-pass filter
[B] High-pass filter

[D]Band-reject filter
Page 24 of 31
96)In the op-amp circuit given in figure , the load current
is
[B]
[C]
[D]
e)
[A]
(IE
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or
97)An op-amp has an offset voltage of 1 mV and is ideal in all other respects . If this op-amp is used in the
circuit shown in figure , the output voltage will be
[A] 1mV
[C] 1V
[B] 1V
[D]0 V
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u.
co
98)For a sinusoidal input , the circuit shown in the figure will act as a
[A] Pulse generator

[C]Full-wave rectifier
[B] Ramp generator

[D]Voltage doubler
99)
In the ideal Op-amp circuit shown
is
Page 25 of 31
[A]
[C]
[B]
[D]
100)A differential amplifier has a differential gain of 20,000 . CMRR = 80 dB . The common mode gain is given
by
[A] 2
[C]1/2
[B] 1
[D]0
[B] - 4.875 V
[D]- 6.875 V
. [QNetA006] .. 1 Marks (
ng
[A] - 3.875 V
[C]- 5.875 V
al
or
e)
101)Determine the output voltage of a network shown in figure if the digital input is 1011
S,
Ba
102)In an ideal op-amp the output impedance is

[A] 50 ohm
[C]Infinite
[B] 100 ohm

[D]Zero
G
at
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es
Ps
u.
co
(IE
103)The very low frequency gain of the low pass filter shown in the given figure is
[A] 10 dB
[C]30 dB
[B] 20 dB
[D]40 dB
104)The circuit shown in figure represents
[A] LPF
[C]BPF
[B] HPF
[D]BSF
Page 26 of 31
105)For the 4-bit DAC shown in figure ., the output voltage
is
. [QNetA017] .. 2 Marks (
[A] 2 V
[C]3 V
[B] - 2 V
[D]- 3 V
[B]
[C]
[D]
S,
Ba
[A]
. [QPowA772] .. 2 Marks (
. [QAlgA104] .. 2 Marks (
ng
al
or
e)
106)A non-inverting OP-AMP summer is shown in the figure. The output voltage is
107)Assertion(A):An operational amplifier should have a low input offset current

Reason(R) : Input impedance of op-amp should be very high
(IE

explanation of A
[A] Both A and R are true and R is the correct

explanation of A
G
at
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es
Ps
u.
co
108)The circuit of op-amp figure 1 and figure 2 represent
[A] Both are log amplifiers

[C]log Amp for figure 1 and detector for figure 2
109)
Find current gain
for the figure shown in the Shunt-Shunt feedback given
[A]
[C]
[B] Both are detectors

[D]Detector for figure 1 and Log Amp for figure 2
[B]
[D]
Page 27 of 31
110)A differential Amplifier is shown. Transistors and have identical parameters. Assuming
= 0.7 V and
= 200 for each transistors. Given
. Find the value of collector current
e)
[B] 0.5 mA
[D]2 mA
or
[A] 0 mA
[C]1 mA
(IE
S,
Ba
ng
al
111)Figure shows an ideal voltage amplifier with gain 100 V/V. Find the overall gain
= 5V,
= - 10V , find the common mode input signal
G
at
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es
Ps
Given
[B] - 149.7
[D]- 94.7
u.
112)Given A =
co
[A] - 49.7
[C]- 100.7
[A] 4.995
[C]2.425
[B] 5.005
[D]10.215
113)Consider op-amp and diode ideal, find the transfer characteristics
Page 28 of 31
[A]
[B]
[C]
[D]None
current series feedback with
[C]
ng
[B]
current shunt feedback with
[D]
S,
Ba
[A]
al
or
e)
114)Identify the topology and the value of
voltage shunt feedback with
voltage series feedback with
Statement for Linked answer Q115 and Q116 is given below
Ps
u.
co
(IE
115)Findthe frequency of oscillations in theoscillator
G
at
eI
es
[A] R/L
[C]R / 2L
116)Find the relation between

[A]
[C]
[B] L / 2R
[D]
and
[B]
[D]
Page 29 of 31
117)The Op-amp in the circuit in figure has an open loop differential voltage gain of = . Neglect the
current into the op-amp, and assume the output resistance looking back into the Op-amp is zero.
Determine the closed loop voltage gain

al
[B] 10.99
[D]45.6
or
in
[A] 7.6
[C]31.2
ng
118)The input resistance
[B] -32.7
[D]-21.94
e)
[A] -11.9
[C]-19.1
If
G
at
eI
es
[A] All pass filter

[C]high pass filter
Ps
u.
co
(IE
S,
Ba
119)A general filter circuit is shown in the figure
[B] Band pass filter

[D]low pass filter
120)The output of the filter in the above question is given to the circuit shown in figure: The gain vs frequency
characteristic of the output will be
[A]
[B]
Page 30 of 31
[C]
[D]
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(IE
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Page 31 of 31
Key Paper
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G
at
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es
Ps
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(IE
S,
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e)
1.

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Institute of Engineering Studies (IES,Bangalore)

Leading Institute for GATE/IES/JTO/PSUs in (Branches @ Jayanagar &Malleshwaram) Bangalore.

Subject: Analog Electronics

Total Questions :120

Practice Questions for Classroom & Postal Series Students

1)Find input resistance

Consider op-amp ideal

2)Find the ratio

4)Find the value of R to get _

[A] 47.74 kHz

5)For a type 741 op- amp ( = 9.5 A and

= 30 PF) then the slew rate is

[B] Notch Filter

7)TheSchmitt trigger is shown in figure. The hysteresis

9)Thecommon mode rejection ratio of a diff amp with parameters

10)Consider the Schmitt trigger in figure with parameters

12)For the circuit shown in figure

13)For the correct shown in figure

= 11. Determine CMRR

15)For the amplifier circuit shown in figure ,

in the circuit shown in the

[B] 9.9 and -10

[A] logarithmic amplifiers for both figures (i) and (ii)

[B] detectors for both figures (i) and (ii)

. The output voltage

are to be amplified the same amplification factor , the

20)Calculate output voltage &current for the circuit

19)In the given circuit , if the voltage inputs

[A] terminal A is inverting and = 1V

[B] terminal A is non - inverting and = 1V

23)In the figure shown, what is the value of

24)For the circuit shown assume op-amp to be ideal

[A] Both A and R are true and R is the correct

[A] both A and R are true and R is the correct

[B] both A and R are true but R is NOT the correct

[A] applied load

[B] internal compensation

[B] 1,2 and 4

[A] both A and R are true and R is the correct

[B] both A and R are true but R is NOT the correct

[A] both A and R are true and R is the correct

[B] Both A and R are true but R is NOT the correct

33)An operational amplifier possesses

[A] very large input resistance and very large output

[B] very small input resistance and very small output

[A] To avoid saturation of the op-Amp

35)Cosider the following circuit :

[B] To provide negative feedback when the input is

What is the function of diode D2 in the above circuit ?

34)consider the following circuit :

How does the above circuit work

[B] As a negative clipper

36)Consider the following statements :

[B] 1,2 and 4

of the below circuit ?

of the below circuit ?

38)What is the output voltage

40)Assuming the operational amplifier to be ideal the gain

for the circuit shown in figure is

41)Consider the following statements :

[A] 1,2 and 3

[B] 2,3 and 4

43)Inthe circuit shown above , what is the value of transfer function