Why JTAG Testing Makes Sense

Copyright Corelis, Inc. 2016

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Agenda

Corelis company overview

Why is test necessary?
JTAG: What is it and why do we need it?
Corelis solutions and tools
Corelis integration with other ATE
DFT and Test Procedure Services
Questions & Answers

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Corelis Background
Corelis, Inc.

Founded in 1991
Headquarters in Cerritos, California
Core competency focus is on
IEEE-1149.1 and related standards

Acquired by Electronic Warfare Associates 2006

Founded 1977
Engineering Design & Development, Systems Integration, Information
Assurance, Software/Hardware Assurance, Information Operations,
Infrastructure Protection, Development/Operational Testing.
Customer Base:
DoD, National Intelligence Agencies, National Law Enforcement, Secret Service, NASA

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Corelis Business Segments

Business
Segments
JTAG
Test & ISP

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Engineering
Services

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Bus
Analyzers
& Exercisers

Emulation
Tools

Core Customer Base

Telecommunication
Aerospace and Defense
Medical
Contract Manufacturers
Networking and Storage
Industrial

3Com, Agilent, Algen, Allen-Bradley, AMCC, AMD, Anaren, Avici, BAE Systems, Beckman,
Bell Helicopter, Benchmark, BigBand Networks, Boeing, Broadcom, Brocade, Canon,
Celestica, Ciena, Cisco, DirectTV, Draper Labs, EADS, Ericsson, E-Systems, Fermi National
Lab, Flextronix, FLIR Indigo Systems, Fluke Networks, Force 10 Networks, Force
Computers, Ford, General Dynamics, Hamilton Sundstrand, Harris, Hewlett-Packard,
Honeywell, Hughes, Hypercom, IBM, Intel, ITT, Jabil, JC Air, JPL, Juniper Networks, L3
Comm., Lockheed Martin, LSI, Marconi, Matra, Matsushita, Medtronic, Microsoft,
Motorola, NASA, Netcom, Nokia, Nortel, Northrop Grumman, Panasonic, Philips,
Polaroid, Qualcomm, Raytheon, Rockwell, Samsung, Sandia, Sanmina-SCI, Seagate,
Sharp, Siemens, Smith Industries, Solectron, Spacelabs, Sun, Tandem, Teledyne, Textron,
Thales, Thomson Consumer, TI, Toshiba, TRW, ViaSat

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Presenter
Ryan Jones
Senior Technical Marketing Engineer

Ryan brings 20+ years of experience in the test

equipment industry. He started his career as a
design engineer developing measurement
electronics and writing control firmware for bare
board test equipment including flying probers.
Ryan joined the Corelis team in 1999 and has since
become an expert in the field of boundary-scan test.
He regularly conducts boundary-scan training
classes focusing on design-for-test and test
procedure development with Corelis products.
Ryan holds a Bachelors of Science degree in
Computer Engineering Technology from California
State University, Long Beach.

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Testing is Fundamental

The ideal test strategy is to maximize test coverage while

minimizing total product cost
Faults found in the factory are less costly than escaped faults
Testable circuits are less costly to test and repair

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Where Engineers Spend Time

Source: UBM Tech

2014 Embedded Market Study

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What are Designers Greatest Concerns?

Source: UBM Tech

2014 Embedded Market Study

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What Designers Want to Improve?

Source: UBM Tech

2014 Embedded Market Study

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What is JTAG?
The term JTAG has a wide variety of meanings:

Joint Test Action Group

IEEE-1149.x Standard
Software Debugging / Emulation
In-System Programming
Structural Board Testing
JTAG Embedded Testing
Embedded Instrumentation
XBOX Hacking

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CORELIS
Toolbox

IEEE 1149.1 Standard

Developed during the late 80s

Officially standardized in 1990
BSDL language added in 1994
Latest standard is maintained by IEEE:

Active Document name

1149.1-2013: IEEE Standard for Test Access Port and Boundary-Scan Architecture
Publication Date: May 13, 2013
Page(s): 442
ISBN(s): 9781504414975, 9780738182636, 9780738182643, 9780738189949, 9780738189956

Contact
1- 800-699-9277 (USA and Canada)
1- 734-780-8000 (Worldwide)
http://www.ieee.org

Copyright Corelis, Inc. 2016

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Related Board Test Standards

IEEE Std 1149.1-2013 Test Access Port and Boundary-Scan Architecture

Test Access Port and Boundary-Scan Architecture

IEEE Std 1149.6 Advanced Digital Networks

This standard augments IEEE Std 1149.1 to improve the ability for testing high-speed
differential signals and AC coupled interconnections between ICs.

IEEE Std 1149.7 Reduced-Pin and Enhanced-Functionality TAP

Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan
Architecture. Augments, but does not replace IEEE-1149.1.

IEEE Std 1532 In-System Configuration of Programmable Devices

Defines instructions and data registers for accessing and configuring programmable
devices using the IEEE-1149.1 TAP.

IEEE Std 1581 Test access methodology for memory devices

Defines a low-cost method for testing the interconnection of discrete, complex memory
ICs where additional pins for testing are not available and implementing JTAG is not
feasible.

IEEE Std 1687 Access and Control of Embedded Instrumentation

Defines a methodology for access to embedded test and debug features via the IEEE1149.1 TAP.

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Traditional Test Methods

Bed of Nails In-Circuit Testers
Requires Bed-of-Nails Test
Fixture to access all internal
nodes of the board
Requires keeping inventory of
test fixtures
Requires fixture maintenance
and verification
Requires machine maintenance
(calibration / test probe wear)

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Traditional Test Limitations

Loss of physical access by
traditional bed of nails testers is
the #1 driver for JTAG adoption

Inability to place a probe on

high-speed signals is also a
significant problem

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Rationale for JTAG

Loss of
physical
access

High-speed
signaling

Technology miniaturization, higher density, increased layer counts

Blind & buried vias, dual-sided component placement, BGAs
High Density Interconnection (HDI), high-speed buses
Multi-core, MCM, SoC, 3D stacked dies

Drive to shorten product life cycles

Increased
board
density

PC boards have become more complex

Fine-pitch
Components
SMTs, BGAs

Tremendous market pressure to minimize the time from design to manufacturing

The value of using traditional test equipment has diminished

Loss of physical/electrical access decreases effectiveness of bed of nails and flying probe
test technologies
Test results are no longer able to meet test expectations
Test fixtures increase test cost, take time to build, and are often impractical for prototype
Larger memories mean longer programming times. Using ICT for device programming
doesnt make economical sense.

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Boundary-Scan Adoption

Source:
iNEMI
2010

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JTAG Usage
Top 5 Uses for JTAG:
Structural Test
Part Programming
Device Version
Verification
Circuit Board Debug and
Diagnosis
Nail Reduction on ICT
Fixtures
Source: iNEMI Boundary-Scan Adoption Survey
Results 2009

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Product Life Cycle JTAG Support

Product Life-Cycle JTAG Support
Development Phase

Design

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Hardware
Debug

Software
Debug

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Integration
and Test

Corelis Tools

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Corelis Tools

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Boundary-Scan Controllers
Multi-TAP PCI & PCIe Interfaces

Multi-TAP Ethernet & USB Interfaces

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ScanExpress Demonstration
TPG
DFT Analyzer

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Runner
Viewer

ScanExpress Benefits

Relatively quick test procedure development

No need for test fixtures
Single cable interface to UUT
Access to inaccessible device pins
No unreliable probe contact
Combine board testing with device programming
Reduces inventory management
No pre-programmed parts
Eliminates excessive device handling and potential ESD
damage

Copyright Corelis, Inc. 2016

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ScanExpress Benefits
Reusable test vectors across prototype development,
production test, and field service
High resolution pin and net level diagnostics
Does not require writing any functional test code
Significantly lower investment cost than traditional
ICT systems
Portable

Copyright Corelis, Inc. 2016

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ICT / ATE / Flying Probe Integration

Seica
Keysight 3070, i3070, and Medalist products
Teradyne Test Station, GR Pilot, HSSub
Checksum
SPEA Flying Probe
Digitaltest
National Instruments HSDIO

Copyright Corelis, Inc. 2016

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Benefits of Integrated Testing

One test station with a single GUI reduces board
handling and offers a more comprehensive test
Higher test coverage & fault detection with more
accurate fault diagnostics
More robust programming capability
Adds 1149.6, IEEE-1532 and STAPL capabilities
Reduced fixture costs by test point reduction
Extends the life of ICT equipment

Copyright Corelis, Inc. 2016

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DFT and Test Procedure Services

Corelis offers a complete range of turn-key
design-for-test and test procedure services.
Our design consultations provide a thorough
analysis of your design for boundary-scan
testability including recommendations on how
to improve the testability.
Monthly training classes held at Corelis
headquarters offered at no charge.
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TestGenie

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Corelis Commitment
Our core philosophy is that Corelis
provides solutions, not just
products

Customer Support is as important as

the products we sell
Providing customer support is not
enough. Our goal is to provide
Better than World Class support

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Questions & Answers

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