VHDL Rangkaian CLOCKDIV Percobaan 3A

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity CLOCKDIV is port(
CLK: IN std_logic;
DIVOUT: buffer BIT);
end CLOCKDIV;
architecture behavioural of CLOCKDIV is
begin
PROCESS(CLK)
variable count: integer:=0;
constant div: integer:=24;
begin
if CLK'event and CLK='1' then
if(count<div) then
count:=count+1;
if(DIVOUT='0') then
DIVOUT<='0';
elsif(DIVOUT='1') then
DIVOUT<='1';
end if;
else

if(DIVOUT='0') then
DIVOUT<='1';
elsif(DIVOUT='1') then
DIVOUT<='0';
end if;
count:=0;
end if;
end if;
end process;
end behavioural;

3B Simulasi

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY bcd IS
PORT ( D0,D1,D2,D3 : IN BIT;
A,B,C,D,E,F,G : OUT BIT);
END bcd;
ARCHITECTURE behavioral OF bcd IS
BEGIN
A<= (D3 OR D1 OR (D2 AND D0) OR ((NOT D2) AND (NOT D0)));
B<= ((NOT D2) OR (((NOT D1) AND (NOT D0)) OR (D1 AND D0)));
C<= ((NOT D1) OR D2 OR D0);
D<= (D3 OR ((NOT D2) AND (NOT D0)) OR (D2 AND (NOT D1) AND D0) OR (D1
AND (NOT D0)) OR (D1 AND (NOT D2)));
E<= ((NOT D0) AND ((NOT D2) OR D1));
F<= (D3 OR ((NOT D1) AND (NOT D0)) OR (D2 AND (NOT D1)) OR (D2 AND
(NOT D0)));
G<= ((D3 OR D2 OR D1) AND ((NOT D2) OR (NOT D1) OR (NOT D0)));
END behavioral;

3B FPGA
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY bcd IS
PORT ( D0,D1,D2,D3 : IN BIT;
A,B,C,D,E,F,G : OUT BIT);
END bcd;
ARCHITECTURE behavioral OF bcd IS
BEGIN
A<= NOT (D3 OR D1 OR (D2 AND D0) OR ((NOT D2) AND (NOT D0)));
B<= NOT ((NOT D2) OR (((NOT D1) AND (NOT D0)) OR (D1 AND D0)));
C<= NOT ((NOT D1) OR D2 OR D0);
D<= NOT (D3 OR ((NOT D2) AND (NOT D0)) OR (D2 AND (NOT D1) AND D0) OR
(D1 AND (NOT D0)) OR (D1 AND (NOT D2)));
E<= NOT ((NOT D0) AND ((NOT D2) OR D1));
F<= NOT (D3 OR ((NOT D1) AND (NOT D0)) OR (D2 AND (NOT D1)) OR (D2
AND (NOT D0)));
G<= NOT ((D3 OR D2 OR D1) AND ((NOT D2) OR (NOT D1) OR (NOT D0)));
END behavioral;

3C File DUT (abstraksi.vhd)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY abstraksi IS PORT (
SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
HEX1 : OUT STD_LOGIC_VECTOR (1 TO 7));
END abstraksi;
ARCHITECTURE behavioral OF abstraksi IS
CONSTANT NOL
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT SATU
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT DUA
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT TIGA
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT EMPAT
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT LIMA
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT ENAM
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT TUJUH
: STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT DELAPAN : STD_LOGIC_VECTOR(3 DOWNTO
CONSTANT SEMBILAN : STD_LOGIC_VECTOR(3 DOWNTO

0)
0)
0)
0)
0)
0)
0)
0)
0)
0)

:=
:=
:=
:=
:=
:=
:=
:=
:=
:=

BEGIN
PROCESS(SW)
BEGIN
CASE SW IS
WHEN NOL
WHEN SATU
WHEN DUA
WHEN TIGA

=>
=>
=>
=>

WHEN EMPAT =>

WHEN LIMA
=>
WHEN ENAM
=>
WHEN TUJUH =>
WHEN DELAPAN
WHEN SEMBILAN
WHEN OTHERS
END CASE;
END PROCESS;
END behavioral;

3C Testbench (tb_abstraksi.vhd)

HEX1
HEX1
HEX1
HEX1

<=
<=
<=
<=

"1111110";
"0110000";
"1101101";
"1111001";

HEX1 <= "0110011";

HEX1 <= "1011011";
HEX1 <= "1011111";
HEX1 <= "1110000";
=> HEX1 <= "1111111";
=> HEX1 <= "1110011";
=> HEX1 <= "0000000";

"0000";
"0001";
"0010";
"0011";
"0100";
"0101";
"0110";
"0111";
"1000";
"1001";

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY tb_abstraksi IS
END tb_abstraksi;
ARCHITECTURE behavioral OF tb_abstraksi IS
SIGNAL clk
: STD_LOGIC := '0';
SIGNAL SW
: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL HEX1
: STD_LOGIC_VECTOR (1 TO 7);
COMPONENT abstraksi IS
PORT( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
HEX1
: OUT STD_LOGIC_VECTOR (1 TO 7));
END COMPONENT;
BEGIN
dut : abstraksi
PORT MAP (
SW => SW ,
HEX1 => HEX1 );
clock : PROCESS
BEGIN
WAIT FOR 50 ps; clk <= not clk;
end PROCESS clock;
increment: PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
SW <= SW + "0001";
END IF;
END PROCESS;
END behavioral;

6
onbreak {resume}
if [file exists work] {
vdel -all
}
vlib work
vcom abstraksi.vhd tb_abstraksi.vhd
vsim -novopt tb_abstraksi
add wave sim:/tb_abstraksi/dut/*
run 2000
y