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In mode 0 port A and port B can be configured as simple 8 bit input or output
without handshaking. The two halves of port C can be programmed separately as 4
bit input or output ports
In mode 1two groups each of 12 pins are formed. Group A consists of port A and
the upper half of port C. port A and B can be programmed as 8 bit input or output
ports with three lines of port C in each group
for handshaking.
In mode 2 only port A can be used as a bidirectional port. The handshaking signals
are provided on five lines of port C (PC3-PC7). Port B can be used in mode 0 or in
mode
Pin diagram:
Block diagram:
Figure shows the internal block diagram of 8255A. It consists of data bus buffer,
control logic and group A, group B controls.
Data bus buffer:
This tri state bidirectional buffer is used to interface the internal data bus of 8255
to the system data bus input or output instructions executed by the CPU either read
data from or write data into the buffer. Output data from the CPU to the ports or
control register and input data to the CPU from the ports or status register are all
passed through the buffer
Control logic:
The control logic block accepts control bus signals as well as inputs from the
address bus and issues commands to the individual group control blocks (Group A
control and group B control). It issues appropriate enabling signals to access the
required data/control signals word or status word. The input pin for the control
logic sections are described here
Group A and Group B controls:
Each of the Group A and Group B control block receives control words from the
CPU and issues appropriate commands to the ports associated with it. The group A
control block controls port A and PC7-PC4 while the group B control block
controls port B and PC3-PC0
Port A: this has an 8 bit latched and buffered output and an 8 bit input latch. It can
be programmed in three modes- mode 0, mode 1, mode 2
Port B: this has an 8 bit data I/O latch/buffer and an 8 bit data input buffer. It can
be programmed in mode 0 and mode 1
Port C: this has one 8 bit unlatched input buffer and an 8 bit output latch/buffer.
Port C can be separated into two ports and each can be used as control signals for
ports A and B in the handshake mode. It can be programmed for bit set/reset
operation
Operation modes:
Bit set- reset (BSR) mode:
The individual bits of port c can be set or reset by sending out a single OUT
instruction to the control register. When port c is used for control/status operation
this feature can be used to set or reset individual bits
I/O modes:
Mode 0: simple input/output:
In this mode ports A and b are used as two simple 8 bits I/O ports and port c as two
4 bits ports. Each port can be programmed to function as simply an input port or an
output port. The input/output features in mode 0 are as follows:
programmed for any other mode by writing a single control word into the control
register when required
For bit set/reset mode:
0
D6
D5
D4
D3
D2
D1
D0
D0 bit set/reset
1 set
2 reset
D3, D2, D1 bit select
D4, D5, D6 dont care
0 bit set//reset flag
0 active
The eight possible combination of the states of bits D3-D1 (B2B1B0) in the bit set
reset format (BSR) determine particular bit in the PC0-PC7 being set or reset as per
the status of the bit D0
The BSR word can also be used for enabling and disabling interrupt signals
generated by port c when the 8255 is programmed for mode 1 and mode 2
operations. This is done by setting or resetting associated bits of interrupts
For I/O mode:
The mode definition format for I/O mode is shown in figure. The control words for
both mode definition and bit set-reset are loaded into the same control register with
bit D7 used for specifying whether the word loaded into the control register in a
mode definition word or bit set reset word
0
D6
D5
D0 group B, port C (lower)
1-input, 0-output
D1 port B
D2 mode selection
D3 group A, port C (upper)
D4 port A
D5, D6 - mode selection
00 mode 0
01 mode 1
D4
D3
D2
D1
D0
1x mode 2
Mode set flag
(1 active)
Mode 1 input control signals:
- storable input
input buffer full
- interrupt request
Mode 1 output control signal
- output buffer full
- acknowledge input
- interrupt request
Mode 2 control signals
- interrupt request
- output buffer full
acknowledge
- storable input
input buffer full
Status words:
Mode 1: (input)
D7
D6
I/O
I/O
D5
IBFA
D4
INTEA
D3
INTRA
GROUP A
Mode 1: (output)
D7
D6
INTEA
A
D5
I/O
D2
INTEA
GROUP A
D0
INTRB
GROUP B
D4
I/O
D3
INTRA
D2
INTEB
GROUP A
Mode 2: (status word)
D7
D6
D5
INTE1
IBFA
A
D1
IBFB
D4
INTE2
D1
B
D0
INTRB
GROUP B
D3
INTRA
D2
D1
GROUP B
D0
Control logic:
This block has an input and an output line. If the 8259A is properly enabled the
interrupt request will cause the 8259A to asset its INT output pin high. If this pin is
connected to the INTR pin of an 8085 and if the 8085 interrupt enable (IE) flag is
set then this high signal will cause the 8085 to respond INTR as explained earlier
Interrupt request register (IRR)
The IRR is used to store all the interrupt levels which are requesting the service.
The eight interrupt inputs set corresponding bits of interrupt request register upon
service request
Interrupt service register (ISR)
The ISR stores all the levels that are currently being serviced
Interrupt mask register (IMR)
IMR stores the masking bits of the interrupt line to be masked. This register can be
programmed by an operation command word (OCW). An interrupt which is
masked software will not be recognized and serviced even if it set the
corresponding bits in the IRR
Priority resolver
This determines the priorities of the bits set in the IRR. The bit corresponding to
the highest priority interrupt input is set in the ISR during the input.
Cascade buffer comparator
This section generates control signals necessary for cascade operations. It also
generates buffer enable signals.
SP/EN: (slave program/enable buffer)
The SP/EN signal is tied high for the master. However it is grounded for the slave
In non buffered mode the SP/EN pin of an 8259 is used to specify whether the
8259 is to operate as a master or as a slave and in the buffered mode the / pin is
used as an output to enable the data bus buffer of the system.
CAS0-CAS2
For a master 8259 these pins are output pins and for slave 8259s these are input
pins.
Priority modes and other features
The various modes of operation of 8259 are
Fully nested mode (FNM)
Special fully nested mode (SFNM)
Rotating priority mode
Special masked mode
Polled mode
Fully nested mode (FNM)
After initialization the 82259A operates in fully nested mode so it is called default
mode. The 8259 continues to operate in this mode until the mode is changed
through operation command words. In this mode IR0 has highest and IR7 has
lowest priority. When the interrupt is acknowledged it sets the corresponding bit in
ISR. This bit will inhibit all interrupts of the same or lower level however it will
accept higher priority interrupt requests. The vector address corresponding to this
interrupt is then sent. The bit in ISR will remain set until an EOI command is
issued by the microprocessor at the end of interrupt service routine. But if AEOI
(Automatic End Of Interrupt) bit is set the bit in the ISR reset all the trailing edge
of the last
Specially fully nested mode (SFNM)
In the FNM on the acknowledgement of the interrupt from the same level are
disabled. Consider a large system which uses the cascaded 8259s and where the
interrupt levels within each slave have to be considered. An interrupt request input
to a slave in turn cases the slave to place an interrupt request to the masks on one
of the masters input. Further interrupts to the slave will cause the slave to place
requests to the master on some inputs to the master but these will not be recognized
because further interrupts on the same input level are disabled by the master.
Rotating priority mode:
The rotating priority mode can be in
Automatic rotation
and
Specific rotation
IR1
5
IR2
6
IR3
7
IR4
0
IR5
1
IR6
2
IR7
3
IR1
5
IR2
6
IR3
7
IR4
0
IR5
1
IR6
2
IR7
3
provides polled word and sets ISR bit of highest priority active interrupt request
format
I
W2
W1
W0
Read/write logic:
This has five signals. , , and the address lines A0 and A1. In the peripheral I/O
mode, the and signals are connected to and respectively. In memory mapped I/O
these are connected to and address lines A0 and A1 of the CPU are usually
connected to lines A0 and A1 of the 8253/54 and is tied to a decoded address
Control word register:
The register is accused when lines A0 and A1 are at logic 1. It is used to write a
command word which specifies the counter to be used (binary or BCD) its mode
and either a read or write operation
Counters:
These 3 functional blocks are identical in operation. Each counter consists of a
single, 16 bit, presettable, down counter. The counter can operate in either binary
or BCD and its input, gate and output are configured by the selection of modes
stored in the control word register. The counters are fully independent. The
programmer can read the contents of any of the 3 counters without disturbing the
actual count in progress
Pin diagram:
Operational description:
The complete functional definition of the 8253/54 is programmed by the system
software. Once programmed the 8253/54 is ready to perform whatever timing tasks
it is assigned to accomplish.
Programming the 8253/54:
Each counter of 8253/54 is individually programmed by writing a control word
into the control word register (A0A1=11). The following figure shows the control
word format. Bits SC1 and SC0 select the counter bits RW1 and RW0 select the
read. Write or catch command bits M2, M1 and M0 select the mode of operation
and bit BCD decides whether it is a BCD counter or binary counter
WRITE operation:
Write a control word into control register
Load the low order byte of a count in the counter register
Load the high order byte of count in the counter register
D7
SC1
D6
SC0
D5
RW1
D4
RW0
D3
M2
D2
M1
D1
M0
D0
BCD
READ operation:
In some applications especially in event counter it is necessary to read the value of
the count in progress. This can be done by 3 possible methods
Simple read:
It involves reading a count after inhibiting the counter by controlling the gate input
or the clock input of the selected counter and two I/O read operations are
performed by the CPU. The first I/O operation reads the low order byte and the
second I/O operation reads the high order byte
Counter latch command:
In this method an appropriate control word is within into the control register to
latch a count in the output launch and two I/O read operations are performed by the
CPU. The first I/O operation reads the low order byte and the second I/O operation
reads the high order byte
Read back command (available only for 8254):
This method uses the read back command. This command allows the user to check
the count value programmed mode and the current status of OUT pin and null
count flag of the selected counters
D7
1
D6
D5
D4
D3
CNT2
D2
D1
CNT1
CNT0
D0
0
RW1
1
RW0 M2
1
0
M1 M0 BCD
0 0
0
=BOH
Source program:
MVI A, BOH
OUT OBH
MVI A, lowbyte (30H)
OUT 0AH
MVI A, highbyte (COH)
OUT 0AH
SERIAL DATA TRANSFER (USART) 8251:
Most of the processors are designed for parallel communication. In parallel
communication number of lines required to transfer data depend on the number of
bits to be transformed. In serial communication one bits is transferred at a time
over a single line.
Features of 8251A:
The Intel 8251A is an universal synchronous and asynchronous
communication controller.
It supports standard asynchronous protocols with 5 to 8 bit character format.
Odd, even and no parity generation and detection.
Band rate from DC to 19.2K band.
False start bit detection.
Automatic break detect and handling.
Break character generation.
It has build in band rate generator.
It supports standard synchronous protocols with 5 to 8 bit character format.
Internal or external character synchronous.
Automatic sync insertion.
Baud rate from DC to 64K baud.
It allows full duplex transmission and reception.
It provides double buffering of data both in the transmission section and in
the receive section.
It provides error detection logic which detects parity overrun and framing
errors.
It has modern control logic which supports basic data set control signals.
It provides separate clock inputs for receiver and transmitter sections thus
providing an option of fixing different band rates for the transmitter and
receiver section.
It is compatible with an extended range of Intel microprocessor.
It is fabricated in 28 pin DIP package and its all inputs and outputs are TTL
compatible.
It is available in standard as well as extended temperature range.
Block diagram:
The figure shows the block diagram of IC 8251A. it includes data bus buffer,
read/write control logic, modem control, transmit buffer, transmit control, receiver
buffer and receiver control.
Data bus buffer:
This tri state, bi-directional, 8 bit buffer is used to interface 8251 to the system data
bus. Along with the data, control word, command words and status information are
also transferred through data bus buffer
Pin Diagram:
Transmit buffer:
The transmit buffer accepts parallel data from CPU adds the appropriate framing
information serializes it and transmits it on the TxD pin on the falling edge of . It
has two registers. A buffer register to hold eight bit and an output register to count
eight bits into a stream of serial bits. The CPU write a byte in a buffer register
which is transformed to the output register when it is empty. The output register
then transmits serial data on the TxD pin
Transmit control:
It manages all activities associated with the transmission of serial data. It accepts
and issues signals both externally and internally to accomplish this function.
TxRDY (transmit ready):
This output signal indicates CPU that buffer register is empty and the USART is
ready to accept data character. It can be used as an interrupt to the system or for
parallel operator the CPU can check TxRDY using the status read operation. This
signal is reset when a data byte is loaded into the buffer register
TxE (transmitter empty):
This is an output signal. A high on this line indicates that the output buffer is
empty. In the synchronous mode, if the CPU has failed to load a new character are
loaded into TxE will go high momentarily as SYNC characters are loaded into the
transmitter to fill the gap in the transmission
TxC:(transmitter clock):
This clock controls the rate at which characters are transmitted by USART. In the
synchronous mode is equivalent to the band rate and is supplied by the modem. In
asynchronous mode is 1, 16 or 64 times the band rate. The clock division is
programmable. It can be programmed by writing proper mode word in the mode
set register.
Receiver buffer:
The receiver accepts serial data on the RxD line. Convert this serial data to parallel
format checks for bits and characters that are unique to the communication
techniques and sends an assembled characters to the CPU
In the synchronous mode the receiver simply receives the specified number of data
bits and transferred them to the receiver input register and then to the receiver
buffer register
Receiver control:
It manages all receiver related activities. Along with the data reception it does false
start bit detection, parity error detection, framing error detection, sync detection
and break detection.
RxRDY (receiver ready):
This is an output signal. It does high (active), when the USART has a character in
the buffer register and is ready to transfer it to the CPU. This line can be used
either to indicate the status in the status register or to interrupt the CPU. This is
signal reset when a data byte fro receiver buffer is read by CPU.
RXC: (receiver clock)
This clock controls the rate at which the character is to be received by USART in
the synchronous mode is equivalent to the band rate and is supplied by the modem.
In asynchronous mode is 1, 16 or 64 times the band rate. The clock division is
programmable. It can be programmed by writing proper mode word in the mode
set register
Modem control:
The 8251 has a set of control inputs and outputs that can be used to simplify the
interface to almost any modem. It provides control gravity for the generation of
and the reception of and . In addition a general purpose inverted output and a
general purpose input are provided. The output is labled and input is labled as
can be assets by setting bit 2 of the command instruction DSR can be sensed by 7 th
bit of status register
8251A control words:
The control words defines the complete functional definition of 8251A and they
must be loaded before any transmission or reception. The control words of 8251A
are splitted into two formats
Mode instruction
Command instruction
Mode instruction format:
D7
D6
D5
D4
D3
D2
D1
D0
D3
SBRK
D2
RXE
D1
DTR
D0
TXEN
D6
D5
D4
SYNDET/BRKDET FE
OE
D3
PE
D2
D1
D0
TXEMPTY RXRDY TXRDY
In the receiver section the received character is stored in the receiver buffer. The
CPU is supposed to read this character before reception of the next character. But
if CPU fails in reading the character loaded in the receiver buffer the next received
character replaces the previous one and the overrun error occurs.
Framing error:
If valid stop bit is not detected at the end each character framing error occurs.
All these errors when occur set the corresponding bits in the status register. These
error bits are reset by setting ER bit in the command instruction.
Data communication types:
8251A is universal, synchronous, asynchronous receiver and transmitter. Therefore
communication can take place in four different ways
Asynchronous transmission
Asynchronous reception
Synchronous transmission
Synchronous reception
KEYBOARD AND DISPLAY CONTROLLER (8279):
Features of 8279:
IC 8279 provides a scanned interface to a 64 contact key matrix with two
more keys CONTOL and SHIFT.
It provides 3 input modes for keyboard interface.
o Scanned keyboard mode
o Scanned sensor matrix mode
o Strobed input mode
It has built in hardware to provide key de-bounce.
It allows key depressions in 2 key lockout or N-key rollover mode which
eliminates software required to implement 2 key lockout and N-key rollover
mode.
The interrupt output of 8279 can be used to tell CPU that the keypress is
detected. This eliminates the need of software polling.
It provides 8 byte FIFO RAM to store key-codes. This allows to store 8 key
board inputs when CPU is busy in performing his own computation.
It provides multiplexed display interface with blanking and inhibit options.
It provides sixteen byte display RAM to store display codes for 16 digits
allowing to interface 16 digits.
It provides two output modes for display interface.
Left entry (typewriter type).
Right entry (calculator type).
Simultaneous keyboard and display operation facility allows to interface
keyboard and display software.
Block diagram:
Figure shows the block diagram of 8279. It consists of four main sections
CPU interface and control sections
Scan section
Keyboard section
Display section
CPU interface and control section
This section consists of data buffers, I/O control, control and timing registers and
timing and control logic.
Data buffers:
The data buffers are 8 bit bidirectional buffers that connect the internal data bus to
the external data bus.
I/O control:
The I/O control section uses the A0, , and signals to control data flow to and from
various internal registers and buffers. The data flow to and from the 8279 is
enabled only when =0 otherwise the 8259 signals are in a high impedance state.
Display can use all 16 scan lines to interface 16 digit 7 segment display but
keyboard can use only 8 scan lines out of 16 scan lines.
Decoded mode:
In this mode the internal decoder decodes the least significant 2 bits of binary
count and provides four possible combinations on the scan lines (SC 3-SC0): 1110,
1101, 1011, 0111. Thus the output of decoded scan is active low. This four active
low output lines can be used directly to interface 4 digit 7 segment display, 8x4
matrix keyboard, eliminating the external decoder
Keyboard section:
This section consists of return buffers, keyboard de-bounce and control,
FIFO/sensor RAM and FIFO/sensor RAM status
Display section:
The display section consists of
Display RAM
Display address registers
Display registers
Pin Diagram:
DB0-DB7 bidirectional data bus
read
write
A0 address line
- chip select
RESET reset
CLK clock
IRQ interrupt request
RL0-RL7 return lines
CNTL/STB control/strobe
OUT A3-A0, OUT B3-B0 output lines
blank display
Operating modes:
Input modes:
The 8279 provides 3 basic input modes
Scanned keyboard
Scanned sensor matrix
Strobed input
In scanned keyboard mode keyboard can be scanned in two ways: encoded scan &
decoded scan
In scanned sensor matrix mode image of the sensor matrix is kept in the sensor
RAM. The status of the sensor switches are input directly to the sensor RAM
In strobed input mode data is entered to the FIFO RAM from the returned lines.
The data is entered at the rising edge of the CNTL/STB signal
Display modes:
The 8279 provides 2 basic output modes
Left entry (typewriter type)
Right entry (calculator type)
The below figure shows the analog output voltage plotted against all 16 possible
digital input words
DAC 1408:
The IC 1408 consists of a reference current amplifier an R/2R ladder and eight
high speed current switches. It has 8 input data lines A1 (MSB) through A8 (LSB)
which controls the positions of current switches.
It requires 2 mA reference current for full scale input and two power supplies
VCC=+5V and VEE=-15V (VEE can range from -5V to -15V)
The voltage Vref and resister R14 determine the total reference current source and
R15 is generally equal to R15 to match the input impedence of reference current
amplifier
Interfacing DAC 1408/0808 with 8085 microprocessor using 8255:
The following figure shows the interfacing of DAC 0808 with microprocessor
8085. Here the programmable peripheral interface 8255 is used as parallel port to
send the digital data to DAC.
I/O map for 8255:
Port/register
Port A
Port B
Port C
Control register
Address
00
01
02
02
Program:
MVI A, 80H
OUT 03
MVI A, Data
OUT 00
The following figure shows the digital output of an ideal 3 bit ADC plotted against
the analog input voltage
ADC 0808/0809 has eight input channels so to select deviced input channel it is
necessary to send 3 bit address on A, B and C inputs. The address of the desired
channel is sent to the multiplexer address inputs through port pins. After at least
50ns this address must be latched. This can be achieved by sending ALE signal.
After another 2.5s the start of conversion (SOC) signal must be sent high and
then low to start the conversion process. To indicate the end of conversion it
activates EOC signal. The microprocessor system can read converted digital word
through data bus by enabling the output enable signal after EOC is activated
The DMA I/O technique provides direct access to the memory while the
microprocessor is temporarily disabled.
This chapter also explains the operation of disk memory systems and video
systems that are often DMA-processed.
Disk memory includes floppy, fixed, and optical disk storage. Video systems
include digital and analog monitors.
Basic DMA operation
The direct memory access (DMA) I/O technique provides direct access to
the memory while the microprocessor is temporarily disabled.
A DMA controller temporarily borrows the address bus, data bus, and
control bus from the microprocessor and transfers the data bytes directly
between an I/O port and a series of memory locations.
Two control signals are used to request and acknowledge a DMA transfer in
the microprocessor-based system.
The HOLD signal is a bus request signal which asks the microprocessor to
release control of the buses after the current bus cycle.
The HLDA signal is a bus grant signal which indicates that the
microprocessor has indeed released control of its buses by placing the buses
at their high-impedance states.
The HOLD input has a higher priority than the INTR or NMI interrupt
inputs.
The 8237 supplies memory & I/O with control signals and memory address
information during the DMA transfer.
actually a special-purpose microprocessor
whose job is high-speed data transfer between memory and I/O
Status register
The 8237 DMA controller supplies the memory and I/O with control signals
and memory address information during the DMA transfer.
The current address register holds a 16-bit memory address used for the
DMA transfer.
each channel has its own current address
register for this purpose
When a byte of data is transferred during a DMA operation, CAR is either
incremented
or decremented.
depending on how it is programmed
The current word count register programs
a channel for the number of bytes (up to 64K) transferred during a DMA
action.
The number loaded into this register is one less than the number of bytes
transferred.
for example, if a 10 is loaded to CWCR, then
11 bytes are transferred during the DMA action
The base address (BA) and base word count (BWC) registers are used
when
auto-initialization is selected for a channel.
In auto-initialization mode, these registers
are used to reload the CAR and CWCR
after the DMA action is completed.
allows the same count and address to be used
to transfer data from the same memory area
The command register programs the operation of the 8237 DMA controller.
The register uses bit position 0 to select the memory-to-memory DMA
transfer mode.
memory-to-memory DMA transfers use DMA channel 0 to hold the
source address
When the word count ``rolls over'' from zero to FFFFH, a Terminal Count
(TC) will cause an Auto initialize if the channel has been programmed to do
so.
DREQ need only be held active until DACK becomes active. Again, an
Auto initialization will occur at the end of the service if the channel has been
programmed for it.