CH 41

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CHAPTER 41
MICROELECTRONIC MANUFACTURING AND
ELECTRONIC ASSEMBLY
41.1 INTRODUCTION
41.2 HOW ELECTRONIC PRODUCTS
ARE MADE
41.3 SEMICONDUCTORS
41.4 HOW INTEGRATED CIRCUITS
ARE MADE
41.5 HOW THE SILICON WAFER IS MADE
41.6 FABRICATING INTEGRATED

CIRCUITS ON SILICON WAFERS
41.7 THIN-FILM DEPOSITION
Physical Vapor Deposition
Chemical Vapor Deposition
Epitaxial Growth
Integrated Circuit Component
Interconnection
Integrated Circuit Yield and

Economics
41.8 INTEGRATED CIRCUIT PACKAGING
Package Types
Packaging Processes
41.9 PRINTED CIRCUIT BOARDS
41.10 ELECTRONIC ASSEMBLY
& 41.1 INTRODUCTION

Miniaturized microelectronic circuits are in common use today in wristwatches, portable CD players, cellular phones, home entertainment systems, fax machines, artificial
hearts, military satellites, automotive fuel injection systems, and cardiac defibrillators,
among others. Over the past three decades, the number of components per integrated
circuit has increased from 2300 in 1971 to 42 million in 2001, while the number of calculations per second has increased 100,000 times, from 10,000 to more than a billion. The
key to this progress has been the development of large-batch-size, semiconductor-processing methods coupled with miniaturization of electrical components and connectors.
Unlike most other manufacturing processes in this book, semiconductor processes and
other electrical and electronic manufacturing processes are concerned mainly with the
manipulation of electrical properties rather than mechanical properties.
& 41.2 HOW ELECTRONIC PRODUCTS ARE MADE

The goal of all electronics is the processing and manipulation of electrical signals represented most fundamentally by the flow of electrons. A hierarchy for producing electronic products is illustrated in Figure 41-1. At the lowest level, microelectronic
fabrication methods produce entire integrated circuits (ICs) of solid-state (no moving
parts) components, complete with wiring and connections, on a single piece of semiconductor material. Arrays of ICs are produced on thin, round disks of semiconductor
material called wafers. Once the semiconductor wafer has been processed, the finished
wafer is sectioned into individual ICs, or chips. Next, these chips are individually housed
within various types of IC packages for connection to other electronic components and
protection from environmental elements. These IC packages, along with other discrete
components (e.g., resistors, capacitors, etc.), are then combined together into even
larger circuits on printed circuit boards (PCBs). This is sometimes referred to as electronic assembly. Electronic packages at this level are called cards or printed wiring
assemblies (PWAs). Next, series of cards are combined on a backpanel PCB, also
known as a motherboard or simply a board. This level of packaging is sometimes
referred to as card-on-board packaging. Ultimately, card-on-board assemblies are put
into housings and integrated with power supplies and other electronic peripherals
through the use of cables to produce final commercial products.
In general, the lower the level of integration (i.e., the physically smaller the circuit
and its components) within this hierarchy, the less expensive it is to produce in terms of
cost per functional element. This is because, to some extent, the manufacturing cost per
1144
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SECTION 41.3
1145
Semiconductors
Silicon wafer
Microelectronic
manufacturing
Level 1
Die
Level 2
Cover
chip
Packaging
C
S
O
O
or
Integrated
circuit (IC)
on chip
IC
Package for
connection
Level 1
PCB fab
Computer
PCB
assembly
Motherboard
Level 3
Level 5
Level 4
FIGURE 41-1 The hierarchy for producing electronic products has many levels. (M. L. Minges, Electronic Materials Handbook,
Volume 1, Packaging, Materials Park, OH: ASM International, 1989)
IC is about the same regardless of how many components are packaged onto the chip.
At the same time, the lower the level of integration is, the less flexibility in configuring
the electronic system for different commercial applications. This balance between cost
and flexibility is primarily what drives designers to implement circuits at various hierarchical levels.
& 41.3 SEMICONDUCTORS

Semiconductorssuch as silicon, gallium arsenide, and germaniumare materials that
can be made to be either electrically conducting or electrically insulating by changing
the type and concentration of impurity atoms found within the material. Like metals,
all semiconductors have crystalline microstructures exhibiting long-range order in the
form of a lattice. However, unlike metals, semiconductor atoms are characterized as
having half-filled valence shells, and so, when placed into a lattice, the semiconductor
atoms form covalent bonds. Figure 41-2a shows a schematic of a lattice of covalently
bonded silicon atoms.
At room temperature (25 C), silicon permits a small amount of electrical conductivity that is too small for most electronic applications. The electrical conductivity of
semiconductors can be altered by inserting impurity atoms into the semiconductor lattice. The process of modifying the electrical properties of semiconductors by introducing impurity atoms is commonly referred to as doping. Figure 41-2b shows the same
lattice as before with the middle silicon atom having been replaced by a phosphorous
atom. Because phosphorous is a Column V element on the periodic chart, the phosphorous atom has one more valence electron than the surrounding silicon atoms. As such,
the phosphorous atom is considered a donor of electrons to the silicon lattice and the
phosphorus-doped semiconductor is now called an n-type (negatively charged type)
semiconductor. N-type semiconductors have extra valence electrons, which are free to
move about, providing increased electrical conductivity. Similarly, Figure 41-2c shows a
third silicon lattice, this time with the middle silicon atom replaced by a boron atom (a
Column III element). This lattice has a shortage of electrons represented as electron
holes and is therefore termed a p-type (positively charged type) semiconductor.
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CHAPTER 41
Microelectronic Manufacturing and Electronic Assembly

Covalent
bond
Si
+4
Valence
electrons
Si
+4
+4
Free electron
Si
Si
Si
+4
+4
+4
+4
+4
Si
Si
+4
+5
+4
+4
+4
Si
Si
Si
(a)
+4
Si
+4
Si
+4
Si
Si
+5
Si
Si
+4
(b)
+4
+4
Si
Si
Si
FIGURE 41-2 (a) Schematic of

a lattice of silicon atoms; (b)
doping with impurity atoms
changes conductivity to n-type
semiconductor or (c) to p-type,
positively charged
semiconductor. (J. Millman,
Microelectronics: Digital and
Analog Circuits and Systems,
New York: McGraw-Hill, 1979)
+4
+4
+4
Si
Hole
Si
+4
+3
+4
Si
+4
Si
B
Si
(c)
+4
+4
Si
Silicon is the most widely used semiconductor. It is plentiful and can be readily
produced in single crystal form. Also, the native oxide, silicon dioxide, can be used both
as a dieletric layer and a diffusion mask during processing.
& 41.4 HOW INTEGRATED CIRCUITS ARE MADE

The ability to selectively modify the electrical properties of semiconductors is the
backbone of microelectronic manufacturing as shown in the following examples for
producing IC components. A simple bipolar diode (allows current flow in only one
direction) may be fabricated by forming two adjacent regions of n-type and p-type
semiconductors whose electrical properties have been modified through the placement of impure, secondary atoms into the semiconductor lattice. At the interface of
the regions, a so-called p-n junction is formed (Figure 41-3a). In the p-n junction, the
excess electrons (from the n-type semiconductor) and holes (from p-type) recombine
to form a depletion region, where all charge mobility (i.e., via electrons and holes) is
effectively eliminated. While the recombination of holes and electrons fills out the
valence shells in the lattice, an imbalance in charge exists, creating an electrostatic
potential called the barrier potential. The barrier potential for a p-n junction in silicon
is approximately 0.7 V. Application of a negative potential to the cathode and a positive potential to the anode (forward bias) at a level greater than the barrier potential
of the p-n junction results in a flow of electrons (or holes) as shown in Figure 41-3b. In
this state, the diode acts as a closed switch with very little electrical resistance. Application of a reverse bias (Figure 41-3c) causes the diode to act as an open switch with
very high electrical resistance.
As shown in Figure 41-4, the manufacturing fabrication sequence for making a
simple bipolar diode has many steps, beginning with the production of a silicon wafer
from a predoped, single crystal ingot (boule), which is cut into wafers, lapped, and polished to produce silicon wafers. The wafers are placed in vacuum chambers, where an
oxide layer is grown on the surface of the wafer to act as a mask during subsequent
doping of the substrate. The oxide layer is patterned using photolithography in combination with etching (see Figure 41-5). Photolithography is used to produce a polymeric
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SECTION 41.4
How Integrated Circuits Are Made
Anode (+)
P (+)
P (+)
N ()
Cathode ()
Depletion
region
N ()
Fixed charges
Mobile charges
(a)
1147
V=0
Anode (+)
e
Anode (+)
Cathode ()
Widened depletion
P (+)
N ()
region
Cathode ()
(c)
Holes
+
(b)
Anode (+)
Holes
Cathode ()
FIGURE 41-3 The diode is produced with a p-n junction or interface at (a) which allows electrons to flow at (b) or have high
electrical resistance at (c) (Texas Engineering Extension Service, Semiconductor Processing Overview, College Station, TX: The Texas A&M
University System, 1996)
mask over the oxide layer, which will allow only select areas of the oxide layer to be
etched. After etching, the polymeric mask is removed from the silicon dioxide layer,
and the n-type silicon is doped (by diffusion) with boron to produce a p-type region.
After doping, the silicon dioxide mask is removed, and a second silicon dioxide layer is
grown and patterned to establish openings in the silicon dioxide layer above the n-type
and p-type regions. Next, a thin metal film is deposited on top of the silicon dioxide to
provide an electrical pathway allowing the p-type and n-type regions of the diode to be
connected to an external power supply. Photolithography and etching are used once
again to pattern the thin film into leads and contact pads large enough for biasing the
device. To protect the final integrated device from mechanical damage and moisture, a
final passivation coating is added.
This example shows the production of a single IC component. Typically, multiple components and, further, multiple circuits are produced in parallel during IC fabrication. As shown in Table 41-1, IC fabrication has evolved from the original smallscale integration (SSI) architecture of the 1960s, with 2 to 50 electronic components
per circuit, to the ultra-large-scale integration (ULSI) architectures of today, with
tens of millions of components per circuit. The classification of ICs by scale of integration represents the successive advancement of semiconductor processing technologies
to provide lower cost, higher-performance ICs. Each increase in the number of components represented a breakthrough in miniaturization technology (e.g., photolithography and clean rooms) that permitted the fabrication of smaller IC
components with improved performance. To achieve lower cost, manufacturing
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CHAPTER 41
1. Material preparation (P+ wafer)
2. Epitaxial growth (P)
3. Mask oxide and

photolithography
4. Etch and diffusion

and oxide removal
5. Mask removal and

fresh oxidation (gate oxide)
6. Deposited polysilicon
7. Photolithography
8. Etch
9. Photolithography
10. Ion implantation
11. Oxide deposition
12. Photolithography
13. Etch
14. Metallization
15. Photolithography
16. Etch
17. Final overcoat
FIGURE 41-4 The manufacture of a simple metal-oxide-semiconductor (MOS) field effect transistor device requires many steps
as shown here. Source: Semiconductor Processor Overview, # 2008, Texas Engineering Extension Service. www.teex.org
TABLE 41-1
Classification in the Development of IC Architectures
Class
Number of Electrical
Components per IC
Applications
SSI
MSI
250
505,000
Basic logic
Encoders, multiplexers, etc.
LSI
5,000100,000
First generation microprocessors, memory ICs, early calculators, and electronic watches
VLSI
100,0001,000,000
Integration of microprocessor, memory and I/O on single chip, digital signal processors, computer
workstations and microcomputers
ULSI
Greater than 1,000,000
464 Mb memory ICs, latest microprocessors, advanced workstations and microcomputers
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SECTION 41.5
How the Silicon Wafer Is Made
Seed
Melt
FIGURE 41-5 In the

Czochralski method, a small seed
crystal is used to grow large
single crystals of silicon. (MEMC
Electronics International website,
www.memc.com)
Noncontaminating
liner
1149
Growing
crystal
Graphite
crucible
(a) Seed being
lowered down
to melt
(b) Seed dipped

in melt; freezing
on seed just
beginning
(c) Partially grown

crystal slowly
being withdrawn
from melt
processing technology breakthroughs were needed to make miniaturization technologies possible and economical. Today, this trend of seeking higher performance at
lower cost continues.
& 41.5 HOW THE SILICON WAFER IS MADE

One of the key reasons that single crystal silicon is the most widely used semiconductor
material is that it can be refined and grown economically in single crystal form. Here is
how it is done. Under equilibrium conditions, molten silicon (when cooled) produces a
polycrystalline structure. However, under controlled conditions, silicon can be grown
from a single seed in a large single crystal ingot called a boule. The technique used most
often for growing single crystal silicon is called the Czochralski method. In the
Czochralski method, a small seed crystal is lowered into molten silicon and raised
slowly, allowing the crystal to grow from the seed. The size of the seed crystal is about
0.5 cm in diameter and about 10 cm long. Its crystallographic orientation is critical
because it defines the crystallographic orientation of the boule, which controls
the electrical properties within the boule. The melt consists of electronic-grade
(99.999999999% pure) polycrystalline silicon (polysilicon). If desirable, dopant may be
added to the melt, although alloying complicates the crystal growth process. The silicon
is melted in a fused silica crucible within a furnace chamber backfilled with an inert gas
such as argon. The crucible is heated to approximately
1500 C and maintained at slightly above the melting point
TABLE 41-2 Typical Specifications for State-of-thewith a graphite resistance heater.
Art Silicon Wafer
Once grown, the boule is characterized for resistivity
Cleanliness (particle/cm2)
<0.03
and crystallographic defects. Table 41-2 provides a list of
Specified 3%
Oxygen concentration (cm3)
typical specifications for a silicon wafer. If acceptable, the
< 1.5 1017
Carbon concentration (cm3)
unusable end portions of the boule are cut off, and the outMetal contaminants bulk (ppb)
< 0.001
side of the body is ground into a cylindrical ingot. For diam< 0.1
Grown in dislocation (cm2)
eters less than 300 mm, flats are ground along the length of
<3
Oxidation induced stacking faults (cm3)
the ingot to denote crystal orientation and dopant type
Diameter (mm)
150
(Figure 41-6). The largest flat, called the primary flat,
Thickness (mm)
625 or 675
denotes the (011) plane. Flats are used to properly orient
Bow (mm)
10
wafers during IC processing. In larger-diameter boules,
Global flatness (mm)
3
notches are cut along the length of the boule to increase the
0.2
Cost ($/cm2)
surface area available for IC processing. Afterward, the
boule is chemically etched to remove any damage imparted
Source: Campbell, S. A., The Science and Engineering of Microelectronics,
Oxford: Oxford University Press, 2001.
while grinding the flat.
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CHAPTER 41
45 CW
(111) n-type
Secondary
flat
180 CW
Polished
surface
Primary flat denotes (011)
Secondary flat
(111) p-type
90 CW
Primary flat
(100) n-type
125-mm diameter or less
FIGURE 41-6 Flats are ground

on the boule to denote the (011),
(111), (100) planes, n-type and
p-type materials. (B. El-Kareh,
Fundamentals of Semiconductor
Processing Technology, Boston:
Kluwer Academic Publishers, 1995)
Primary
flat
Primary
flat
Secondary flat
(100) p-type
135 CW
Primary
flat
Secondary flat
(100) n-type
150-mm diameter or greater
Next, the boule is sliced into wafers using a wire or diamond saw. Geometric concerns resulting from wafer slicing include flatness and bowing of the wafer. The wafers
are typically ground on the edge because edge-rounded wafers handle better and have
less mechanical damage during IC processing, and the pile-up of photoresists on the
edge of the wafer during photolithography is minimized. Finally, a series of processing
steps are needed to remove any sawing damage, including lapping, chemical etching,
and polishing.
Single-crystal silicon, with few lattice imperfections, is necessary to produce the
high yields required in IC processing. Several sources of crystalline defects exist during
processing of the wafer, including contamination, improper pull rates, temperature gradients during pulling, and residual stress during wafer machining. Some methods exist
for controlling crystalline defects during processing, such as by rotating the solidified
boule and the melt in opposite directions during growth to minimize unbalanced growth
caused by temperature gradients. However, not all defects can be avoided. To keep
unwanted impurities and defects from diffusing into active regions of the wafer
(i.e., where IC components are made), a strategy known as gettering is used. Gettering
involves the use of hard-to-move crystalline defects in inactive regions of the wafer
(i.e., away from where components will be made) to trap other impurities and defects
that may otherwise diffuse into active regions thereby impairing device performance.
& 41.6 FABRICATING INTEGRATED CIRCUITS ON SILICON WAFERS

The first level of electronic manufacturing involves the manufacture of the ICs or chips.
This is a complex process involving many steps, the sequence of which depends on the
particular electrical device. The initial steps of doping by diffusion or ion implantation
and oxidation are performed in large machines that manipulate the wafers in and out of
various vacuum chambers in the correct sequence and duration.
Doping can be accomplished in bulk by alloying at the time of crystal formation.
However, selective doping is required for IC production. Selective doping in most early
IC devices involved thermal diffusion; more recently, as device dimensions have continued to shrink, ion implantation has become more suitable to better control the depth
and concentration of the dopant atoms in the silicon wafer. The doped lateral geometry
is primarily defined by the use of a low diffusivity mask (e.g., oxide mask) patterned by
lithography methods (covered later in this chapter). The depth and concentration are
controlled by the method of doping and its process parameters.
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Fabricating Integrated Circuits on Silicon Wafers
1151
One method for doping semiconductor materials involves diffusion. Diffusion can
be defined as the random migration of particles from regions of high concentration to
regions of lower concentration. Any solid solution that contains a concentration gradient will experience a redistribution of solute (dopant) concentration over time. The
source of this migration is the random motion characteristic of atoms above 0 K.
Single-atom movements can cause atoms to swap lattice locations with adjacent atoms,
move to adjacent vacancies, or move interstitially.
Diffusion doping of silicon substrates is usually carried out in two steps. First, a predeposition step is used to deposit a fixed quantity (dose) of dopant atoms through an oxide
mask and into the substrate. This may be done by placing the wafer in a furnace having a
gaseous atmosphere containing the required source concentration of dopant. Predeposition can also happen by solid-source and liquid-source doping. In solid-source doping, a
solid disk of the dopant material is placed in a furnace boat adjacent to the wafer where it is
heated and evaporated onto the wafer. In liquid-source doping, an inert gas is bubbled
through an isotropic solution (bath) containing compounds with the desired dopant. The
partial pressure of dopant in the furnace is controlled by the temperature of the bath, the
pressure of the gas above the liquid, and the flow of other inert gases into the furnace. Liquid-source doping has gained significant acceptance because of improved purity levels. Disadvantages include high corrosivity and sensitivity to temperature changes in the bath.
Once the dose is deposited in the predeposition step, a drive-in step is used to
redistribute the dose to achieve the proper depth and concentration. The drive-in step
is performed in a vacuum oven without the presence of the dopant source. The advantage of thermal diffusion is that it is fast relative to other doping processes. The disadvantage is less control over the depth and concentration of dopant profiles.
As the overall size of IC devices has decreased, the required thickness of doped
regions has also decreased, requiring greater control and precision of doped dimensions. Therefore, doping by thermal diffusion has been replaced by ion implantation
within the current generation of IC devices. Ion implantation involves electrostatically
accelerating a beam of ionized atoms or molecules toward the wafer surface, allowing
the resultant kinetic energy to drive the particles into the substrate. Ion implantation
has been found to control the amount of impurity and the depth of impurity penetration
much better than thermal diffusion.
One disadvantage of ion implantation is that the kinetic energy of the ion particles
damages the silicon substrate. The resulting lattice damage can significantly affect the
electrical and chemical properties of the single crystal substrate. This damage can be
minimized by annealing the substrates at temperatures up to 1000 C after ion implantation. However, annealing at these temperatures can create problems of its own, causing
redistribution of dopant profiles within other previously processed regions of the
device. To compensate, rapid thermal processing technologies have been developed to
reduce the time the wafer is exposed to high temperature. In rapid thermal annealing
(RTA), the wafer rests on quartz pins and is heated using a bank of high-intensity filament lamps. Problems with RTA include temperature measurement and thermal uniformity across the wafer. Excessive temperature gradients across the wafer can lead to
plastic deformation in the wafer such as warpage and/or slip. RT technologies have
been extended to include rapid thermal oxidation, chemical vapor deposition, and epitaxial growth, among others.
Under exposure to oxygen, a silicon surface oxidizes to form silicon dioxide, the
same underlying chemical makeup of window glass. Silicon dioxide is an excellent
dielectric material and so can be used as the gate dielectric in a MOSFET device or
as an isolation layer between layers of metal wires that interconnect IC components.
Thick oxides formed by thermal oxidation are generally used as masks during doping.
The major objective in thermal oxidation is to create an oxide layer of uniform thickness. While silicon readily oxidizes at room temperature, deep penetration of the oxide
into the single crystal is accelerated at high temperatures by thermal diffusion. From
this standpoint, thermal oxidation is similar to diffusion doping. Other methods for producing thin-oxide layers (e.g., for device isolation) do exist and are briefly discussed in
the section on deposition processes.
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Though similar in some ways, atomic diffusion in oxidation is different than in

doping. Compared with the number density of silicon (on the order of 5 1022 atom/
cm3), final dopant concentrations for active device regions within semiconductor substrates are small (on the order of 1017 atom/cm3), whereas oxygen concentrations are of
the same magnitude (1022 atom/cm3). Due to the large oxygen concentrations and the
stoichiomety of the reactions, about 46% of the silicon surface is consumed during
oxidation. That is, for every 1mm of SiO2 grown, about .046 mm of silicon is used.
The thermal oxidation of silicon is achieved by heating the substrate to temperatures typically in the range of 900 to 1200 C within an oxygen atmosphere. The atmosphere in the furnace can either contain pure oxygen (dry oxidation) or part oxygen and
water vapor (wet oxidation). Initially, the growth of silicon dioxide is a surface reaction,
and the growth rate depends on the reaction rate at the silicon surface. The chemical
reaction for dry oxidation at the wafer surface is:
Si O2 ! SiO2
41-1
Thin gate oxides can be prepared with a very high uniformity over the wafer and from
wafer to wafer using dry oxidation.
Because growth rates in wet oxidation are higher than in dry oxidation, wet oxidation is often used to grow thicker oxides. For thicker oxides, the arriving oxidant molecules must diffuse through the growing layer to get to the silicon surface in order to
react. The primary reason for the faster growth rate in wet oxidation is because water
vapor molecules are smaller than molecular oxygen and, therefore, diffuse more easily
within silicon. One disadvantage of wet oxidation is that the oxide layer is not as dense.
Therefore, wet oxidation is used in applications that are not subjected to electrical
stress, such as for diffusion masks.
Techniques like diffusion and oxidation are used to modify the electrical properties of the silicon wafer. Additional techniques are needed to transfer the shape of the
integrated circuit from the designers workstation to the semiconductor wafer. In particular, lithography and etching are two intermediate steps necessary to pattern the silicon dioxide films formed as diffusion masks and as electrically insulating layers in
components. In addition, these two steps are also needed to pattern the various conductive and insulating thin films necessary to fabricate and interconnect IC components.
Lithography is the process of transferring the geometric patterns of the IC design
to a thin layer of polymer, called a resist, producing a resist mask on the surface of the
silicon wafer. The purpose of the resist mask is to serve as a temporary barrier to etching
or implantation, allowing for the selective patterning of thin films (e.g., thin films of
deposited polysilicon, oxide, or metal for component fabrication, insulation, or interconnection) or the selective doping of semiconductor substrates underneath the resist
in various steps of IC processing. Lithography is the most complicated, expensive, and
critical process in mainstream microelectronic fabrication. A typical silicon IC device
technology may involve 15 to 20 different lithography patterns, each with feature sizes,
or linewidths, as small as 0.18 mm. Needless to say, the technologies needed to meet
these requirements are expensive. In the early 1990s, using dynamic random access
memory (DRAM) ICs as an example, lithography accounted for roughly one-third of
the total fabrication cost.
Several different lithography methods exist including: (1) photolithography, (2)
X-ray lithography, (3) electron-beam (e-beam) lithography, and (4) ion-beam lithography. The difference in the techniques is the source of ionizing radiation used to expose
the resist. The first two methods involve the use of electromagnetic radiation, whereas
the latter two involve particle radiation (i.e., an electron or ion beam). Lithography
techniques based on electromagnetic radiation are through-mask techniques, requiring
the use of a lithography mask to selectively pattern the resist, whereas techniques based
on particle radiation are direct-write techniques, indicating that the particle beams scan
the pattern onto the resist directly without the use of a mask. Photolithography is the
most common method and will be discussed here.
In photolithography, UV sources of radiation are used to expose UV-sensitive
materials called photoresists, or simply resists. The photomasks, sometimes called
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SECTION 41.6
1153
UV light
Oxide layer
Silicon
(1) Starting wafer with layer

to be patterned
Resist removed
Developer
(5) Immerse exposed wafer
in developer
Resist coating
applied
Soft bake
(2) Coat with photoresist

using spin coating
(3) Bake the resist to set its

dissolution properties
Resist
Silicon
oxide
(6) Hard bake
Mask
SiO removed
Silicon
Etchant
(7) Etch the film
Mask
(4) Expose resist by shining

light through a photomask
Silicon
oxide
Silicon
(8) Strip off the resist
FIGURE 41-7 The process of making an IC using photolithography has many steps. (S. A. Campbell, The Science and
Engineering of Microelectronic, Oxford: Oxford University Press, 2001)
reticles, are used to mask or screen parts of the surface from etching or doping processes. The photomask is a thin, high-optical-purity quartz plate onto which a thin film
of opaque material (such as chromium) has been deposited and patterned (selectively
etched). The photomask is patterned with the aid of computer-aided manufacturing
(CAM) techniques using the original IC design data from computer-aided design
(CAD) systems.
The photolithography process involves the sequence of steps shown in Figure 41-7.
First, a liquid photoresist is applied to the surface of the silicon oxide layer over the silicon
wafer. Typically, this is done with a process known as spin coating. In spin coating, centrifugal forces are used to produce a photoresist layer of uniform thickness. Next, the coated
wafer is soft baked on a hot plate or in an oven. In this step, solvents used to reduce the
viscosity of the photoresist during spin coating are evaporated, and adhesion between the
wafer and the photoresist is improved. After soft bake, the photoresist is exposed using a
photomask to transmit a pattern of electromagnetic radiation onto the surface of the photoresist. This step is performed using a machine called a stepper, because the lithographic
pattern of the device is indexed or stepped across the wafer, subjecting it to repeated
exposuresone for each chip you are making. Once the resist has been exposed, the
wafer is developed in a chemical solvent. Development removes the unwanted resist
materials, exposing the underlying material to be etched. Next, the resist is hard baked to
remove any remaining solvents after development and to further toughen the remaining
resist against downstream etching or implantation processes. Hard bakes generally take
longer and are at slightly higher temperatures than soft bakes. Once the downstream
etching or implantation has made use of the resist, a photoresist stripping step is necessary
for removal of the resist.
During exposure, the UV radiation that is transmitted through the photomask
selectively modifies the molecular weight of the polymer in desired regions. In positive
photoresists, the UV radiation is responsible for decreasing the molecular weight in
these regions by breaking molecular bonds. The lower molecular weight of these
regions makes them more soluble in the chemical developer. In negative photoresists,
the UV radiation increases the molecular weight of the exposed resist through crosslinking, making the exposed region more insoluble in the developer. These two types of
photoresists are contrasted in Figure 41-8.
Obviously, the most important requirementof the photoresist is that it resists the
downstream etching or implantation process. Other requirements important to the
function of resists are their resolution and sensitivity. Resolution refers to the smallest
linewidth that can be reproduced repeatably by the resist. The resolution of the resist is
strongly a function of the source of ionizing radiation or the exposure machine tool
used. Sensitivity refers to the amount of ionizing energy required to sufficiently modify
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CHAPTER 41
Resist
SiO2
Si Wafer
(a)
Exposed region
Mask
Resist
SiO2
Si
(b)
Positive resist
Negative resist
SiO2
SiO2
Si
Si
(c)
FIGURE 41-8 Photoresist

material can be made soluble
(positive) or insoluble (negative)
to the developer. (R. C. Jaeger,
Introduction to Microelectronic
Fabrication (Modular Series on
Solid State Device Volume 5),
New York: Addison-Wesley, 1990)
SiO2
SiO2
Si
Si
(d)
the solubility of the resist. The more sensitive a resist is, the shorter the exposure cycle
time and the greater the throughput. A final requirement of the resist is that it adheres
to the substrate.
In the past, the most commonly used light source in photolithography was the
mercury arc lamp. Its most useful wavelengths for photolithography occur at 436 and
365 nm (blue and UV light, respectively)the so-called mercury g-line and i-line. As a
result, g-line and i-line photoresists have long been used as standards within the IC
industry. Negative photoresists were popular in the early history of IC processing
because of their low cost and good adhesion, but positive photoresists are now most
widely used because they offer better process control for small geometric features.
Schematic of the exposure step in photolithography are shown in Figure 41-9.
Exposure begins with photomask alignment. The photomask is aligned with the wafer
so that the pattern can be transferred onto the wafer surface. Each pattern after the first
one requires photomask alignment to the previous pattern. For linewidths on the order
of (current IC resolutions), misregistration errors as small as 6 nm can have detrimental
effects on device performance. This registration requirement contributes to the high
cost of lithography equipment.
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1155
Mask/reticle
Resist
Oxide layer
Wafer
Lens 1
Ultraviolet
light
source
Mask
Lens
Lens 2
Mask
SiO2
Space
Wafer
Contact printing
Photoresist
Photoresist
Wafer
Proximity printing
Wafer
Projection printing
SiO2
FIGURE 41-9 The exposure step in photolithography is shown in upper left with three primary exposure
methods. (R. C. Jaeger, Introduction to Microelectronic Fabrication (Modular Series on Solid State Device
Volume 5), Addison-Wesley Publishing Company, New York, 1990; and P. V. Zant, Microchip Fabrication: A
Practical Guide to Semiconductor Processing, New York: McGraw-Hill, 2000)
Once the photomask has been accurately aligned with the pattern on the wafers
surface, the photoresist is exposed through the photomask with a high intensity ultraviolet light. Three primary exposure methods exist: contact printing, proximity printing,
and projection printing, as shown in Figure 41-9.
In contact printing, the resist-coated silicon wafer is brought into physical contact
with the photomask. The wafer is held on a vacuum chuck, and the whole assembly rises
until the wafer and photomask contact each other. The photoresist is exposed with UV
light, while the wafer is in contact position with the photomask. Because of the contact
between the resist and photomask, very high resolution is possible in contact printing
(e.g., 1-mm features in 0.5 mm of positive resist). The problem with contact printing is
that debris trapped between the resist and the photomask can damage the photomask
and cause defects in the resist mask.
Proximity printing is similar to contact printing except that a small gap, 1 to 25 mm
wide, is maintained between the wafer and the photomask during exposure. This gap
minimizes, but may not eliminate, resist mask damage entirely due to particles between
the photomask and the wafer. Proximity printing offers higher throughput than the
other methods but is limited in resolution. Approximately 2- to 4-mm resolution is possible with proximity printing.
Projection printing avoids photomask and resist-mask damage entirely. An image of
the photomask is projected onto the resist-coated wafer, which can be many centimeters
away. To achieve high resolution, only a small portion of the resist layer can be imaged
thus, the need to scan or step the small image over the surface of the wafer. Projection printers that step the photomask image over the wafer surface are called step-and-repeat systems, or steppers. Step-and-repeat projection printers are capable of submicron resolution.
After photolithography, the next step is the permanent removal of an underlying
film or substrate by etchingby chemical or physical means or both. Typical materials
etched during semiconductor processing include silicon dioxide to make diffusion
masks, dielectric layers, and thin-metal films for device fabrication and interconnection.
Typical etch rates in semiconductor processing are on the order of several hundred to
several thousand Angstrom per minute.
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CHAPTER 41

Mask
Chrome
Lithography
bias
FIGURE 41-10 Deviations

from the lateral dimensions in the
resist mask are called etch bias,
produced here by isotropic
behavior of the etchant. (S. A.
Campbell, The Science and
Engineering of Microelectronic,
Oxford: Oxford University Press,
2001)
Photoresist
Oxide
Wafer
Etch bias
The objective in etching is to produce the proper lateral dimensions of the IC in

the target material while minimizing the removal of the mask and substrate (underlying
the target) materials. Lateral dimensions in etching are controlled in large part by a
resist (or perhaps an oxide) mask patterned as described in the lithography section.
Deviations from the lateral dimensions in the resist mask are called etch bias.
Etching through the resist mask is typically accomplished by either wet chemical
etching or dry plasma etching. Wet etching involves the immersion of the lithographically patterned wafer in a liquid etchant. The etchant removes material exposed
through the resist mask, creating soluble by-products. A rinsing procedure is used to
terminate the etching process. Critical parameters in wet-etching processes include
immersion time, etchant concentration, and etchant temperature. Poor control of process parameters can cause underetching or overetching. Underetching of oxide masks
may cause electrical opens in doped regions. In thin films, underetching can cause electrical shorts. Overetching results in etch bias due to undercutting of the mask. Undercutting is the lateral extent of the etch beneath the mask. Overetching can also cause
damage to the properties of substrate materials or to the geometry of the resist mask,
resulting in further bias.
One way to minimize damage in mask and substrate materials is to use an etchant
with high selectivity. Selectivity of an etchant refers to the ratio of its etch rate in the
target material to its etch rate in the mask or substrate material. As an example, hydrofluoric (HF) acid has a nearly infinite selectivity over silicon in the making of a diffusion
mask. However, one disadvantage of using HF to etch is that the etch process is isotropic, meaning that it proceeds equally in all directions. As shown in Figure 41-10, isotropic etching results in an etch bias caused by undercutting.
Dry etching refers to those plasma-assisted etching techniques sometimes called
gas-phase chemical etching. There are three main types of plasma-assisted etching,
with the main difference being the gas pressure (vacuum) inside the plasma and, consequently, the kinetic energy generated by ions formed within the plasma. Plasma etching
involves the use of a partially ionized gas (plasma) to chemically react with the target
material surface, producing gaseous by-products.
At the opposite end of the dry-etching spectrum is sputter etching or ion milling.
Sputter etching involves no chemical reaction with the target. Etching of target materials simply involves the physical removal of target atoms as electrostatically accelerated
plasma ions slam into the target substrate. As such, sputter etching is the micromechanical equivalent of sandblasting. High-etch anisotropy is possible with sputter etching,
meaning the etch is very directional with very little undercutting.
A cross between plasma etching and sputter etching is ion-assisted etching, better
known as reactive ion etching (RIE). In RIE, plasma ions bombard the target material,
creating physical damage, which increases the rate of chemical etching.
Table 41-3 compares the anisotropies, resist selectivities, and etch rates of the dry
etching processes.
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TABLE 41-3
1157
Thin-Film Deposition
Types of Dry Etching

Plasma Etching
Reactive Ion Etching
Sputter Etching
Relative excitation energy
Low
Medium
High
Relative chance of radiation damage
Low
Medium
High
Relative selectivity
Undercut, directionality
High
Isotropic
Low
Highly anisotropic
Low
Pressure (vacuum)
Greater than 100 mtorr
Medium
Directional from quasi-isotropic (slope) to
anisotropic (vertical profile)
Approximately 100 mtorr
Etch rate
High
Medium
TABLE 41-4
Less than 100 mtorr
Some Common Applications of Deposited Thin Films and the Processes Used to Make Them
Process
Function
VPE
MBE
Single-crystal
Si
Single-crystal
GaAs
APCVD
LPCVD
PECVD
Sputtering
SiO2,
PSG
SiO2,
PSG
W, TiN
TiN
Al, Cu
SiO2,
PSG
SiO2,
Si3N4, PSG
Evaporation
Component Fabrication
Growth of higher purity
semiconductor for increased
device performance
Si3N4
Masking layer during oxidation

Dopant source for diffusion
Doped
polysilicon
Metal and Dielectric Layers

Dielectric layer for component
fabrication
BPSG
Conduction path for component

fabrication
SiO2,
SiO3N4
Doped
polysilicon
Component Interconnection
SiO2,
PSG
Dielectric layer for component

interconnection
Conduction path for component
interconnection
Al, Cu
IC Packaging
Passivation of the IC after
processing
& 41.7 THIN-FILM DEPOSITION

In semiconductor processing, many thin layers of material must be deposited on top of
the semiconductor substrate to build IC component features such as transistor gates and
to interconnect IC components to form electrical circuits. These layers of material
are often well below in thickness, and so the term thin films is used to describe them.
Table 41-4 illustrates some typical ways that thin films are used in semiconductor
processing. Various thin film deposition processes are necessary to accomplish these
objectives. In general, deposition processes can be broken down into physical vapor
deposition (PVD) and chemical vapor deposition (CVD) processes.
PHYSICAL VAPOR DEPOSITION

Physical vapor deposition (PVD) processes include both evaporation and sputtering.
The simplest form of PVD is evaporation. In evaporation, the substrate is coated by
condensation of a metal vapor.The vapor is formed from a source material called the
charge, which is heated within a crucible in moderate vacuum (below 1 millitorr) at a
high temperature (greater than 1000 C). Heat energy is provided by either electrical
resistance or an electron beam. Electron-beam heating has the advantage of reducing
contamination of the deposited thin film because it does not require crucible heating
and, consequently, outgassing of the crucible.
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Metal target ( bias)
Gas
distribution
system
Metal
target
Sputtered
metal
atoms
Deposition
chamber
13.56 MHz
Wafer
(+) Ions (from process gas)

(+ bias)
Vacuum system
FIGURE 41-11 Sputtering is a PVD method for depositing thin films on microelectronic devices. (Texas Engineering Extension
Service, Semiconductor Processing Overview, College Station, TX: The Texas A&M University System, 1996)
While early semiconductor technologies utilized evaporation, it is not used in

mainstream processes today. The major disadvantage of evaporation is poor step coverage. Step coverage is important to avoid openings in wires that connect components
during late-stage processing where the surface of the wafer can have severe topology as
a result of the many deposition and etching steps. Step coverage has become even more
important because the lateral dimensions of circuits continue to decrease with little
change in vertical dimensions, resulting in device features with higher aspect ratios.
Another disadvantage of evaporation is that it is limited primarily to the deposition of
pure metals, although deposition of alloys can be accomplished with difficulty.
Dielectrics and polysilicon cannot be deposited by evaporation. Finally, the uniformity
of film thickness is hard to control over a large substrate.
An alternative PVD method for metal deposition is sputtering. The physics of
sputtering are much the same as reactive ion etching. As shown in Figure 41-11, two
electrodes are placed several centimeters apart in a low-pressure gas (typically, argon,
at about 100 millitorr). A potential is placed across the electrodes forming a plasma.
Plasma ions are accelerated toward the cathode on which is placed the charge material.
At moderate ion energies, atoms and clusters of atoms are ejected from the charge
material surface and accelerated toward the wafer.
One advantage of sputtering over evaporation is better step coverage due largely
to greater transport energies leading to enhanced surface mobility of the atoms on the
wafer. Further, sputtering can be performed on a wide range of materials including elemental metals, alloys, and dielectrics. For metals, a simple DC power source can be used
to generate the plasma. For dielectrics, a radio frequency RF plasma is required. Due to
its advantages, sputtering has replaced evaporation for most silicon-based technologies,
although deposition rates for sputtering are lower than those for evaporation and
require more expensive equipment.
CHEMICAL VAPOR DEPOSITION

Chemical vapor deposition (CVD) processes involve the growth of a thin film on a
heated substrate by chemical reactions between the substrate and a gaseous compound
containing reacting species. In general, CVD techniques provide the advantage of uniform step coverage and, therefore, have become the preferred deposition method for
many materials. Figure 41-12 shows a simple configuration for an atmospheric pressure
CVD (APCVD) system. The reactor consists of a tube with a heated susceptor on which
the wafer rests. An inlet and outlet permits the flow of gasses over the surface of the
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1159
Exhaust
Gas in
Unload
stack
N2
N2
Gas showerhead
Load
stack
Wafers
Susceptor
Heater
Heater
Chain
drive belt
Vent
Cleaning
solution
Vent
APCVD
APCVD with conveyor
Pressure
sensor
Insulated RF input
Wafers
Glass
cylinder
Three-zone heater
Plasma
Wafers
Aluminum
electrodes
Pump
Load
door
Quartz
tube
Gas
inlet
Hot-wall LPCVD
Heated
sample
holder Pump
Gas
inlet
Gas
inlet
Parallel-plate PECVD
FIGURE 41-12 Chemical vapor deposition (CVD) processes include atmospheric pressure CVD (upper left);
APCVD with conveyor (upper right); hot-wall, low-pressure CVD (lower left); cold-wall plasma enhanced CVD.
(S. A. Campbell, The Science and Engineering of Microelectronic, Oxford, U.K.: Oxford University Press, 2001; R. C.
Jaeger, Introduction to Microelectronic Fabrication (Modular Series on Solid State Device Volume 5), New York:
Addison-Wesley, 1990; and M. Madou, Fundamentals of Microfabrication, New York: CRC Press, 1997)
wafer. A common thin film deposited in APCVD reactors is silicon dioxide used for
passivating circuits. The chemical reaction for the deposition of silicon dioxide is:
SiH4 g O2 g h ! SiO2 s 2H2 g
where the parenthetical entities represent gas, heat, and solid, respectively. In this
reaction, silane and molecular oxygen enter the reactor at the inlet, silicon dioxide is
deposited onto the wafer, and molecular hydrogen leaves the reactor at the outlet
(along with any unused silane). Under proper conditions, this reaction takes place on
the surface of the wafer at around 425 C.
APCVD can be performed at temperatures much lower than thermal oxidation,
which has advantages in midstage processing of dielectrics. APCVD processes are also
attractive because of high deposition rates and simple equipment design. To increase
production, wafers can be conveyed through the APCVD reactor on a heated chain
conveyor, fed one wafer at a time by multiwafer cassettes. In addition, APCVD can be
used to deposit phosphorous-doped or phosphosilicate glass (PSG) otherwise known as
p-glass, by adding phosphine to the reaction. P-glass can be used to smooth the wafer
topology and getter wafer impurities, also during midstage processing. Problems with
APCVD include impurities and poor control over film thickness.
Because CVD processes involve chemical reactions, one distinction from other
processes involves the location of those reactions. Gas-phase (homogeneous) reactions
resulting in solid particulates are generally undesirable because the ensuing particulate
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deposition produces thin films with poor morphology, increased contamination, and
inconsistent properties. Chemical reactions on the wafer surface (heterogeneous
reactions) result in the deposition of a solid, thin film with more uniform properties.
In APCVD, homogeneous reactions are reduced by the introduction of diluent gases.
However, greater control over gas-phase reactions can be obtained with the use of low
gas pressures on the order of several hundred millitorr. This process is commonly called
low-pressure CVD (LPCVD).
Most polycrystalline silicon, or polysilicon, is deposited through LPCVD. The
chemical reaction for the deposition of polysilicon is carried out at 600 C on the wafer
surface. Polysilicon is often used for making gate electrodes during component fabrication. While polysilicon can be deposited within an APCVD reactor, the uniformity of
the film thickness is hard to control, which is problematic for gate electrodes. Therefore,
polysilicon is normally deposited in an LPCVD reactor where uniformity is easier to
control. Another benefit of LPCVD is that it consumes much less carrier gas, which
reduces gas expense and handling.
To understand the reason for the improved process control in LPCVD reactors, it
is important to differentiate CVD processes that are reaction-rate limited from those
that are mass-transport limited. In reaction-rate limited processes, the deposition rate
is controlled by the chemical reaction rate at the surface of the wafer. In contrast, masstransport limited processes are controlled by the concentration of gases at the surface of
the wafer. These two limits on process kinetics account for the major differences in
CVD reactor designs.
Most LPCVD processes are reaction-rate limited. Because chemical reaction rates
are heavily temperature dependent, thermal uniformity tends to be a design requirement
for LPCVD reactors. However, at the low gas pressures in LPCVD reactors, there is
more distance between molecules than in APCVD reactors, and consequently, there are
fewer interactions between molecules. Therefore, it is more difficult to transfer energy
between molecules and attain thermal equilibrium within LPCVD reactors. Because
thermal equilibrium is hard to achieve within LPCVD reactors, most LPCVD reactors
keep all surfaces within the reactor at the same temperature to minimize thermal gradients within the reactor. Because the walls of these reactors are heated, they are called hotwall reactors. The ability to maintain thermal stability within hot-wall reactors is the reason for the improved process control of LPCVD reactors.
One disadvantage of hot-wall reactors is that the thin film is deposited along the
walls of the reactor as well as on the wafer surface. Over time, these deposited films can
flake off and contaminate the wafer surface. As a result, hot-wall LPCVD reactors must
be dedicated to the growth of only one material, which reduces their flexibility. In some
cases, cold-wall reactors can be used to reduce deposition on the walls. Cold-wall
reactors have been used successfully to deposit tungsten for component interconnection, which has the advantage of reducing the size of metal contacts. However,
cold-wall reactors do not permit the same level of temperature control and, therefore,
do not permit the same level of deposition uniformity as hot-wall reactors.
In general, LPCVD reactors require higher capital expense due to their vacuum
requirements and permit lower deposition rates than APCVD reactors. However,
because LPCVD reactors typically are not mass-transport limited, wafers may be processed in higher densities within the reactor. Batch sizes in hot-wall LPCVD reactors
may be as high as several hundred wafers, which more than makes up for the loss of
deposition rate. With such large batch sizes, depletion of reacting species can cause variation in deposition rates from the front to the back of the reactor. This can be accommodated by setting up a temperature gradient from the front to the back of the reactor,
resulting in higher chemical reaction rates in the back of the reactor.
In other CVD processes where the deposition rate is mass-transport limited, the
major design requirement of reactors is to permit uniform transport of reactant gasses
to all parts of the wafers. As a result, these reactors have geometries optimized for gas
flow and have excellent gas flow controls. One example of this was shown in the conveyorized APCVD reactor in Figure 41-12. In such reactors, the natural convection of the
reactant gas between the wafer surface and the cold walls of the reactor can cause
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1161
circulation of the gas and make it difficult to control the concentration of the gas at the
wafer surface. Consequently, this can make the deposition uniformity between wafers
hard to control. These problems can be addressed with proper flow design of the reactor
and appropriate parametric design.
Many integrated electronic features require the deposition accuracy of LPCVD.
However, many LPCVD processes require high temperatures that are not compatible
with late stage processing, because high temperatures will cause diffusion of previously
deposited material layers. Plasma-enhanced CVD (PECVD) has been used effectively
to lower the processing temperatures needed to sustain the necessary chemical
reactions. One manifestation of a cold-wall PECVD reactor is shown in Figure 41-12.
In this case, the wafer rests between electrodes through which an AC potential is
applied at radio frequency.
One application of PECVD is in passivating the IC after processing, achieved by
depositing silicon nitride as a durable, inert coating to protect the circuit from moisture
and scratches. A chemical reaction for sustaining silicon nitride passivation is:
3SiH4 g 4NH3 g h ! Si3 N4 s 12H2 g
An LPCVD reactor would drive this process at 900 C, but by substituting dichlorosilane, the temperature can be driven lower (700 to 900 C). PECVD can drive this
reaction at 300 to 400 C. Both hot-wall and cold-wall PECVD reactors have been used
for silicon nitride passivation.
Issues with PECVD include low deposition rates, poor throughput, poorer step
coverage, and more impurities than LPCVD. Deposition uniformity can be a concern
in hot-wall reactors due to gas depletion. Some effort has been made to improve the
throughput of cold-wall reactors by permitting multiple process steps to be performed
in a single vacuum chamber.
EPITAXIAL GROWTH
In some cases, it is desirable to deposit a thin film of single-crystal semiconductor material onto the silicon wafer prior to semiconductor processing. Epitaxy is the growth of a
single crystal, thin film of identical crystallographic orientation as the surface on which
it is grown. Epitaxy is used for the purpose of improving semiconductor properties or
fabricating abrupt transitions between doped layers that would otherwise be hard to
form by diffusion or ion implantation. Epitaxial layers, or epi-layers, are grown under
tighter specifications than bulk single crystals, resulting in fewer crystal defects, higher
purity, more uniform dopant distributions, and sharper transitions between doped layers. In early semiconductor processing, n-type epilayers were grown on top of p-type
substrates for standard buried-collector bipolar processing. Due to the high temperatures involved (leading to the solid-state diffusion of dopants), current mainstream silicon manufacturing uses epitaxial deposition mainly for thick layers (1 to 10 mm) from
which devices may be fabricated.
The mainstream method for silicon epitaxial deposition is vapor-phase epitaxy
(VPE). VPE is an extension of LPCVD. One difference is that the VPE of single crystal
silicon is performed at higher temperatures (1000 C) than the LPCVD of polysilicon.
Because surface reaction rates are much faster at higher temperatures, VPE reactions
tend to be mass-transport limited, and as a result, the reactor is designed to optimize gas
flow to the wafer. Many other CVD techniques are able to produce semiconductor epitaxial growth, including ultra-high vacuum and laser, optical, and X-ray-assisted CVD.
However, VPE is the mainstream epitaxial method used in silicon fabrications. NonCVD methods (liquid phase, molecular beam, ion beam, and clustered ion beam epitaxy) have been found more important for depositing compound semiconductors such
as galium arsonite (GaAs). CVD techniques such as metallorganic CVD are beginning
to show promise for GaAs as well.
INTEGRATED CIRCUIT COMPONENT INTERCONNECTION

Up to this point, most of the discussion has focused on individual IC components. The
components must be interconnected (connected together) with the use of thin-film
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FIGURE 41-13 Schematic of a

two-level metal interconnect
structure typical of metallization
process. (R. C. Jaeger,
Introduction to Microelectronic
Fabrication (Modular Series on
Solid State Device Volume 5),
New York: Addison-Wesley, 1990)
Second-level
metal
Via
Interlevel dielectric
SiO2
SiO2
n+
Contact
First-level
metal
Si Wafer
metal wires between thin-film dielectric layers. The deposition of thin film metals and
dielectrics for component interconnection is called metallization.
As shown in Figure 41-13, the geometry of metallization involves metal wires, or
lines, in between layers of dielectric. In metallization, metal deposition has conventionally been accomplished by PVD processes, whereas dielectric deposition has been
accomplished by either PECVD or sputtering. In order to interconnect the IC components, access must be made between the first level of lines and the semiconductor. These
access points are called contacts. To permit lines to cross over one another, access must
be made between each layer of lines. These access points are called vias (discussed in
more detail later). Holes for contacts and vias are produced by pattern transfer with
photolithography and etching steps.
Modern ICs typically have between one and six metallization layers. During metallization, as each layer of metal and dielectric is deposited and etched on top of
another, the topology of the wafer can become quite severe. If the topology of the wafer
becomes too pronounced, the result can be shorts in metal wires due to poor step coverage during metal deposition. Further, as the feature resolution of photolithography
exposure systems continues to improve, the depth of focus of these systems decreases,
making photolithography on uneven topology difficult. To avoid these problems, interlayer dielectric layers must be planarized (made flat). As mentioned earlier, one
method of reducing topology is to use p-glass as a dielectric interlayer, because it flows
at a relatively low temperature and smooths out peaks and valleys. Another method is
to perform an etch on the dielectric, which will referentially attack the high points on
the surface. For devices with less than (transistor) gate thicknesses involving a large
number of metallization layers, chemical mechanical polishing (CMP) has become the
standard in planarization. CMP is similar to conventional mechanical polishing with a
wet abrasive slurry, except that the slurry contains a chemical etchant as well. This process is discussed in more detail in Chapter 26.
Metals used for interconnection are those that exhibit low electrical resistance
and good adhesion to dielectric insulating layers. Aluminum is a popular metal for
interconnecting IC components. Small amounts of copper may be added to reduce the
potential for electromigration effects in which the applied current to the device can
induce the undesirable mass transport of metal atoms over time. As the device and wire
sizes continue to decrease, electromigration, which can result in short or open circuits, is
becoming a bigger problem. In addition to aluminum alloys, other alloys and pure metals such as tungsten, titanium, and copper are being considered for metallization for
their ability to resist electromigration. Other key characteristics of deposited metal
films include low film reflectivity (to reduce interference with optical alignment during
photolithography) and low residual stress.
To finish component interconnection, a series of connectivity and functional tests
called wafer testing are performed on each separate IC on the wafer, and the wafer is cut
into individual ICs called dies or chips. The purpose of wafer testing is to eliminate any
unnecessary packaging of defective ICs. At this stage, the wafer has an array of ICs that
has been produced on it. Wafer testing is performed by computer-controlled probing
equipment that introduces electrical signals into each IC by contacting each set of bonding pads on the wafer with needle-like probes. The multiprobe procedure involves
indexing each IC under a probe head, which has a probe for each bonding pad. ICs that
fail the test are marked with an ink dot and discarded. After testing, the wafer is diced
into individual dies or chips. Wafer dicing is typically performed by diamond sawing to
give clean edges with minimal damage.
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Integrated Circuit Packaging
1163
INTEGRATED CIRCUIT YIELD AND ECONOMICS

The larger the IC, the greater the chance for a defect to appear and render the IC
inoperative. At first. it might appear more economical to build very simple, and therefore very small, circuits on the grounds that more of them would likely be functional.
However, in the late 1990s, die area was increasing at a rate of about 12% per year, so
by the turn of the century, ICs with more than 10 million transistors had been produced.
While it is true that small circuits are inexpensive, the cost of packaging, testing, and
assembling the completed circuits into an electronic system must be taken into account.
Once the ICs are separated into individual chips, each chip must be handled individually. From that point on, the cost of any processing is not spread over hundreds or thousands. Thus, packaging and testing costs often dominate the other production costs in
the fabrication of ICs.
One way to improve the economics of microelectronic manufacturing is to
increase wafer sizes. The key benefit from processing larger wafers is an increase in the
percentage of usable area. Larger wafers have a smaller proportion of the area being
affected by edge losses and wafer dicing. Since the mid-1980s, wafer diameters have
increased threefold from 100 to 300 mm, which required the development of new equipment throughout the semiconductor manufacturing process. A second strategy for
improving semiconductor economics involved increasing the number of chips per wafer
by decreasing IC dimensions. IC dimensions have decreased more than 50-fold in the
past 30 years. The smallest feature size in 1971 was 10 mm. By 2001, transistors with gate
features as small as 0.18 mm were made. Again, the catalyst for this improvement was an
investment in the process technology, in particular, photolithography.
Perhaps the most effective method of improving IC economics has been the
improvement in die yield. Die yield improvement is much more desirable because
considerable improvements in economics can be had without making large capital
investments. The die yield depends on the wafer yield (the fraction of silicon wafers
that started versus those that finished the process), which involves the processing
yield (the fraction of good die per wafer), the assembly yield (the fraction of die
that are packaged), and the burn-in yield (the fraction of packaged die that survives
wafer testing). The largest contributors to lower yields are generally the wafer and
processing yields. Wafer yields are driven by large-area defects, which might be
the result of poor process control in deposition or etching that would eliminate the
usefulness of the entire wafer. Processing yields are generally driven by point
defects such as particle contamination, although large area defects can also affect
processing yields.
A single, submicron dust particle trapped between the photoresist and reticle in a
photolithographic step can cause a point defect that will result in the malfunction of an
entire IC. As a result, all microelectronic manufacturing is conducted in clean rooms,
where special clothing must be worn to prevent dust particle contamination of wafers
being processed. The air is continuously filtered and recirculated using high-efficiency
particulate-arresting (HEPA) and ultra-HEPA (ULPA) filters to keep the dust level at
a minimum. Clean rooms are specified by their class of cleanliness with respect to federal standard 209D. Class 100,000 indicates that the filtration in the clean room limits
the number of 0.5-mm diameter particles to 100,000/ft3 volume. Wafers are commonly
processed in Class 100 clean rooms.
& 41.8 INTEGRATED CIRCUIT PACKAGING

Several levels of packaging and assembly are necessary to integrate the IC chip with
other electronic devices to make it part of a fully functional commercial or military
product. IC packaging serves to distribute electronic signals and power as well as provide mechanical interfacing to test equipment and printed circuit boards (PCBs). In
addition to this interconnection role, IC packages protect the delicate circuitry from
mechanical stresses and electrostatic discharge during handling and corrosive environments during its operational life. Finally, because of the high density of the integrated
circuits, dissipation of heat generated in the circuits has become more critical.
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CHAPTER 41

Plastic DIP
No cavity between
body and chip
Molded plastic body
FIGURE 41-14 The dual-inline package (DIP) has a lead

frame and package body. The
leads on the chips are connected
to the pins. (D. P. Seraphim, R. C.
Lasky, and C.-Y. Li, Principles of
Electronic Packaging, New York:
McGraw-Hill, 1989)
Lead frame
Leads imbedded
in plastic body
Wire bond from

lead to chip
Pins
Lead
pitch
PACKAGE TYPES
ICs come in a variety of packages made from a variety of materials. Figure 41-14 shows a
cutaway view of the most well-known IC chip package; the dual in-line package (DIP)
refers to the two sets of in-line pins that go into holes in the PCB. The DIP, like all other
IC packages, is made up of a lead frame and a package body. Typically composed of a
copper alloy (sometimes with an aluminum coating), the lead frame provides electrical
interface between the IC and the PCB. The DIP body is made from a low-cost epoxy,
which facilitates mass production. In high-reliability applications (e.g., military), where
hermetic (air-tight) sealing of the package is important, ceramic package bodies are used.
Generally, IC packages are grouped mainly based on the arrangement, shape, and
quantity of leads. Lead pitch refers to the center-to-center distance between leads on an
IC package. In conformance to standard-setting bodies, such as the Electronics Industries
Association (EIA) in the United States and EIA Japan, lead pitches above 20 mils
(0.02 in.) are measured in inches. Below 20 mils, lead pitches are measured in millimeters.
There are two methods by which components are connected to the circuit on the
PCB. The DIP is the leading example of through-hole (TH) technology, also known as
pin-in-hole (PIH) technology, where IC packages and discrete components are inserted
into metal-plated holes in the PCB and soldered from the underside of the PCB. In surface mount (SM) technology, electronic components are placed onto solder paste pads
that have been dispensed onto the surface of the PCB. Figure 41-15 shows the cross
section of solder joints for typical SM- and TH-packaged components on a PCB.
SM packages are more cost effective in electronic assembly, and this SM technology has replaced a lot of the TH technology, but not entirely, because not all electronic
components can be purchased in an SM package. SM packages are designed for automated production and allow for higher circuit board density than TH components. The
manufacturing challenges associated with SM technology include weaker joint strength
and solderabilty issues relating to lower in-process lead temperatures. Also, TH components have only one lead geometry, whereas SM components have many different
designs. The key packaging families for TH technology are dual in-line packages
(DIPs) and pin grid arrays (PGAs).
In SM technology, IC packages cannot be discussed separately from lead geometry. Lead geometries affect the electrical performance, size constraints on the PCB, and
ease of assembly of the IC package. The most basic form of SM lead is the butt lead, or
I-lead (see Figure 41-16). Butt leads are normally formed by clipping the leads on the
TH component. This technique is sometimes used to convert an existing TH component
to an SM component. Consequently, butt-leaded components do not typically save any
space on the PCB. However, they can reduce costs by eliminating the need to perform
TH soldering of the PCB after SM soldering. Butt-lead components tend to result in the
lowest solder joint strengths, and therefore, reliability is an issue.
Gull-wing leads bend down and out, whereas J-leads bend down and in. Gull-wing
leads allow for thinner package sizes and smaller leads, which is important for compact
applications such as laptop computers. In addition, packages with gull-wing leads are
compatible with most reflow soldering processes and have the ability to self-align
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SECTION 41.8
1165
SM
TH
PCB
TH
SIP (single inline package)

Single side
ZIP (zig-zag inline package)
Through-holemount
SM
PCB
Single side
Dual side
DIP (dual inline package)
Full surface
PGA (pin grid array)
SVP (surface vertical-mount package)

SOP (small-outline package)
Dual side
TSOP (thin small-outline package)
Surface mount
SOJ (small-outline J-lead package)
QFP (quad flat package)

QFJ (quad flat J-lead package)
Quadruple side
Full surface
BGA (ball grid array)
LCC (leadless chip carrier)
LCC SOJ
(leaded chip
carrier,
small outline J-lead
package)
FIGURE 41-15 Here is a summary of the various types of packaging used for ICs. (L. T. Manzione, Plastic
Packaging of Microelectronic Devices, New York: Van Nostrand Reinhold, 1990)
during reflow if they are slightly misoriented. Gull-wing leads are compatible with fine
pitch packages, but inspection of solder joints is difficult in its final soldered configuration. Gull-wing leads are also susceptibile to lead damage and deviation from lead
coplanarity. J-leads are sturdier than gull wings and stand up better in handling. The
solder joint of J-leads face out, making inspection easier. J-leads have a higher profile
than gull wings, which can be a disadvantage for compact applications. At the same
time, this higher standoff makes postsolder cleaning easier. J-leads can be used for
packages with between 20 and 84 leads.
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CHAPTER 41
FIGURE 41-16 Basic lead

geometries for surface mounted
packages include butt leads, gullwing leads, J-leads, solder balls,
and plastic quad flat pack.
PCB
Butt leads
Gull wing
PCB
J-leads
J-leads
Solder ball
PCB
Ag-filled die attach
FIGURE 41-17 Ball grid arrays

(BGAs) provide high numbers of
connections for leads using
solder balls arranged across the
entire bottom of the package.
(R. Prasad, Surface Mount
Technology. Principles and
Practice, New York: Chapman &
Hall, 1997, p. 493)
Quadpack with
gull wing leads
Silicon die
Au bond wires
Epoxy
overmold
BT/Glass PCB
62/36/2 Sn/Pb/Ag
Solder balls
Solder balls are increasingly being used to provide SM interconnection through

ball grid arrays (BGAs). Figure 41-17 shows a BGA package. BGAs provide high lead
density because the solder balls are arrayed across the entire bottom surface of the
package. Lead counts on BGAs can go as high as 2400, with most in the 200 to 500 lead
range. Because of their arrayed nature, BGAs do not need as fine of a pitch (40 to 50
mils) as quad flat packages (QFPs), which can help in electronic assembly yields. To
further boost yield, the solder balls on BGAs have excellent self-aligning capability during reflow and require less coplanarity (6 to 8 mils) than other leads. The downside of
BGAs is the difficulty associated with cleaning, inspection, and rework of solder joints
and the lack of compatibility with some reflow methods because joints are out of sight
beneath the package.
PACKAGING PROCESSES
The first step in IC packaging is to attach the die to the package. Die attachment techniques include wire bonding, tape-automated bonding (TAB), and flip-chip technology.
In wire bonding, also known as chip-and-wire attachment, the chip is attached to the
package with an adhesive, and a wire is attached to bonding pads on the chip and on
the package. Gold wire as thin as 25 mm and aluminum wire as thin as 50 mm can be
attached in wire bonding. As shown in Figure 41-18 for gold wire, the ball bond at the
die pad is formed by melting the wire tip and compressing it against the die pad. After
die pad bonding, the wire is then looped out and ultrasonically or thermosonically
welded to the lead frame of the package. In ultrasonic welding, frictional energy, caused
by placing the vibrating wire in contact with the lead frame, causes heating, melting, and
coalescence of the two materials. Thermosonic welding is ultrasonic welding with the
addition of heat.
In TAB attachment, a thin polymer tape carrying the lead circuitry (see Figure 41-19)
is aligned with the die, and the leads are bonded under temperature and pressure to the IC
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SECTION 41.8
FIGURE 41-18 Thermosonic
ball-wedge bonding of a gold
wire. (a) Gold wire in a capillary;
(b) ball formation accomplished
by passing a hydrogen torch over
the end of the gold wire or by
capacitance discharge;
(c) bonding accomplished by
simultaneously applying a
vertical load on the ball while
ultrasonically exciting the wire
(the chip and substrate are
heated to about 150 C); (d) a
wire loop and a wedge bond
ready to be formed; (e) the wire
is broken at the wedge bond;
(f) the geometry of the ballwedge bond that allows highspeed bonding. Because the
wedge can be on an arc from the
ball, the bond head or package
table does not have to rotate to
form the wedge bond.
(Semiconductor International
magazine, May, Des Plaines, IL:
Cahners Publishing Co., 1982)
1167
Capillary
H2 torch
Gold wire
D
(a)
2.5-3D
(b)
Chip
Substrate
(c)
Substrate
(d)
Wedge bond-on arc

about first bond
Wire
tail end
Substrate
(e)
(f)
chip. In flip-chip attachment, the chip is turned over so that the bonding pads on the chip
and on the package face each other. Flip-chip technology is more common for direct chip
attachment to the PCB but is becoming more important for chip-scale packages, as
explained later. As shown in Figure 41-20, flip-chips are normally attached to the package
with a solder bump.
After die attachment, the package is sealed. Plastic packages are either premolded
or postmolded. Premolded packages are sealed adhesively with a lid (Figure 41-21).
Postmolded packages are sealed via a transfer molding or injection molding process
(Figure 41-21). Prior to molding, the die is adhered and wire bonded to the lead frame,
which is automatically inserted into the mold. The postmolding process is relatively harsh
on the die and wire bonds and can cause major yield and reliability problems. To keep out
environmental contaminates, ceramic packages are hermetically sealed by glass using
either eutectic AuSi or silver-loaded glass adhesive technologies.
Once the package is sealed, leads are typically formed and may require a solder
dip. BGA packages differ from the other packages in that the BGA is interconnected
through the use of laminated substrates (plastic or ceramic) similar to PCB processing
instead of through leadframes. In BGAs, the outermost layer of interconnection is covered with a solder mask, and openings in the solder mask allow for solder ball attachment during solder dipping.
A more advanced option for interconnecting ICs with PCBs is called direct chip
attachment (DCA), also known as chip-on-board or direct die mounting. As suggested,
DCA directly attaches the chip to the board using any of three die-attachment technologies mentioned previously. On paper, flip-chip technology has the greatest potential
for DCA. However, one challenge associated with flip-chip technology is the coefficient
of thermal expansion (CTE) mismatch between the chip and the PCB substrate, particularly as chip sizes increase and solder joint sizes decrease. As a result, the development
of underfill encapsulants has become increasingly important for the reinforcement of
the mechanical and thermal properties of flip-chip solder joints.
Disadvantages of DCA technologies include shipping and handling of the bare
chip and the need for electronic assembly manufacturers to purchase die-attachment
equipment. As a compromise, chip scale packaging (CSP) has been developed to help
downstream processes take advantage of DCA technology. CSP is defined as any
packaging that adds no more than 20% of additional board area to the chip. The micro
BGA (MBGA) package shown in Figure 41-22 is one example of CSP.
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CHAPTER 41

Sprocket
drive holes
Inner leads
bonded to IC
Outer leads
IC
Window in tape to facilitate

excising and expose outer
leads beyond polymer support
ring for outer lead bonding
Area
of polymer
support ring
after excising
by custom die
Heated bonding tool

Leads contact
bond pads
Gas
Chip
Die matrix alignment device
(a)
Wax holds chip

in location
Tool alignment
Wax melts releasing chip

(b)
FIGURE 41-19 Tapeautomated bonding (TAB) uses a

polymer type to carry the leads to
the chip for bonding. (R. C.
Jaeger, Introduction to
Microelectronic Fabrication
(Modular Series on Solid State
Device Volume 5), New York:
Addison-Wesley, 1990)
Bonded chip
Chip motion
Chip in matrix
(c)
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SECTION 41.8
Chip bonding pad
FIGURE 41-20 Flip-chips have

the chip turned over so that the
bonding pads on the chip and
the package face each other.
(C. A. Harper, Electronic
Packaging and Interconnection
Handbook, New York:
McGraw-Hill, 2000)
Solder
mask
or dam
1169
IC
Three-layer under
bump metallization
Ni/Cu/Au
Solder bump
Solder mask or dam

or die passivation
Integrated circuit chip
Filled
epoxy
underfill
Substrate (organic or ceramic)
FIGURE 41-21 Premolded packages (on left) are sealed adhesively with a lid while postmolded packages
are sealed via atransfer molding or injecting molding process. (L. T. Manzione, Plastic Packaging of
Microelectronic Devices, New York: Van Nostrand Reinhold, 1990)
Another alternative to single-chip carriers is multichip carriers or multichip modules (MCMs). MCMs are chip carriers that package more than one chip through direct
chip attachment to fine-line, thin-film conductors within a ceramic carrier. MCMs are
an extension of hybrid circuits that use refractory substrates and thick- and thin-film
metallization processes for interconnection. The MCM is essentially a mini-PCB
Handling
ring
(optional)
Aluminum pad
Chip
Elastomer
FIGURE 41-22 The Tessera

micro BGA package is an
example of chip scale packaging.
(R. Prasad, Surface Mount
Hall, 1997, p. 493)
Next-level
board
Gold wire
Silicon
encapsulant
Flex circuit
Gold-plated
nickel bumps
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CHAPTER 41
with DCA interconnection between the chips and the board. Usually, the die is
mounted in the MCM with flip-chip technology. The major advantage of MCMs is
the reduction in electronic, single-path distance between ICs. The MCM replaces
the typical die-wirebond-pin-board-pin-wirebond-die path with a much shorter diebump-wire-bump-die path.
Selection of the final chip package for an IC device depends on several factors,
including size, weight, cost, number of leads, power handling, signal delay, electrical
noise, and cooling requirements, among others.
& 41.9 PRINTED CIRCUIT BOARDS

The printed circuit board (PCB), or printed wiring board, connects the IC with other
components to produce a functional circuit. Specifically, a PCB is a laminated set of
dielectric layers or laminates of bulk sheet materials that have metallic circuits that are
used to interconnect the various packaged components. As shown in Figure 41-23, each
PCB laminate comprises a base, tracks, and pads. The base material must be electrically
insulating to provide support to all components making up the circuit. Pads on the laminate are connected by conductive tracks or traces (usually copper) that have been
deposited onto the surface of the base. Screen printing was the first technology used to
make circuits, hence the term printed circuits. Today, metal for traces and pads is deposited by electroless plating and electroplating. Surface mount (SM) components are connected to the PCB at pads (lands) or, in the case of through-hole (TH) technology, at
insertion holes.
Typical base materials used may be epoxy-impregnated fiberglass, polyimide, or
ceramic. Criteria used for substrate material selection are shown in Table 41-5. Epoxyimpregnated fiberglass is the cheapest substrate for interconnecting leaded packages.
Fiberglass is used to increase the mechanical stiffness of the device for handling, while
epoxy resin imparts better ductility. Prior to impregnation, the uncured epoxy resin is
referred to as A-stage. The fiberglass is impregnated on a continuous line where Astage resin infiltrates the fiberglass mat in a dip basin, and the soaked fabric passes
through a set of rollers to control thickness and an oven where the resin is partially
cured (Figure 41-24). The resulting glass-resin sheet is called B-stage or prepreg. Multiple prepregs are then pressed together between electroformed copper foil under precise
heat and pressure conditions to form a copper-clad laminate. The fully cured glassepoxy core is called C-stage material.
Many different types of epoxy-impregnated fiberglass exist, as shown in Table 41-6.
FR-4 (flame retardant) and G-10 are the most popular PCB substrates in use today.
Polyimide (without reinforcing fiberglass) is also now widely used in consumer products.
PCBs using polyimide substrates are known as flexible printed circuits, or simply flex
circuits, emphasizing the lack of rigidity. Flex circuits offer the advantages of reduced
size and weight as well as the ability to route printed circuits around corners or other nonplanar geometry. Polyester is also used as a flex circuit substrate, although polyimide is
the most popular due to its high temperature stability.
Tracks
Pads
Insulating substrate (base)
FIGURE 41-23 Double-sided

PCB laminate has a base, tracks,
and pads.
Insertion hole
Via hole
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SECTION 41.9
TABLE 41-5
1171
Printed Circuit Boards
Substrate Selection Criteria

Material Properties
Design
Parameters
Transition
Temperature
Coefficient
of Thermal
Expansion
Thermal
Conductivity
Tensile
Modulus
Temperature
and Power
Cycling
Flexural
Modulus
Dirlectric
Constant
Volume
Resistivity
Surface
Resistivity
Moisture
Absorption
Circuit
Density
Circuit Speed
Vibration
Mechanical
Shock
Temperature
and Humidity
Power
Density
Chip Carrier
Size
X
X
X
Impregnation
(treater tower)
Heat
stage 2
Heat
stage 3
Heat
stage 4
Heat
stage 1
Fiberglass cloth
Prepreg
Resin
TABLE 41-6
Cut
FIGURE 41-24 The PCB is

made up of laminates of epoxyimpregnated fiberglass
manufactured on a machine like
this. (D. P. Seraphim, R. C. Lasky,
and C.-Y. Li, Principles of
McGraw-Hill, 1989)
Laminate Materials Used in Printed Circuit Boards
Common
Designation
Resin
System
Base
Material
Description
XXXP
Phenolic
Paper
Punchable at room temperature.
XXXPC
Phenolic
Paper
Punchable at or above room temperature. XXXP and XXXPC are widely used in
high volume single-sided consumer products.
G-10
Epoxy
Glass fibers
General purpose material system.
G-11
Epoxy
Glass fibers
Same as G-10, but can be used to higher temperatures.
FR-2
Phenolic
Paper
Same as XXXPC, but has a flame retardant (FR) system that renders it selfextinguishing.
FR-3
Epoxy
Paper
Punchable at room temperature and has flame retardant.
FR-4
Epoxy
Glass fibers
Same as G-10, but has a flame retardant.
FR-5
Epoxy
Glass fibers
Same as FR-4, but has better strength and electrical properties at higher
temperatures.
FR-6
Polyester
Glass fibers
Designed for low capacitance or high impact resistance; has flame retardant.
Polyimide
Polyimide
Glass fibers
Better strength and demonstrated stability to a higher temperature than FR-4.
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CHAPTER 41

Component
Hole through board
Component lead
Base material
Land
Solder
(a)
Hole through
board
Component
Component leads
Base
material
Land
Track
Metallized layers
Solder
Plated throughholes (vias)
(b)
Component on underside
Component
Buried via
Through via
Metallized layers
Track
Solder
Blind via
Land
Metallized layer
(c)
FIGURE 41-25 PCBs can be single-sided, double-sided, or multilayer. (M. Judd and K. Brindley,
Soldering in Electronics Assembly, Boston: Reed International Books, 1992)
Ceramic substrates (typically alumina) are used primarily to minimize thermal

stresses on joints in military applications that use leadless ceramic packages. In addition, ceramic substrates are used for hybrid circuits involving both semiconductor
and thick-film components. Thick film refers to components that are screen printed
as opposed to deposited by thin-film technology (i.e., evaporation, sputtering, or
electroplating).
PCBs can be single-sided, double-sided, or multilayer. Single-sided PCBs simply
have metallic circuits on one side of the laminate. Through-hole (TH), single-sided
PCBs have insertion holes that extend through the board to the other side where TH
components may be inserted into the board (Figure 41-25a). Surface mount (SM) components are simply mounted onto the pads on the same side as the circuit and do not
require through-holes. Double-sided PCBs are used in cases where circuits must
jump, or cross over, one another. In this case, via holes (or simply vias) are needed to
route the circuits over one another (Figure 41-25b). Vias are essentially metal-filled
holes through the laminate material that connect a circuit on one side to the other. The
metal inside of the via is electroplated. Vias that are also used as insertion holes are
called plated through-holes (PTHs). As the number of packaged components on the
board increases, the complexity of the circuits increases, giving rise to the need for multilayer PCBs in which multiple single- and double-sided boards are laminated together
using prepreg. Vias that pass from an outermost track on one side of the board to the
outermost track on the other side are called through vias (Figure 41-25c).Vias within a
laminate core on the inside of a multilayer PCB are called buried vias. Vias that come
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SECTION 41.9
Printed Circuit Boards
1173
Subtractive etch
Etched
pattern
Photoresist
Additive
Copper plated pattern
Photoresist
Subtractive (panel)
FIGURE 41-26 PCBs can have

inner layer circuits made by
either a subtractive or an additive
process. (D. P. Seraphim, R. C.
Lasky, and C.-Y. Li, Principles of
McGraw-Hill, 1989)
Copper-clad
prepreg
Drill, seed,
plate
Surface prep,
resist apply,
expose, develop.
Etch,
strip resist
Additive (pattern)
Copper-clad
prepreg
Drill, etch
Copper,
surface prep,
resist apply
Expose,
develop,
seed
Copper
plate strip
resist
out on only one side of a multilayer PCB are called blind or partially buried vias. Multilayer PCBs can have as many as 20 layers, although four to eight are more common.
Production of a multilayer PCB from a C-stage laminate begins with a process
known as inner-layer circuitization. Inner-layer circuitization may be either subtractive
or additive. Subtractive circuitization (Figure 41-26) for glass-epoxy PCBs begins with a
double-sided, copper-clad, C-stage laminate known as a panel, which has been sheared
to size. A film of dry photoresist is applied by hot roller to the copper surface. Next, the
circuit pattern (traces and pads) is transferred to the photoresist by exposure through a
reticle and chemical development of the photoresist in a photolithographic process similar to that used in semiconductor processing. The copper is then selectively etched
through the resulting etch mask, and the resist is subsequently stripped from the laminate. Afterward, registration holes are drilled relative to locator marks, called fiducials,
produced in the copper layer during the lithography and etching processes.
In additive circuitization (Figure 41-26), copper is selectively deposited instead of
etched away. The process begins with a bare glass-epoxy laminate cut to size with registration holes. If necessary, via holes may be drilled. An etch mask is exposed and developed, exposing the underlying dielectric including all via holes. The exposed dielectric
surfaces are buttercoated, or seeded, to permit electroless deposition by adsorbing a
catalyst (usually palladium) from solution onto the surface of the dielectric. A thin layer
of electroless copper is deposited on the seeded dielectric, followed by electroplating of
thicker copper layers. Afterward, the resist is stripped. The additive process has the
advantage of providing higher resolution for circuitry with finer lines and higher density
but tends to be less economical.
The final multilayer board is produced by lamination of inner layers, drilling and
preparation of via holes, and circuitization of outer layers. In lamination, as shown in
Figure 41-27, a stack of inner layers is bonded together between B-stage prepreg of the
appropriate shape and size under time, temperature, and pressure. Usually the inner
layers are stacked up between copper layers on the top and bottom of the stack. Prior to
lamination, the copper surfaces of the inner layers are oxidized to improve adhesion
between layers. Alignment between layers is critical during lamination and is controlled
with pins and registration holes. After lamination, excess resin that oozed out during
bonding is sheared off. Next, via holes are drilled, deburred, and plated. After drilling,
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CHAPTER 41

Caul plates
Copper foil
}
Inner layer
FIGURE 41-27 PCBs are often

multilayers of laminations as
shown here with a four-layer foil
construction. (M. L. Minges,
Electronic Materials Handbook,
Volume 1. Packaging, Materials
Park, OH: ASM International,
1989)
B-stage material
Knockout pins
some epoxy smear may exist on the copper surface within the via, which will prevent
electrical connection or weaken the mechanical integrity of the via. Therefore, an acidic
solution is used to remove excess epoxy and actually to slightly etch back epoxy within
the hole so that the copper layers protrude slightly, which improves the connection
between copper layers within the via. Subsequently, the epoxy surface within the via is
seeded, and a thin layer of electroless copper is deposited. Outer-layer circuitization
involves the same method of dry resist patterning to produce a lithographic mask. One
difference between inner- and outer-layer circuitization is that copper is electrolytically
deposited onto exposed copper after masking to ensure good electrical contact between
the inner and outer copper layers. To finish the PCB, the copper layer is etched, a photosensitive solder mask/encapsulant is applied, and the remaining exposed pads are
pre-tinned with solder.
The manufacturing process for producing flex circuits is similar to the process just
described. Flex circuits are typically not as complicated as glassepoxy PCBs and so
have fewer layers. The typical process makes use of a two-sided, copper-clad, polyimide
film usually bonded with an epoxy resin. Encapsulation is performed with the use of
flexible cover layers, which are either photosensitive or precut and bonded. After
encapsulation, the final shape of the flex circuit is cut to size either by shearing (high
volume) or by lasers and water jets (prototyping).
With the advent of CSP and MCM packaging technologies, the requirements for
track and pad densities have increased. The practical limit of mechanical drilling is a
diameter of about 200 mm. Microvias are via holes made by photo-imaging, laser ablation, and plasma etching that extend well below 200 mm. Microvias as small as 25 mm
can be made that increase the density of pads and tracks eightfold over conventional
mechanical drilling technologies. Advantages of such small vias include the elimination
of bonding pads for direct trace-to-trace connections. Microvias can be used to produce
built-up multilayers (Figure 41-28). Built-up multilayers are made by deposition and
processing of one dielectric layer at a time, similar to IC interconnection. Connections
between dielectric layers are made by drilling and electroplating into microvias. Circuit
routing can be made extremely efficient, which results in optimally short signal lengths
for high-performance applications.
Thin
buildup
layers
FIGURE 41-28 Microvias can

be used to produce built-up
microlayers. (C. A. Harper,
Electronic Packaging and
Interconnection Handbook, New
York: McGraw-Hill, 2000)
Small
photo-via
(127 mm)
Plated
Cu
conductor
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SECTION 41.10
Electronic Assembly
1175
& 41.10 ELECTRONIC ASSEMBLY

The term electronic assembly is generally reserved for the third level of electronics manufacturing involving the soldering of packaged ICs and other discrete components onto
PCBs using through-hole (TH) and/or surface mount (SM). As explained in the IC
packaging section, TH technology refers to the insertion of packaged leads into plated
through-holes (PTH) in the PCB and soldering of the terminals from the backside. SM
technology involves temporary attachment of components to the surface of the PCB via
a flux-containing solder paste, which is reflowed within an oven. SM components are
much smaller and have much different leads. Passive (non-IC) SM components have
terminations rather than leads that permit better shock- and vibration-resistance as
well as reduced inductance and capacitance losses.
The sequence of operations for SM and TH assembly is shown in Figure 41-29.
Insertion can be performed either manually or with automatic insertion machines. After
Start
Blank
card
Form all
component leads
Mount passive
components
Trim
leads (guillotine)
Mount semiconductor devices
Mount
special devices
Vapour
clean (optional)
Start
Screen print
solder paste
Apply adhesive
side 2
Place SM
components
Place SM
components
Clean
board
Cure solder
paste
Cure adhesive
Invert board
Wave
solder
Inspect
and test
Reflow solder
Invert board
Clean
Wave solder
Insert throughhole components
Clean
Test/repair
Doublesided
assembly
No
Wave solder
Clean
Test/repair
Yes
FIGURE 41-29 The assembly process steps for making a TH PCB (above). The steps for SM assembly
are given below along with the steps for mixed technologiesboth TH and SM. (M. R. Haskard, Electronic
Circuit Cards and Surface Mount Technology: A Guide to Their Design, Assembly, and Application, New
York: Prentice Hall, 1992)
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CHAPTER 41
insertion, leads are generally clinched and trimmed if necessary to avoid bridging
between joints during soldering, which can cause electrical shorting of the circuit. Generally, soldering of TH components is performed automatically through a process known as
wave soldering. Wave soldering involves the conveyance of a preheated and prefluxed
PCB over a standing wave of solder created by pumping action. The combination of capillary action and pumping action permits flow of the solder from the underside of the board
into the joint. Cleanliness of the PCB is critical for wetting of the lead and PTH. A highpressure air jet is used to blow off excess solder from the underside of the board to prevent solder ridging. Postsolder cleaning of the board includes degreasing and defluxing.
One key consideration for TH solder joints is joint strength. The trade-off is the
clearance between the insertion lead and insertion hole. As the clearance decreases,
joint strength increases. However, with smaller clearances it is more difficult to insert
pins in holes. Clearances on the order of 0.25 mm are typical. Another factor affecting
joint strength involves the clinching of leads. Clinched lead joints are much stronger
than unclenched joints. Because the mechanical strength of TH joints is generally superior to SM joints, large, heavy components are generally attached with TH technology.
SM assembly involves application of solder paste to the lands on the surface of the
PCB, placement of SM components on top of this paste, and reflow of the solder paste
within an oven. Solder paste consists of small spherical particles of solder less than a
tenth of a millimeter in diameter together with flux and solvents used to dissolve the
flux (imparting tackiness) and thicken the paste. At the time of application, the paste
has the consistency of peanut butter and is applied by screening, stenciling, or dispensing. In screening and stenciling, a solder paste printer is used to apply solder paste
through a mask (screen or stencil) by running a squeegee over the surface of the mask.
The mask is typically held off of the surface by a distance on the order of 0.5 mm, known
as the snap-off distance (see Figure 41-30). As the squeegee passes over the mask surface, the mask is pressed against the PCB, allowing contact between the paste and the
lands on the board. After the squeegee has passed, the mask snaps back from the surface, leaving an island of solder paste on the PCB lands. Stencils are typically metal
sheets or wire mesh that has been chemically etched using a lithographic process.
Screens are typically formed by application, exposure, and development of a photosensitive emulsion on top of a wire mesh. Advantages of metal sheet stencils include
longevity and multilevel (pads of varying thicknesses) printing, and the screens are
cheaper to make. To decrease tooling costs during product development, pastes can
also be dispensed without a mask through a syringe needle. Dispensing generally
requires pastes with lower viscosity, which can lead to other problems including solder
paste slump (spreading out of the solder pastes after application).
Squeegee
travel
Squeegee
Solder paste
Mesh
+
emulsion
Gap
FIGURE 41-30 Schematic for

applying solder paste on a
substrate by squeegee in a screen
printing process in SM
technology. (R. Prasad, Surface
Mount Technology. Principles
and Practice, New York: Chapman
& Hall, 1997, p. 493)
Open mesh
.020" Typical
Substrate
holder
Substrate
Paste deposit
Snap-off
distance
06/18/2011
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SECTION 41.10
Electronic Assembly
1177
Once the solder paste is positioned on the board, a component placement

machine, also known as a pick-and-place machine, is used to place the components
onto the solder paste pads. The flux in the solder paste is tacky and holds positioned
components in place until oven soldering. Components are fed to a robotic manipulator
that has a vacuum chuck or a mechanical chuck, or both. Component feeders deliver
components to the manipulator. Several types of feeders exist, including tape (or reel),
bulk, tube (or stick), and waffle pack. The feeder system must be carefully selected
based on the desired quantity per feeder, availability, part identification, component
cost, inventory turns, and potential for damage during shipping and handling. Tape
feeders are widely utilized and are most desirable for high-volume placement. Tube
feeders are useful for smaller-volume assemblers, even though costs per component are
higher. Waffle packs are flat-machined plates with inset pockets to hold various chips.
In general, waffle packs increase the cost of assembly. However, some IC packages, like
the bumperless, fine-pitch QFPs, require a high level of protection during handling to
minimize lead damage, so this component requires the tape-feeding mechanism. Bulk
feeding of IC components, through the use of a vibratory bowl, may be useful for prototyping environments.
The economics of SM technology are driven by component placement equipment,
which determines the throughput of the SM line and is the source (at least partially) of
most defects requiring rework. Further, placement equipment strongly influences startup
costs because it may involve as much as 50% of the capital equipment cost in setting up a
line. Key criteria in the selection of placement equipment include placement accuracy,
placement rate, maximum PCB size, types and sizes of components, and maximum number of feeders, among others. In general, placement equipment has been classified as four
discrete types: (1) high throughput, (2) high flexibility, (3) high flexibility and high throughput, and (4) low cost and low throughput with high flexibility. High-throughput placement
machines are called chip shooters. Chip shooters are typically dedicated to the placement
of passive (resistors, capacitors, etc.) and small active (IC) components and can place components at rates up to 60,000 components per hour with linear repeatability around 0.05 to
0.1 mm and rotational accuracy of 0.2 to 0.5 degree over a 350- 450-mm area.
After components are placed, the PCB is placed in a reflow oven, where the solder
paste melts, causing a fluxing action, which permits the melted solder to wet the leads
and the PCB lands. To achieve this, the PCB must be exposed to an appropriate thermal
profile, or timetemperature curve, as it passes through the oven. Figure 41-31 shows a
common thermal profile for SM reflow. At a minimum, the thermal profile must include
at least four zones. The first zone, called preheating, is used to drive off any nonflux
volatiles within the paste. The second zone, the soak zone, is used to bring the entire
assembly up to just below the reflow temperature of the paste. The third (reflow) zone
90 sec. max
30 sec. min
220 10C
Temperature (C)
C41
FIGURE 41-31 The typical

thermal profile used for SM
reflow. (R. Prasad, Surface Mount
Hall, 1997, p. 493)
183C
150C
Max slope
of 2C/sec
90-150 sec.
Preheat
Soak
Time (s)
Reflow
Cooling
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CHAPTER 41
quickly raises the temperature of the solder paste above the reflow temperature allowing for fluxing and wetting of solder joints. The fourth zone cools the assembly permitting solidification. Reflow soldering is generally done in infrared (IR) reflow ovens, and
heating involves both IR radiation as well as gas-forced convection. The minimum
number of heating zones for a reflow oven must be three (the fourth is a cooling zone)
but can contain as many as 20 to provide better control over the thermal profile.
An alternative to IR reflow soldering is vapor-phase soldering, or condensation
soldering, involving the condensation of a hot perfluorocarbon vapor onto the assembly
surface, releasing the latent heat of vaporization into the solder joints and substrates.
By and large, this process has been replaced by IR reflow soldering due to improved
process reliability and control. Other alternatives to IR reflow soldering include laser,
hot bar, and hot belt reflow soldering.
For a variety of reasons, SM technology and through-hole insertion technology
are mixed on the same PCB. Some components are not available in SM packages. Some
components are large and require the added strength provided by TH solder joints.
Some components require more heat dissipations than SM can accommodate. Thus,
both methods will continue to be used in the future.
& KEY WORDS

additive circuitization
assembly yield
A-stage
backpanel PCB
ball grid array (BGA)
barrier potential
blind vias
board
boat
boule
bridging
B-stage
built-in multilayers
buried via
burn-in yield
butt lead
buttercoated
card-on-board
charge
chemical metal polishing
(CMP)
chemical vapor deposition
(CVD)
chip-and-wire attachment
chip carriers
chip-on-board
chip scale packaging (CSP)
chip shooter
chip
clean rooms
clinching
condensation soldering
contact printing
contacts
C-stage
Czochralski method
depletion region
diamond sawing
dies
die yield
diffusion
direct chip attachment
(DCA)
direct die mounting
direct-write technique
donor
dopants
doping
drive-in
dry etching
dry oxidation
dual in-line packging (DIP)
electromigration
electronic assembly
electron holes
epitaxy
etch bias
etchant
etching
evaporation
feeders
fiducials
flats
flex circuits
flip-chip
gettering
gull-wing leads
inner-layer circuitization
integrated circuit (IC)
ion milling
isotropic
J-leads
lattice
lines
linewidths
lithography
mass-transport limited
metallization
microvias
motherboard
multichip module (MCM)
n-type semiconductors
outer-layer circuitization
panel
partially buried vias
p-glass
p-n junction
p-type semiconductors
photolithography
photomask
photoresists
physical vapor deposition
(PVD)
pick-and-place
pin grid array (PGA)
pin-in-hole (PIH)
plasma etching
plated through-hole (PTH)
polishing
polysilicon
predisposition
prepreg
printed circuit board
(PCB)
printed wirign assembly
(PWA)
processing yield
projection printing
proximity printing
quad flat package (QFP)
rapid thermal annealing
(RTA)
rapid thermal processing
reaction-rate limited
reactive ion etching (RIE)
reflow oven
resist
resist masks
resolution
reticles
seed crystal
selectivity
semiconductor
sensitivity
slump
snap-off distance
solder balls
solder paste
spin coating
sputter etching
sputtering
step coverage
stepper
stripping
subtractive circuitization
surface mount (SM)
tape-automated bonding
(TAB)
thermal profile
thick film
thin film
through-hole (TH)
through-mask technique
through vias
timetemperature curve
vapor-phase epitaxy (VPE)
vapor-phase soldering
via holes (vias)
wafer testing
wafer yield
wafers
wave soldering
wet etching
wet oxidation
wire bonding
C41
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Review Questions
1179
& REVIEW QUESTIONS

1. What is the goal of the field of electronics?
2. What are the major advantages of integrated circuits over
electronic assemblies? What is the advantage of electronic
assemblies?
3. How many levels of electronic manufacturing exist? Name
each level.
4. What is a semiconductor?
5. Name three common semiconductor materials.
6. What is meant by the term doping?
7. What is the difference between n-type and p-type
semiconductors?
8. What are electron holes?
9. Give three reasons why silicon is the most popular semiconductor used today.
10. What is a p-n junction? What can it be used for?
11. What is the barrier potential of a p-n junction? Why does it
exist?
12. List the sequence of steps necessary to produce a bipolar
diode.
13. What is meant by the term ULSI? How is it different from
VLSI?
14. In general, what technological breakthroughs were necessary to advance to each successive level of integration?
15. What is a silicon boule?
16. Why is it advantageous to add impurities during the formation of the single crystal?
17. Why are notches or flats cut or ground along the periphery of
the single-crystal ingot?
18. Why are single-crystal ingots with diameters 300 mm and
larger marked with a notch instead of a flat?
19. What are some geometric concerns involved with wafer
production?
20. What does gettering mean in relation to wafer production?
21. Name three methods for doping a silicon wafer.
22. What are some advantages of ion implantation over thermal
diffusion?
23. Why must ion-implanted substrates be annealed?
24. Why are rapid thermal processing technologies generally
advantageous?
25. What are two ways in which silicon dioxide is commonly used
in microelectronic manufacturing?
26. Give two reasons wet oxidation is better suited to making
thicker oxides (e.g., diffusion masks) than dry oxidation.
27. How is the lateral geometry of the IC and its components
patterned into microelectronic materials?
28. What is the most complicated, expensive, and critical step in
microelectronics manufacturing?
29. In addition to photolithography, name three other lithographic methods that may be used for pattern transfer.
30. List the photolithographic steps necessary to produce a resist
mask on a silicon substrate.
31. Of the two major classifications of photoresists, which type
cross-links under exposure to electromagnetic energy of the
proper wavelength, resulting in longer polymer chains?
32. List four requirements of a photoresist.
33. What were the two most important wavelengths for photolithography provided by the mercury arc lamp?
34. List the three types of exposure methods used in photolithography. Give an advantage of each.
35. What is the difference between wet and dry etching?

36. What is undercutting?
37. What are some possible defects that can result from underetching? From overetching?
38. List and describe two properties of etchants.
39. Compare the three dry etch processes, including a description of their etch mechanisms and advantages.
40. What are thin films? Why are they important to microelectronic manufacturing?
41. List two different types of physical vapor deposition, including the physical mechanisms and advantages of each.
42. List three different forms of chemical vapor deposition, and
indicate in what application each might be used.
43. How are undesirable gas-phase reactions controlled within
APCVD and LPCVD reactors?
44. What is the key difference in the reactor designs of APCVD
and LPCVD processes?
45. What are the two types of LPCVD reactor designs? List the
advantages and disadvantages of each.
46. What is the advantage of using PECVD processes?
47. What is epitaxy, and why is it important for microelectronic
manufacturing?
48. In metallization, what is the difference between a contact
and a via?
49. What is planarization, and why is it needed?
50. Give three methods for planarizing interconnect layers.
51. What is electromigration, and why is it a concern in IC
processing?
52. What is the purpose of wafer testing?
53. What is meant by the term chip?
54. What drives the increase in component density and die area
within microelectronic manufacturing?
55. Why are clean rooms so important to microelectronic
processing?
56. What two subcomponents make up an IC package?
57. What are the advantages of surface mount technology and
through-hole (or pin-in-hole) technology for attachment of
IC packages and discrete electrical components to boards?
58. Name the two key classes of TH packages.
59. Name the four different types of SM lead geometries, and
discuss the advantages of each.
60. List the key steps involved in conventional IC packaging.
61. List three techniques for attaching and electrically connecting dies to IC packages.
62. What is meant by direct chip attachment, and how does it differ from more conventional IC packaging? What are some
disadvantages to direct chip attachment?
63. What are chip-scale packages, and how do they differ from
direct chip attachment methods?
64. What are multichip modules, and why are they advantageous
for IC packaging?
65. What is a printed circuit board (PCB)? What three elements
does a PCB consist of?
66. Name three alternative materials used as dielectrics within
PCBs, and give the major reason each is used.
67. What is the difference between plated through-holes and via
holes?
68. What is the difference among blind, buried, and through
vias?
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CHAPTER 41
69. List the four major process steps for producing a multilayer
PCB.
70. List the two methods for inner layer circuitization, and discuss the physical process and advantages of each.
71. What are built-up mulitlayers and microvias? How are they
different from laminates and vias?
72. List the four major steps for assembling a TH printed wiring
assembly (only TH technology).
73. Why are leads trimmed and clinched after through-hole
insertion?
74. List the four major steps for assembling an SM printed wiring
assembly (only SM technology).
75. Name four methods for feeding components to robotic
manipulators in pick-and-place robots. Discuss the application of each.
76. What step in the SM assembly process most strongly affects
startup and operations costs for an SM assembly line? Why?
77. What four zones are necessary within an SM solder reflow
thermal profile?

CH 41

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C41

41.6 FABRICATING INTEGRATED

Integrated Circuit Yield and

& 41.1 INTRODUCTION

& 41.2 HOW ELECTRONIC PRODUCTS ARE MADE

& 41.3 SEMICONDUCTORS

Microelectronic Manufacturing and Electronic Assembly

FIGURE 41-2 (a) Schematic of

& 41.4 HOW INTEGRATED CIRCUITS ARE MADE

How Integrated Circuits Are Made

Microelectronic Manufacturing and Electronic Assembly

1. Material preparation (P+ wafer)

2. Epitaxial growth (P)

3. Mask oxide and

4. Etch and diffusion

5. Mask removal and

10. Ion implantation

11. Oxide deposition

17. Final overcoat

Classification in the Development of IC Architectures

Greater than 1,000,000

464 Mb memory ICs, latest microprocessors, advanced workstations and microcomputers

How the Silicon Wafer Is Made

FIGURE 41-5 In the

(b) Seed dipped

(c) Partially grown

& 41.5 HOW THE SILICON WAFER IS MADE

Microelectronic Manufacturing and Electronic Assembly

Primary flat denotes (011)

FIGURE 41-6 Flats are ground

& 41.6 FABRICATING INTEGRATED CIRCUITS ON SILICON WAFERS

Fabricating Integrated Circuits on Silicon Wafers

Microelectronic Manufacturing and Electronic Assembly

Though similar in some ways, atomic diffusion in oxidation is different than in

Fabricating Integrated Circuits on Silicon Wafers

(1) Starting wafer with layer

(2) Coat with photoresist

(3) Bake the resist to set its

(6) Hard bake

(4) Expose resist by shining

(8) Strip off the resist

Microelectronic Manufacturing and Electronic Assembly

FIGURE 41-8 Photoresist

Fabricating Integrated Circuits on Silicon Wafers

Microelectronic Manufacturing and Electronic Assembly

FIGURE 41-10 Deviations

The objective in etching is to produce the proper lateral dimensions of the IC in

Types of Dry Etching

Reactive Ion Etching

Relative excitation energy

Relative chance of radiation damage

Greater than 100 mtorr

Less than 100 mtorr

Masking layer during oxidation

Metal and Dielectric Layers

Conduction path for component

Dielectric layer for component

& 41.7 THIN-FILM DEPOSITION

PHYSICAL VAPOR DEPOSITION

Microelectronic Manufacturing and Electronic Assembly

(+) Ions (from process gas)

While early semiconductor technologies utilized evaporation, it is not used in

CHEMICAL VAPOR DEPOSITION