First Round:( Max.

Marks:110)
This was a subjective paper of 12 Questions which were based on-Sequence Detection.
-Drawing Voltage & Current waveforms across a Capacitor in a Low Pass Filter
Configuration for a square wave input.
-Checking whether a clock can accommodate various propagation delays in a circuit
comprising of different gates with their respective delays along with some wiring delays
so that no violation occurs.
-Calculation of Maximum Input Clock Frequency so that no Setup/hold violation occurs
in a simple circuit.
-There was a question comprising of two diodes & a 90 degree phase shifter in some
configuration & output waveform had to be drawn for a square wave input. People found
this question quite confusing.
-Designing of a circuit so that output goes high for 1 clock period if the input in that
given clock period goes from high to low. This required some intuition( though it could
have been solved using FSM).
-A seemingly complex current mirror circuit with 4 NPN & 2 PNP BJTs. Currents had to
be found out in various branches.
-A very big Question on Buffering used for interfacing of Graphical LCD with different
datarates, pixel sizes,etc given & the best one out of the options had to be identified with
reason.
-Comparison of a non pipelined & a pipelined processor with data given like clock
frequency, various instructions' sizes, etc.
-A 4 stroke engine with input and output Valves with one opening in 1st stroke, one
closing in other stroke and in third stroke, a spark had to be generated. It was basically a
Moore Machine of 4 states with Input and Output valves changing in some fashion in
each stroke with a spark generated in third stroke.
-CMOS implementation of XNOR gate.
-A 5 stage cascaded PTL circuit with input voltage given at drain of 1st PTL and various
gate voltages given for each pass transistor. Voltage at each node had to be determined.
Second Round:(Technical Interview)
This was a technical interview Round. My interviewer was very polite & humble. He
seemed to be interested in me from the very beginning. He asked me some personal
Questions. He asked me thoroughly about my family. He was impressed by seeing that I
could play guitar. He said they have music club at FS & one interviewer among them was
its member also. He said he would be quite interested in me. He also asked about Quora
as I had mentioned reading on quora as a hobby. He said we people are not that much
updated with whats happening over internet.( He was Senior Design Engineer)
Then he started discussing Questions in which I hadn't scored well due to some silly
mistakes. After I answered he asked why did you do such mistakes. I said I was in haze as
I thought Question paper was lengthy. He sais decisions in life should not be made in
haze as they can prove to be turning point of your life.
Then he asked about projects. 1st project was a Game system(with 7 games) using
ATmega32 on a 8*8 LED matrix display with Keyboard(UART) interfacing. Coding was
done in CVAVR & Circuit simulation in proteus. He was impressed as the Project

covered various concepts of Embedded systems, Timer interrupts, Random number

generation, POV, etc. He asked me my role in Project & why I did this project to which I
replied that it was a Problem statement of last years 'Embedded Design' Event in our
college's techfest Avishkar and all the three team members did work on different games
and hardware circuitry was done with the combined Effort.(I didn't even tell him that we
stood 2nd in the event). He told me about some 'Avishkar' Event which is organized by
FS & it revolves around Embedded systems too.
This project was not discussed in detail.
2nd Project was Verilog based 8 bit RISC processor to which he again asked when and
why I did this project. I told him I did out of my own interest and I did primarily because
all the microprocessors I had studied before it(8085)
had instructions of varying size & hence architecture was not that Robust.
I told him that my processor could do each instruction in one clock(except 2 Memory
based instructions) and was quite efficient. He then asked me the definition of efficient.
To which I replied that architecture would be quite flexible if each instruction executes in
a similar fashion. And also Time required to execute a program/software in my processor
would be very less.
He was satisfied with the answer. Then he asked me to explain this project.
I started making block diagram starting from Program Counter, then Instruction
memory, Instruction register, Register File, ALU, Write back to RF. He asked me to
explain flow of some particular instruction through various stages which I answered. I
also told him complete instruction set Architecture of my processor which had 16
instructions (Arithmetic-logic register based, immediate, memory based, Jump and
branch, etc.) which I explained using various opcodes & control signals generated(a
control vector output of 15 bits from control unit to data unit). I mentioned different
possibilities for Program counter and fed them all into a mux. I explained him complete
block diagram. Then he asked me how I implemented it using Verilog. Then I told him
that I have implemented it using states. There would be 1 state associated with execution
of each instruction. Then he asked how did I implemented it in verilog if suppose I have
instruction AND and then ADD after that , then how the states would be decided. I
started writing code for moore fsm which i had used in my project code & explained to
him what he asked. He said that was the answer he wanted to hear.
Then he asked me some basic digital electronics questions like frequency divider by 2. I
drew D flip flop and connected Qbar to Din. He gave input frequency of 100Mhz asked to
check setup/hold violation at Din for same circuit(by first asking definition of both). I
started explaining it using clock to Qbar propagation delay . He stopped me as my
approach was correct.
He then asked me whether I had any Questions. Then I asked him What kind of work do
design engineers at FS deal with. He asked me back why I wanted to join FS. I answered
it by saying that I had immense interest in Digital Logic Design and that if FS gives this
opportunity to me then I would love to implement all the skills I have. He then gave 5
minute overview of various divisions where design engineers are alloted their projects.
Then I asked him whether any person in FS can request for a patent(some info
mentioned in company's ppt) if he has an idea. He said nowadays people of your age in
the company only contribute to majority of the patents. We people are just following
whats been told. Its you people who bring fresh ideas. Finally I asked him one more

question on knowing the primary reason behing merging of FS-NXP. He thought and
said Question is quite difficult(not easy to answer). Then he explained by saying that
NXP intersection FS was NULL. Hence there had to be union of both for the profit of
both organisations. I smiled at his witty answer and then the interview was over.
My technical interview was quite easy as compared to others. Others were given rigorous
circuit solving problems & were asked in-depth electronics & semiconductor related
concepts and their interviews going for more than 1 hour. mine was just for 35 minutes.
Next day I was called for another interview.
This interview was a complete surprise as I didn't know whether it was gonna be
technical or HR.

HR Interview:
Interviewer seemed to be in hurry. He asked me some rapidfire questions( like count the
names of all of your friends). About my qualities, what makes me different, about my
family, Guitar as a hobby. He asked me whether you'd prefer Noida or Bangalore. He
seemed to be satisfied with all the answers I gave. He said he'll meet me one more time.
Some people were called for two technical interviews, others for only one(myself
included).