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A fault is suddenly applied to the system and the sine wave suddenly becomes asymmetrical (the positive
and negative peaks are NOT equidistant from zero), and then returns to normal (symmetrical) after a few
cycles.
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The asymmetrical response to the fault is called DC Offset and it is a naturally occurring phenomenon of
the electrical system. Design engineers need to compensate for DC Offset when creating engineering
studies, high-voltage equipment must be able to interrupt the larger current created by DC offset, and
electrical personnel who look at oscilligraph reports can use DC Offset to recognize real faults (as we
discuss in our online training Course 1-1: The Three-Phase Power System). If this is such a normal part of
the electrical system, why is it so hard to find a good description of DC offset?
Here are some other descriptions from various textbooks:
The actual magnitude of the DC current is dependent on the point of the voltage wave where the fault
occurs and the circuit angle (X/R).
A symmetrical fault is a balanced fault with the sinusoidal waves being equal about their axes, and
represents a steady-state condition.
An asymmetrical fault displays a DC offset, transient in nature and decaying to the steady state of a
symmetrical fault after a period of time
Direct current offsetoccurs as a result of two natural laws:
1. Current cannot change instantaneously in an inductance and
2. Current must lag the applied voltage by the natural power-factor
You can get a more detailed description in Protective Relaying: Principles and Applications, second edition,
by J. Lewis Blackburn, but you have to have a very good understanding of power systems to understand all
of the nuances in the description.
When a current change occurs in the primary ac system, one or more of the three-phase currents will have
some dc offsetfrom the necessity to satisfy two conflicting requirements.
1. In a highly inductive network, the current wave must be near maximum when the voltage wave is
near zero; and
2. The actual current at the time of change is determined by prior network conditions
An excellent description is also provided in Protective Relaying for Power Generation Systems by Donald
Reimart:
At first glance, the occurrence of a DC current in an AC power system seems illogical. To understand its
existence, let us look at a few electrical rules learned in EE 101. First, in an inductive circuit, the current
lags the voltage by 90. If a fault occurs when the voltage is zero, the current must be at the positive or
negative maximum value. Secondly, the generator is a large inductor. The current in an inductor cannot
change instantaneously.
Lets break this explanation down into its components and look at a few different scenarios.
If you set your test-set to start with zero volts and zero amps and then apply a resistive condition (voltage
and current in-phase), the test-set would produce symmetrical waveforms that start at zero and are inphase as shown in the following image:
If we apply a purely inductive condition (current lags voltage by 90), the output looks something like this:
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Did you notice that the test-set cheated? It needed to maintain the pure inductive relationship of zero volts
equals maximum current, so it started the voltage at the first peak while the current started at the zerocrossing. It could also cheat the other way by starting the voltage at the zero-crossing while the current
starts at the peak:
The current cant make an instantaneous jump in the real power system like a test-set can, but it still needs
to maintain those two conflicting rules of electricity at the same time. Whenever the electrical system
experiences a large jump in current, a DC signal appears to create asymmetrical waveforms so that both of
our electrical rules can be true at the same time as shown in this image:
Do you remember the first rule? the current lags the voltage by 90 If we draw a vertical line through
the positive peaks of the voltage and current in a cycle from the example, we can see that the current is
lagging the voltage by 90. Therefore, our example with DC Offset satisfies the first rule.
Lets look at the second rule. If a fault occurs when the voltage is zero, the current must be at the positive
or negative maximum value. The current waveform has a zero-crossing AND is at its negative peak, so we
can see that the second rule is satisfied as well.
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DC Offset is necessary to maintain the basic laws of electricity at the initial moment when the current in the
system makes a sudden change, like what happens during a fault. However, the generators will be able to
react to the new system conditions, and the DC Offset will decrease over a few cycles until the waveform is
back to its normal symmetrical condition.
The size and duration of DC Offset depends on:
1. The ratio of reactance and resistance (X/R) of the circuit during a fault. This includes the generator
coils, and the equipment connecting the generator to the fault. The X/R ratio at the generator is
typically very high because the generator is almost a pure inductor, which means that the DC Offset
will be greater when the fault is closer to the generator. The system does not consist of pure
inductors, so the resistance in the X/R ratio grows as the distance between the fault and the
generator grows, which means the time constant will be larger. Also, the offset will be less extreme as
a result of an increase in source impedance.
2. The voltage magnitude at the exact moment of the fault. A fault at zero degrees on the A-Phase
voltage means that there is zero voltage when the fault is applied to the system. When the voltage is
zero in an inductive circuit, the current must be maximum. Therefore the maximum DC offset occurs
when the voltage is zero. Remember that when the A-Phase voltage is zero, the other two phases
will not be at zero, so different phases will react to the same fault differently.
3. The ability of the generator(s) to react to the fault and time necessary to stabilize the system.
Faults rarely occur at exactly zero degrees as shown in our previous examples. Faults can occur at any
point on a voltage waveform and different people may use different terms when describing this moment.
For example:
Manta Test Systems refer to it as the Fault Incidence Angle (FIA)
Omicron uses the term Fault Inception Mode/Angle
The amount of time that it takes to go from fault inception with DC offset to to steady-state symmetrical
waveforms can also have different descriptions:
Doble uses the Time Constant L/R setting
Manta Test Systems uses the setting System Time Constant
The next images show the same fault with different fault incidence, or fault inception, angles.
Fault Incidence at 0 with a 50ms Time Constant
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Did you notice that the three voltages experience the initial fault at different points on their waveforms?
And that the DC Offset introduced to each current waveform is different even though the fault happens in
the same moment for all phases? Do you see that the individual phases do not respond to the different
angles in the same way?
DC Offset is something that all relay testers should understand because it is a normal part of the electrical
system. You can use this information to properly interpret oscilligraph reports, or tweak your test plans so
that they will be more realistic and therefore, more reliable.
I hope that I was able to properly answer this question and help you understand this ever-present, but
seldom understood, aspect of the electrical system.
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Comments
Walt Slade says
December 16, 2015 at 10:06 am
Hey, Chris,
This article is very helpful. I had a question from a customer where they got RAW event reports out of
an SEL and didnt know why all those DC offsets were showing up. I referred him to your article. One
question: in point #1 above, you said The system does not consist of pure inductors, so the resistance
in the X/R ratio grows as the distance between the fault and the generator grows, which mean less DC
Offset will be required to meet all of the laws of electricity.
I wonder if it would be more precise to say: The system does not consist of pure inductors, so the
resistance in the X/R ratio grows as the distance between the fault and the generator grows, which
means the time constant will be larger. Also, the offset will be less extreme as a result of an increase
in source impedance.
Reply
karthik says
March 31, 2016 at 5:04 am
i has an DR from site, where the bus fault level is 40kA but the actual bus fault current was
more than 106kA, and the waveform appears completely distorted. what i am refering is from
generating station. So huch higher fault current is due to higher X/R ?
Reply
Edward says
September 13, 2016 at 8:05 pm
How about predominantly capacitive circuits near cap banks do we expect the DC offset in
Voltage Trace at current zero crossings? I believe I recall seeing something like that on fault records
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but I did not understand it so I had to let it go. Thank you for great explanation finally it makes sense
after staring at it in fault records for a decade
Additionally faults that occur on waveforms that are not at zero crossing induce traveling waves (step
surges) that show up as hi frequency oscillations on current and voltage traces. They show up if the
fault record is sampled at high enough frequency so that may partly explain distorted waveform.
Another reason for distorted waveform might have been severe CT core saturation due to DC offset
(in an attempted answer to kathiks question above).
Reply
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