Protocol Control Lane Regs reset values

PCIe modif Config offset() :

As per the TigerEDS Protocol Control upper Lane Register Pcie mode Config offset
(0x0c)
both and upper and lower lane reset value should be 0x0200_0001
For both flavour of CSW1
In RTL(ProtocolControlParams.vh)
parameter PRTCL_CTRL_PCIE_MODE+CNFG_DFLT

=32'h0000_0001

for the Same register for lower lane register it reset value getting 0x0000_0000
as per the EDS reset value should be 32'h0200_0001
pcie_Dwell_Timer offset(0x04) :
For all lanes(0-16) reset values should be same where lower lanes(0-7) its reset
values
behave differently always showing 0x0000_0000 where expecting 32'h0000-00064
sas_Dwell_Timer offset(0x08)
For all lanes(0-16) reset values should be same where lower lanes(0-7) its reset
values
behave differently always showing 0x0000_0000 where expecting 32'h0000-00064
Protocol Control Common reg :
Protocol control Refclk swtich count register offset(0x2c) :
When num_chan_sas_16 & num_chan_pcie_16 , upper and lower protocol control commo
n register are aCtive
when i check the reset values of protocol control low for refclk switch count re
gister(0x2c) 0x0000_0000 as per
rtl its 0x0000_0100

When num_chan_sas_8 & num_chan_pcie_16

Protocol ControlLane register : PCIe_mode_Config
Pcie_mode_config register is read/write register id not happening for all upper
lanes [8-15]
upper Protocol control common register :Receiver Electrical Idle Test Control :
Power_stagger_and_clock_and gating control register
SAS_Dwell_Timer :
PCIE_Dwell_Timer:

PCIe_mod_Config reset value are changed in latest data base

Unable to read/write Soft_Reset_Control_Register/ERRO
Task list :
1 . RAL testing for Protocol control register CSW0/CSW1 Flavour
2. Test mux Verification for protocol control register
3. MDIO Verfication for TigerCSW
4. SBus Master verfication for Aero(Kilkenny)
1.Apb2sbm bridge testing (All interrupts)
2.Firmware load over AXI
3.Firmware load axi sbus master
5. RAL Testing for all blocks(PUB/SASPhy/SASSdchannel/Protocol control register
)
1.reset testing
2.byte testing
3.read/write testing
4.read access : RO/W1C etc ...
5.simulataneously read write
6. TEst mux verification
6. I2c Verification
7. twi verificaiton

Hi Chris
During Ral testing when NUM_CHAN_SAS_16 & NUM_CHAN_PCIE_16 Most of the lowe lane
s are not working
properly due to multiple driver issue ,
Below Assign Satatment APB_PRDATA_int[160:32] 160th bit always driving x which i
s not using
This make Lower lane register driving always x not reading writing register
Snippet code Path: guinness/rtl/TopWrappers/TrimodeSerdes.v (Line number 607)
// PSEL[4:0] are all used by Sbus bridge, so replicated its response to lanes[4:
1] so APB read mux can find it.
assign APB_PRData_int[160:32] = {4{APB_PRData_int[31:0]}};
resoultion :
assign APB_PRData_int[159:32] = {4{APB_PRData_int[31:0]}};
Locally i tried with updated its working
Wave snap shot :

Ral testing for CSW0/CSW1

1.PUB
2.SASSDChannel
3.SasPhy
4.Protocol Control
5.Protocol LAne registers